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/linux/Documentation/devicetree/bindings/clock/
H A Dsprd,sc9860-clk.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/clock/sprd,sc9860-clk.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Orson Zhai <orsonzhai@gmail.com>
11 - Baolin Wang <baolin.wang7@gmail.com>
12 - Chunyan Zhang <zhang.lyra@gmail.com>
17 - sprd,sc9860-agcp-gate
18 - sprd,sc9860-aonsecure-clk
19 - sprd,sc9860-aon-gate
[all …]
H A Dsprd,ums512-clk.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/clock/sprd,ums512-clk.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Orson Zhai <orsonzhai@gmail.com>
12 - Baolin Wang <baolin.wang7@gmail.com>
13 - Chunyan Zhang <zhang.lyra@gmail.com>
18 - sprd,ums512-apahb-gate
19 - sprd,ums512-ap-clk
20 - sprd,ums512-aonapb-clk
[all …]
H A Dsprd,sc9863a-clk.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/clock/sprd,sc9863a-clk.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Orson Zhai <orsonzhai@gmail.com>
12 - Baolin Wang <baolin.wang7@gmail.com>
13 - Chunyan Zhang <zhang.lyra@gmail.com>
16 "#clock-cells":
21 - sprd,sc9863a-ap-clk
22 - sprd,sc9863a-aon-clk
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/linux/drivers/clk/rockchip/
H A Dclk-gate-grf.c1 // SPDX-License-Identifier: GPL-2.0-or-later
11 #include <linux/clk.h>
12 #include <linux/clk-provider.h>
15 #include "clk.h"
29 struct rockchip_gate_grf *gate = to_gate_grf(hw); in rockchip_gate_grf_enable() local
30 u32 val = !(gate->flags & CLK_GATE_SET_TO_DISABLE) ? BIT(gate->shift) : 0; in rockchip_gate_grf_enable()
31 u32 hiword = ((gate->flags & CLK_GATE_HIWORD_MASK) ? 1 : 0) << (gate->shift + 16); in rockchip_gate_grf_enable()
34 ret = regmap_update_bits(gate->regmap, gate->reg, in rockchip_gate_grf_enable()
35 hiword | BIT(gate->shift), hiword | val); in rockchip_gate_grf_enable()
42 struct rockchip_gate_grf *gate = to_gate_grf(hw); in rockchip_gate_grf_disable() local
[all …]
H A Dclk.c1 // SPDX-License-Identifier: GPL-2.0-or-later
7 * Author: Xing Zheng <zhengxing@rock-chips.com>
11 * samsung/clk.c
18 #include <linux/clk.h>
19 #include <linux/clk-provider.h>
26 #include "../clk-fractional-divider.h"
27 #include "clk.h"
33 * src1 --|--\
34 * |M |--[GATE]-[DIV]-
35 * src2 --|--/
[all …]
/linux/drivers/clk/tegra/
H A Dclk-periph-gate.c1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/clk-provider.h>
14 #include "clk.h"
18 /* Macros to assist peripheral gate clock */
19 #define read_enb(gate) \ argument
20 readl_relaxed(gate->clk_base + (gate->regs->enb_reg))
21 #define write_enb_set(val, gate) \ argument
22 writel_relaxed(val, gate->clk_base + (gate->regs->enb_set_reg))
23 #define write_enb_clr(val, gate) \ argument
24 writel_relaxed(val, gate->clk_base + (gate->regs->enb_clr_reg))
[all …]
H A Dclk-periph.c1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/clk.h>
7 #include <linux/clk-provider.h>
12 #include "clk.h"
17 const struct clk_ops *mux_ops = periph->mux_ops; in clk_periph_get_parent()
18 struct clk_hw *mux_hw = &periph->mux.hw; in clk_periph_get_parent()
22 return mux_ops->get_parent(mux_hw); in clk_periph_get_parent()
28 const struct clk_ops *mux_ops = periph->mux_ops; in clk_periph_set_parent()
29 struct clk_hw *mux_hw = &periph->mux.hw; in clk_periph_set_parent()
33 return mux_ops->set_parent(mux_hw, index); in clk_periph_set_parent()
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H A Dclk-tegra-periph.c1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/clk-provider.h>
13 #include <linux/clk/tegra.h>
15 #include "clk.h"
16 #include "clk-id.h"
130 #define MASK(x) (BIT(x) - 1)
229 #define GATE(_name, _parent_name, \ macro
773 GATE("rtc", "clk_32k", 4, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_rtc, 0),
774 GATE("timer", "clk_m", 5, 0, tegra_clk_timer, CLK_IS_CRITICAL),
775 GATE("isp", "clk_m", 23, 0, tegra_clk_isp, 0),
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/linux/arch/arm/boot/dts/intel/socfpga/
H A Dsocfpga.dtsi1 // SPDX-License-Identifier: GPL-2.0+
6 #include <dt-bindings/reset/altr,rst-mgr.h>
9 #address-cells = <1>;
10 #size-cells = <1>;
22 #address-cells = <1>;
23 #size-cells = <0>;
24 enable-method = "altr,socfpga-smp";
27 compatible = "arm,cortex-a9";
30 next-level-cache = <&L2>;
33 compatible = "arm,cortex-a9";
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/linux/drivers/clk/visconti/
H A Dclkc.c1 // SPDX-License-Identifier: GPL-2.0-only
11 #include <linux/clk-provider.h>
30 struct visconti_clk_gate *gate = to_visconti_clk_gate(hw); in visconti_gate_clk_is_enabled() local
31 u32 clk = BIT(gate->ck_idx); in visconti_gate_clk_is_enabled() local
34 regmap_read(gate->regmap, gate->ckon_offset, &val); in visconti_gate_clk_is_enabled()
35 return (val & clk) ? 1 : 0; in visconti_gate_clk_is_enabled()
40 struct visconti_clk_gate *gate = to_visconti_clk_gate(hw); in visconti_gate_clk_disable() local
41 u32 clk = BIT(gate->ck_idx); in visconti_gate_clk_disable() local
44 spin_lock_irqsave(gate->lock, flags); in visconti_gate_clk_disable()
47 spin_unlock_irqrestore(gate->lock, flags); in visconti_gate_clk_disable()
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/linux/drivers/clk/ti/
H A Dgate.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * OMAP gate clock support
7 * Tero Kristo <t-kristo@ti.com>
10 #include <linux/clk-provider.h>
15 #include <linux/clk/ti.h>
22 static int omap36xx_gate_clk_enable_with_hsdiv_restore(struct clk_hw *clk);
48 * omap36xx_gate_clk_enable_with_hsdiv_restore - enable clocks suffering
74 orig_v = ti_clk_ll_ops->clk_readl(&parent->reg); in omap36xx_gate_clk_enable_with_hsdiv_restore()
78 dummy_v ^= (1 << parent->shift); in omap36xx_gate_clk_enable_with_hsdiv_restore()
79 ti_clk_ll_ops->clk_writel(dummy_v, &parent->reg); in omap36xx_gate_clk_enable_with_hsdiv_restore()
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/linux/drivers/clk/renesas/
H A Drcar-cpg-lib.c1 // SPDX-License-Identifier: GPL-2.0
3 * R-Car Gen3 Clock Pulse Generator Library
5 * Copyright (C) 2015-2018 Glider bvba
8 * Based on clk-rcar-gen3.c
13 #include <linux/clk.h>
14 #include <linux/clk-provider.h>
23 #include "rcar-cpg-lib.h"
48 csn->saved = readl(csn->reg); in cpg_simple_notifier_call()
52 writel(csn->saved, csn->reg); in cpg_simple_notifier_call()
61 csn->nb.notifier_call = cpg_simple_notifier_call; in cpg_simple_notifier_register()
[all …]
/linux/drivers/clk/bcm/
H A Dclk-iproc-asiu.c1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/clk-provider.h>
13 #include "clk-iproc.h"
23 struct iproc_asiu_gate gate; member
38 struct iproc_asiu_clk *clk = to_asiu_clk(hw); in iproc_asiu_clk_enable() local
39 struct iproc_asiu *asiu = clk->asiu; in iproc_asiu_clk_enable()
43 if (clk->gate.offset == IPROC_CLK_INVALID_OFFSET) in iproc_asiu_clk_enable()
46 val = readl(asiu->gate_base + clk->gate.offset); in iproc_asiu_clk_enable()
47 val |= (1 << clk->gate.en_shift); in iproc_asiu_clk_enable()
48 writel(val, asiu->gate_base + clk->gate.offset); in iproc_asiu_clk_enable()
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/linux/drivers/clk/sunxi/
H A Dclk-a10-hosc.c1 // SPDX-License-Identifier: GPL-2.0-or-later
8 #include <linux/clk-provider.h>
19 struct clk *clk; in sun4i_osc_clk_setup() local
21 struct clk_gate *gate; in sun4i_osc_clk_setup() local
22 const char *clk_name = node->name; in sun4i_osc_clk_setup()
25 if (of_property_read_u32(node, "clock-frequency", &rate)) in sun4i_osc_clk_setup()
28 /* allocate fixed-rate and gate clock structs */ in sun4i_osc_clk_setup()
32 gate = kzalloc(sizeof(struct clk_gate), GFP_KERNEL); in sun4i_osc_clk_setup()
33 if (!gate) in sun4i_osc_clk_setup()
36 of_property_read_string(node, "clock-output-names", &clk_name); in sun4i_osc_clk_setup()
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H A Dclk-a20-gmac.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 * Copyright 2013 Chen-Yu Tsai
7 * Chen-Yu Tsai <wens@csie.org>
10 #include <linux/clk-provider.h>
29 * sun7i_a20_gmac_clk_setup - Setup function for A20/A31 GMAC clock module
34 * MII TX clock from PHY >-----|___________ _________|----> to GMAC core
35 * GMAC Int. RGMII TX clk >----|___________\__/__gate---|----> to PHY
36 * Ext. 125MHz RGMII TX clk >--|__divider__/ |
45 * select the appropriate source and gate/ungate the output to the PHY.
51 * driver then responds by auto-reparenting the clock.
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H A Dclk-a10-mod1.c1 // SPDX-License-Identifier: GPL-2.0-or-later
8 #include <linux/clk-provider.h>
23 struct clk *clk; in sun4i_mod1_clk_setup() local
25 struct clk_gate *gate; in sun4i_mod1_clk_setup() local
27 const char *clk_name = node->name; in sun4i_mod1_clk_setup()
39 gate = kzalloc(sizeof(*gate), GFP_KERNEL); in sun4i_mod1_clk_setup()
40 if (!gate) in sun4i_mod1_clk_setup()
43 of_property_read_string(node, "clock-output-names", &clk_name); in sun4i_mod1_clk_setup()
46 gate->reg = reg; in sun4i_mod1_clk_setup()
47 gate->bit_idx = SUN4I_MOD1_ENABLE; in sun4i_mod1_clk_setup()
[all …]
H A Dclk-sun8i-mbus.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright 2014 Chen-Yu Tsai
5 * Chen-Yu Tsai <wens@csie.org>
8 #include <linux/clk.h>
9 #include <linux/clk-provider.h>
28 const char *clk_name = node->name; in sun8i_a23_mbus_setup()
31 struct clk_gate *gate; in sun8i_a23_mbus_setup() local
33 struct clk *clk; in sun8i_a23_mbus_setup() local
43 pr_err("Could not get registers for sun8i-mbus-clk\n"); in sun8i_a23_mbus_setup()
55 gate = kzalloc(sizeof(*gate), GFP_KERNEL); in sun8i_a23_mbus_setup()
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H A Dclk-sun4i-pll3.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Maxime Ripard <maxime.ripard@free-electrons.com>
8 #include <linux/clk-provider.h>
23 const char *clk_name = node->name, *parent; in sun4i_a10_pll3_setup()
25 struct clk_gate *gate; in sun4i_a10_pll3_setup() local
28 struct clk *clk; in sun4i_a10_pll3_setup() local
31 of_property_read_string(node, "clock-output-names", &clk_name); in sun4i_a10_pll3_setup()
40 gate = kzalloc(sizeof(*gate), GFP_KERNEL); in sun4i_a10_pll3_setup()
41 if (!gate) in sun4i_a10_pll3_setup()
44 gate->reg = reg; in sun4i_a10_pll3_setup()
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H A Dclk-factors.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Adjustable factor-based clock implementation
8 #include <linux/clk-provider.h>
16 #include "clk-factors.h"
19 * DOC: basic adjustable factor-based clock
22 * prepare - clk_prepare only ensures that parents are prepared
23 * enable - clk_enable only ensures that parents are enabled
24 * rate - rate is adjustable.
25 * clk->rate = (parent->rate * N * (K + 1) >> P) / (M + 1)
26 * parent - fixed parent. No clk_set_parent support
[all …]
H A Dclk-a10-ve.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright 2015 Chen-Yu Tsai
5 * Chen-Yu Tsai <wens@csie.org>
8 #include <linux/clk-provider.h>
12 #include <linux/reset-controller.h>
24 * sunxi_ve_reset... - reset bit in ve clk registers handling
42 spin_lock_irqsave(data->lock, flags); in sunxi_ve_reset_assert()
44 reg = readl(data->reg); in sunxi_ve_reset_assert()
45 writel(reg & ~BIT(SUN4I_VE_RESET), data->reg); in sunxi_ve_reset_assert()
47 spin_unlock_irqrestore(data->lock, flags); in sunxi_ve_reset_assert()
[all …]
/linux/drivers/clk/davinci/
H A Dda8xx-cfgchip.c1 // SPDX-License-Identifier: GPL-2.0
3 * Clock driver for DA8xx/AM17xx/AM18xx/OMAP-L13x CFGCHIP
8 #include <linux/clk-provider.h>
9 #include <linux/clk.h>
12 #include <linux/mfd/da8xx-cfgchip.h>
15 #include <linux/platform_data/clk-da8xx-cfgchip.h>
21 /* --- Gate clocks --- */
44 struct da8xx_cfgchip_gate_clk *clk = to_da8xx_cfgchip_gate_clk(hw); in da8xx_cfgchip_gate_clk_enable() local
46 return regmap_write_bits(clk->regmap, clk->reg, clk->mask, clk->mask); in da8xx_cfgchip_gate_clk_enable()
51 struct da8xx_cfgchip_gate_clk *clk = to_da8xx_cfgchip_gate_clk(hw); in da8xx_cfgchip_gate_clk_disable() local
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H A Dpll.c1 // SPDX-License-Identifier: GPL-2.0
7 * Based on arch/arm/mach-davinci/clock.c
8 * Copyright (C) 2006-2007 Texas Instruments.
9 * Copyright (C) 2008-2009 Deep Root Systems, LLC
12 #include <linux/clk-provider.h>
13 #include <linux/clk.h>
14 #include <linux/clk/davinci.h>
78 * OMAP-L138 system reference guide recommends a wait for 4 OSCIN/CLKIN
85 /* From OMAP-L138 datasheet table 6-4. Units are micro seconds */
89 * From OMAP-L138 datasheet table 6-4; assuming prediv = 1, sqrt(pllm) = 4
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/linux/sound/soc/mediatek/mt8186/
H A Dmt8186-audsys-clk.c1 // SPDX-License-Identifier: GPL-2.0
3 // mt8186-audsys-clk.h -- Mediatek 8186 audsys clock control
8 #include <linux/clk.h>
9 #include <linux/clk-provider.h>
11 #include "mt8186-afe-common.h"
12 #include "mt8186-audsys-clk.h"
13 #include "mt8186-audsys-clkid.h"
14 #include "mt8186-reg.h"
90 struct mt8186_afe_private *afe_priv = afe->platform_priv; in mt8186_audsys_clk_unregister()
91 struct clk *clk; in mt8186_audsys_clk_unregister() local
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/linux/drivers/clk/
H A Dclk-aspeed.c1 // SPDX-License-Identifier: GPL-2.0+
4 #define pr_fmt(fmt) "clk-aspeed: " fmt
13 #include <dt-bindings/clock/aspeed-clock.h>
15 #include "clk-aspeed.h"
48 /* clk rst name parent flags */
49 [ASPEED_CLK_GATE_ECLK] = { 0, 6, "eclk-gate", "eclk", 0 }, /* Video Engine */
50 [ASPEED_CLK_GATE_GCLK] = { 1, 7, "gclk-gate", NULL, 0 }, /* 2D engine */
51 [ASPEED_CLK_GATE_MCLK] = { 2, -1, "mclk-gate", "mpll", CLK_IS_CRITICAL }, /* SDRAM */
52 [ASPEED_CLK_GATE_VCLK] = { 3, -1, "vclk-gate", NULL, 0 }, /* Video Capture */
53 [ASPEED_CLK_GATE_BCLK] = { 4, 8, "bclk-gate", "bclk", CLK_IS_CRITICAL }, /* PCIe/PCI */
[all …]
/linux/drivers/clk/pistachio/
H A Dclk.c1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/clk.h>
7 #include <linux/clk-provider.h>
13 #include "clk.h"
24 p->clk_data.clks = kcalloc(num_clks, sizeof(struct clk *), GFP_KERNEL); in pistachio_clk_alloc_provider()
25 if (!p->clk_data.clks) in pistachio_clk_alloc_provider()
27 p->clk_data.clk_num = num_clks; in pistachio_clk_alloc_provider()
28 p->node = node; in pistachio_clk_alloc_provider()
29 p->base = of_iomap(node, 0); in pistachio_clk_alloc_provider()
30 if (!p->base) { in pistachio_clk_alloc_provider()
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