16a3a6c7aSCixi Geng# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 26a3a6c7aSCixi Geng# Copyright 2022 Unisoc Inc. 36a3a6c7aSCixi Geng%YAML 1.2 46a3a6c7aSCixi Geng--- 5*32671977SRob Herring$id: http://devicetree.org/schemas/clock/sprd,ums512-clk.yaml# 6*32671977SRob Herring$schema: http://devicetree.org/meta-schemas/core.yaml# 76a3a6c7aSCixi Geng 86a3a6c7aSCixi Gengtitle: UMS512 Soc clock controller 96a3a6c7aSCixi Geng 106a3a6c7aSCixi Gengmaintainers: 116a3a6c7aSCixi Geng - Orson Zhai <orsonzhai@gmail.com> 126a3a6c7aSCixi Geng - Baolin Wang <baolin.wang7@gmail.com> 136a3a6c7aSCixi Geng - Chunyan Zhang <zhang.lyra@gmail.com> 146a3a6c7aSCixi Geng 156a3a6c7aSCixi Gengproperties: 166a3a6c7aSCixi Geng compatible: 176a3a6c7aSCixi Geng enum: 186a3a6c7aSCixi Geng - sprd,ums512-apahb-gate 196a3a6c7aSCixi Geng - sprd,ums512-ap-clk 206a3a6c7aSCixi Geng - sprd,ums512-aonapb-clk 216a3a6c7aSCixi Geng - sprd,ums512-pmu-gate 226a3a6c7aSCixi Geng - sprd,ums512-g0-pll 236a3a6c7aSCixi Geng - sprd,ums512-g2-pll 246a3a6c7aSCixi Geng - sprd,ums512-g3-pll 256a3a6c7aSCixi Geng - sprd,ums512-gc-pll 266a3a6c7aSCixi Geng - sprd,ums512-aon-gate 276a3a6c7aSCixi Geng - sprd,ums512-audcpapb-gate 286a3a6c7aSCixi Geng - sprd,ums512-audcpahb-gate 296a3a6c7aSCixi Geng - sprd,ums512-gpu-clk 306a3a6c7aSCixi Geng - sprd,ums512-mm-clk 316a3a6c7aSCixi Geng - sprd,ums512-mm-gate-clk 326a3a6c7aSCixi Geng - sprd,ums512-apapb-gate 336a3a6c7aSCixi Geng 346a3a6c7aSCixi Geng "#clock-cells": 356a3a6c7aSCixi Geng const: 1 366a3a6c7aSCixi Geng 376a3a6c7aSCixi Geng clocks: 386a3a6c7aSCixi Geng minItems: 1 396a3a6c7aSCixi Geng maxItems: 4 406a3a6c7aSCixi Geng description: | 416a3a6c7aSCixi Geng The input parent clock(s) phandle for the clock, only list 426a3a6c7aSCixi Geng fixed clocks which are declared in devicetree. 436a3a6c7aSCixi Geng 446a3a6c7aSCixi Geng clock-names: 456a3a6c7aSCixi Geng minItems: 1 466a3a6c7aSCixi Geng items: 476a3a6c7aSCixi Geng - const: ext-26m 486a3a6c7aSCixi Geng - const: ext-32k 496a3a6c7aSCixi Geng - const: ext-4m 506a3a6c7aSCixi Geng - const: rco-100m 516a3a6c7aSCixi Geng 526a3a6c7aSCixi Geng reg: 536a3a6c7aSCixi Geng maxItems: 1 546a3a6c7aSCixi Geng 556a3a6c7aSCixi Gengrequired: 566a3a6c7aSCixi Geng - compatible 576a3a6c7aSCixi Geng - '#clock-cells' 586a3a6c7aSCixi Geng - reg 596a3a6c7aSCixi Geng 606a3a6c7aSCixi GengadditionalProperties: false 616a3a6c7aSCixi Geng 626a3a6c7aSCixi Gengexamples: 636a3a6c7aSCixi Geng - | 646a3a6c7aSCixi Geng ap_clk: clock-controller@20200000 { 656a3a6c7aSCixi Geng compatible = "sprd,ums512-ap-clk"; 666a3a6c7aSCixi Geng reg = <0x20200000 0x1000>; 676a3a6c7aSCixi Geng clocks = <&ext_26m>; 686a3a6c7aSCixi Geng clock-names = "ext-26m"; 696a3a6c7aSCixi Geng #clock-cells = <1>; 706a3a6c7aSCixi Geng }; 716a3a6c7aSCixi Geng... 72