Lines Matching +full:clk +full:- +full:gate
1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/clk-provider.h>
13 #include <linux/clk/tegra.h>
15 #include "clk.h"
16 #include "clk-id.h"
130 #define MASK(x) (BIT(x) - 1)
229 #define GATE(_name, _parent_name, \ macro
773 GATE("rtc", "clk_32k", 4, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_rtc, 0),
774 GATE("timer", "clk_m", 5, 0, tegra_clk_timer, CLK_IS_CRITICAL),
775 GATE("isp", "clk_m", 23, 0, tegra_clk_isp, 0),
776 GATE("vcp", "clk_m", 29, 0, tegra_clk_vcp, 0),
777 GATE("ahbdma", "hclk", 33, 0, tegra_clk_ahbdma, 0),
778 GATE("apbdma", "pclk", 34, 0, tegra_clk_apbdma, 0),
779 GATE("kbc", "clk_32k", 36, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_kbc, 0),
780 GATE("fuse", "clk_m", 39, TEGRA_PERIPH_ON_APB, tegra_clk_fuse, 0),
781 GATE("fuse_burn", "clk_m", 39, TEGRA_PERIPH_ON_APB, tegra_clk_fuse_burn, 0),
782 GATE("kfuse", "clk_m", 40, TEGRA_PERIPH_ON_APB, tegra_clk_kfuse, 0),
783 GATE("apbif", "clk_m", 107, TEGRA_PERIPH_ON_APB, tegra_clk_apbif, 0),
784 GATE("hda2hdmi", "clk_m", 128, TEGRA_PERIPH_ON_APB, tegra_clk_hda2hdmi, 0),
785 GATE("bsea", "clk_m", 62, 0, tegra_clk_bsea, 0),
786 GATE("bsev", "clk_m", 63, 0, tegra_clk_bsev, 0),
787 GATE("mipi-cal", "clk72mhz", 56, 0, tegra_clk_mipi_cal, 0),
788 GATE("usbd", "clk_m", 22, 0, tegra_clk_usbd, 0),
789 GATE("usb2", "clk_m", 58, 0, tegra_clk_usb2, 0),
790 GATE("usb3", "clk_m", 59, 0, tegra_clk_usb3, 0),
791 GATE("csi", "pll_p_out3", 52, 0, tegra_clk_csi, 0),
792 GATE("afi", "mselect", 72, 0, tegra_clk_afi, 0),
793 GATE("csus", "clk_m", 92, TEGRA_PERIPH_NO_RESET, tegra_clk_csus, 0),
794 GATE("dds", "clk_m", 150, TEGRA_PERIPH_ON_APB, tegra_clk_dds, 0),
795 GATE("dp2", "clk_m", 152, TEGRA_PERIPH_ON_APB, tegra_clk_dp2, 0),
796 GATE("dtv", "clk_m", 79, TEGRA_PERIPH_ON_APB, tegra_clk_dtv, 0),
797 GATE("xusb_host", "xusb_host_src", 89, 0, tegra_clk_xusb_host, 0),
798 GATE("xusb_ss", "xusb_ss_src", 156, 0, tegra_clk_xusb_ss, 0),
799 GATE("xusb_dev", "xusb_dev_src", 95, 0, tegra_clk_xusb_dev, 0),
800 GATE("emc", "emc_mux", 57, 0, tegra_clk_emc, CLK_IS_CRITICAL),
801 GATE("sata_cold", "clk_m", 129, TEGRA_PERIPH_ON_APB, tegra_clk_sata_cold, 0),
802 GATE("ispa", "isp", 23, 0, tegra_clk_ispa, 0),
803 GATE("ispb", "isp", 3, 0, tegra_clk_ispb, 0),
804 GATE("vim2_clk", "clk_m", 11, 0, tegra_clk_vim2_clk, 0),
805 GATE("pcie", "clk_m", 70, 0, tegra_clk_pcie, 0),
806 GATE("gpu", "pll_ref", 184, 0, tegra_clk_gpu, 0),
807 GATE("pllg_ref", "pll_ref", 189, 0, tegra_clk_pll_g_ref, 0),
808 GATE("hsic_trk", "usb2_hsic_trk", 209, TEGRA_PERIPH_NO_RESET, tegra_clk_hsic_trk, 0),
809 GATE("usb2_trk", "usb2_hsic_trk", 210, TEGRA_PERIPH_NO_RESET, tegra_clk_usb2_trk, 0),
810 GATE("xusb_gate", "osc", 143, 0, tegra_clk_xusb_gate, 0),
811 GATE("pll_p_out_cpu", "pll_p", 223, 0, tegra_clk_pll_p_out_cpu, 0),
812 GATE("pll_p_out_adsp", "pll_p", 187, 0, tegra_clk_pll_p_out_adsp, 0),
813 GATE("apb2ape", "clk_m", 107, 0, tegra_clk_apb2ape, 0),
814 GATE("cec", "pclk", 136, 0, tegra_clk_cec, 0),
815 GATE("iqc1", "clk_m", 221, 0, tegra_clk_iqc1, 0),
816 GATE("iqc2", "clk_m", 220, 0, tegra_clk_iqc1, 0),
817 GATE("pll_a_out_adsp", "pll_a", 188, 0, tegra_clk_pll_a_out_adsp, 0),
818 GATE("pll_a_out0_out_adsp", "pll_a", 188, 0, tegra_clk_pll_a_out0_out_adsp, 0),
819 GATE("adsp", "aclk", 199, 0, tegra_clk_adsp, 0),
820 GATE("adsp_neon", "aclk", 218, 0, tegra_clk_adsp_neon, 0),
864 struct clk *clk; in periph_clk_init() local
865 struct clk **dt_clk; in periph_clk_init()
873 dt_clk = tegra_lookup_dt_id(data->clk_id, tegra_clks); in periph_clk_init()
877 bank = get_reg_bank(data->periph.gate.clk_num); in periph_clk_init()
881 data->periph.gate.regs = bank; in periph_clk_init()
882 clk = tegra_clk_register_periph_data(clk_base, data); in periph_clk_init()
883 *dt_clk = clk; in periph_clk_init()
891 struct clk *clk; in gate_clk_init() local
892 struct clk **dt_clk; in gate_clk_init()
899 dt_clk = tegra_lookup_dt_id(data->clk_id, tegra_clks); in gate_clk_init()
903 clk = tegra_clk_register_periph_gate(data->name, in gate_clk_init()
904 data->p.parent_name, data->periph.gate.flags, in gate_clk_init()
905 clk_base, data->flags, in gate_clk_init()
906 data->periph.gate.clk_num, in gate_clk_init()
908 *dt_clk = clk; in gate_clk_init()
916 struct clk *clk; in div_clk_init() local
917 struct clk **dt_clk; in div_clk_init()
924 dt_clk = tegra_lookup_dt_id(data->clk_id, tegra_clks); in div_clk_init()
928 clk = tegra_clk_register_divider(data->name, in div_clk_init()
929 data->p.parent_name, clk_base + data->offset, in div_clk_init()
930 data->flags, data->periph.divider.flags, in div_clk_init()
931 data->periph.divider.shift, in div_clk_init()
932 data->periph.divider.width, in div_clk_init()
933 data->periph.divider.frac_width, in div_clk_init()
934 data->periph.divider.lock); in div_clk_init()
935 *dt_clk = clk; in div_clk_init()
943 struct clk *clk; in init_pllp() local
944 struct clk **dt_clk; in init_pllp()
950 clk = tegra_clk_register_pll("pll_p", "pll_ref", clk_base, in init_pllp()
952 clk_register_clkdev(clk, "pll_p", NULL); in init_pllp()
953 *dt_clk = clk; in init_pllp()
961 dt_clk = tegra_lookup_dt_id(data->clk_id, tegra_clks); in init_pllp()
965 clk = tegra_clk_register_divider(data->div_name, "pll_p", in init_pllp()
966 clk_base + data->offset, 0, data->div_flags, in init_pllp()
967 data->div_shift, 8, 1, data->lock); in init_pllp()
968 clk = tegra_clk_register_pll_out(data->pll_out_name, in init_pllp()
969 data->div_name, clk_base + data->offset, in init_pllp()
970 data->rst_shift + 1, data->rst_shift, in init_pllp()
972 data->lock); in init_pllp()
973 *dt_clk = clk; in init_pllp()
981 * CPU, register a gate clock "pll_p_out_cpu" for this gating in init_pllp()
983 * re-parenting CPU off from "pll_p_out4" the PLLP branching to in init_pllp()
986 clk = tegra_clk_register_divider("pll_p_out4_div", in init_pllp()
992 clk = tegra_clk_register_pll_out("pll_p_out4", in init_pllp()
997 *dt_clk = clk; in init_pllp()
1004 clk = clk_register_gate(NULL, "pll_p_out_hsio", "pll_p", in init_pllp()
1007 *dt_clk = clk; in init_pllp()
1013 clk = clk_register_gate(NULL, "pll_p_out_xusb", in init_pllp()
1017 clk_register_clkdev(clk, "pll_p_out_xusb", NULL); in init_pllp()
1018 *dt_clk = clk; in init_pllp()