Merge remote-tracking branch 'drm/drm-next' into msm-next

Back-merge drm-next to (indirectly) get arm-smmu updates for making
stall-on-fault more reliable.

Signed-off-by: Rob Clark <robin.clark@oss

Merge remote-tracking branch 'drm/drm-next' into msm-next

Back-merge drm-next to (indirectly) get arm-smmu updates for making
stall-on-fault more reliable.

Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>

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Merge drm/drm-next into drm-misc-next

Backmerging to forward to v6.16-rc1

Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de>

Merge drm/drm-next into drm-xe-next

Backmerging to bring in 6.16

Signed-off-by: Thomas Hellström <thomas.hellstrom@linux.intel.com>

Merge drm/drm-next into drm-intel-next

Sync to v6.16-rc1, among other things to get the fixed size GENMASK_U*()
and BIT_U*() macros.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>

Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux

Pull clk updates from Stephen Boyd:
"This has been a semi-quiet cycle. The core framework remains unchanged
th

Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux

Pull clk updates from Stephen Boyd:
"This has been a semi-quiet cycle. The core framework remains unchanged
this time around.

In terms of shiny new code though, we have support for the SpacemiT K1
SoC, Sophgo SG2044, and T-HEAD TH1520 VO clk drivers joining the usual
silicon players like Qualcomm, Samsung, Allwinner, and Renesas.

Surprisingly, the Qualcomm pile was smaller than usual but that is
likely because they put one SoC support inside a driver for a
different SoC that is very similar.

Other than all those new clk drivers there are the usual clk data
updates to fix parents, frequency tables, and add missing clks along
with some Kconfig changes to make compile testing simpler and even
more DT binding conversions to boot.

The exciting part is still the new SoC support like SpacemiT and
Sophgo support though, which really dominate the diffstat because they
introduce a whole new silicon vendor clk driver.

New Drivers:
- Camera clock controller driver for Qualcomm QCS8300
- DE (display engine) 3.3 clocks on Allwinner H616
- Samsung ExynosAutov920 CPU cluster CL0, CL1 and CL2 clock controllers
- Video Output (VO) subsystem clk controller in the T-HEAD TH1520 SoC
- Clock driver for Sophgo SG2044
- Clock driver for SpacemiT K1 SoC
- Renesas RZ/V2N (R9A09G056) SoC clk driver

Updates:
- Correct data in various SoC clk drivers
- Allow clkaN to be optional in the Qualcomm RPMh clock controller
driver if command db doesn't define it
- Change Kconfig options to not enable by default during compile
testing
- Add missing clks in various SoC clk drivers
- Remove some duplicate clk DT bindings and convert some more to
YAML"

* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (93 commits)
clk: qcom: gcc-x1e80100: Set FORCE MEM CORE for UFS clocks
clk: qcom: gcc: Set FORCE_MEM_CORE_ON for gcc_ufs_axi_clk for 8650/8750
clk: qcom: rpmh: make clkaN optional
clk: qcom: Add support for Camera Clock Controller on QCS8300
clk: rockchip: rk3528: add slab.h header include
clk: rockchip: rk3576: add missing slab.h include
clk: meson: Do not enable by default during compile testing
clk: meson-g12a: add missing fclk_div2 to spicc
clk: qcom: gcc-msm8939: Fix mclk0 & mclk1 for 24 MHz
clk: rockchip: rename gate-grf clk file
clk: rockchip: rename branch_muxgrf to branch_grf_mux
clk: sunxi-ng: ccu: add Display Engine 3.3 (DE33) support
dt-bindings: allwinner: add H616 DE33 clock binding
clk: samsung: correct clock summary for hsi1 block
dt-bindings: clock: add SM6350 QCOM video clock bindings
clk: rockchip: Pass NULL as reg pointer when registering GRF MMC clocks
clk: sunxi-ng: h616: Add LVDS reset for LCD TCON
dt-bindings: clock: sun50i-h616-ccu: Add LVDS reset
clk: rockchip: rk3036: mark ddrphy as critical
clk: rockchip: rk3036: fix implementation of usb480m clock mux
...

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Merge branches 'clk-amlogic', 'clk-allwinner', 'clk-rockchip' and 'clk-qcom' into clk-next

* clk-amlogic:
clk: meson: Do not enable by default during compile testing
clk: meson-g12a: add missing

Merge branches 'clk-amlogic', 'clk-allwinner', 'clk-rockchip' and 'clk-qcom' into clk-next

* clk-amlogic:
clk: meson: Do not enable by default during compile testing
clk: meson-g12a: add missing fclk_div2 to spicc

* clk-allwinner:
clk: sunxi-ng: ccu: add Display Engine 3.3 (DE33) support
dt-bindings: allwinner: add H616 DE33 clock binding
clk: sunxi-ng: h616: Add LVDS reset for LCD TCON
dt-bindings: clock: sun50i-h616-ccu: Add LVDS reset
clk: sunxi: Do not enable by default during compile testing
clk: sunxi-ng: Do not enable by default during compile testing

* clk-rockchip:
clk: rockchip: rk3528: add slab.h header include
clk: rockchip: rk3576: add missing slab.h include
clk: rockchip: rename gate-grf clk file
clk: rockchip: rename branch_muxgrf to branch_grf_mux
clk: rockchip: Pass NULL as reg pointer when registering GRF MMC clocks
clk: rockchip: rk3036: mark ddrphy as critical
clk: rockchip: rk3036: fix implementation of usb480m clock mux
dt-bindings: clock: rk3036: add SCLK_USB480M clock-id
clk: rockchip: rk3528: Add SD/SDIO tuning clocks in GRF region
clk: rockchip: Support MMC clocks in GRF region
dt-bindings: clock: Add GRF clock definition for RK3528
clk: rockchip: add GATE_GRFs for SAI MCLKOUT to rk3576
clk: rockchip: introduce GRF gates
clk: rockchip: introduce auxiliary GRFs
dt-bindings: clock: rk3576: add IOC gated clocks
clk: rockchip: rk3568: Add PLL rate for 33.3MHz
clk: rockchip: Drop empty init callback for rk3588 PLL type
clk: rockchip: rk3588: Add PLL rate for 1500 MHz

* clk-qcom:
clk: qcom: gcc-x1e80100: Set FORCE MEM CORE for UFS clocks
clk: qcom: gcc: Set FORCE_MEM_CORE_ON for gcc_ufs_axi_clk for 8650/8750
clk: qcom: rpmh: make clkaN optional
clk: qcom: Add support for Camera Clock Controller on QCS8300
clk: qcom: gcc-msm8939: Fix mclk0 & mclk1 for 24 MHz
dt-bindings: clock: add SM6350 QCOM video clock bindings
clk: qcom: gpucc-sm6350: Add *_wait_val values for GDSCs
clk: qcom: gcc-sm6350: Add *_wait_val values for GDSCs
clk: qcom: dispcc-sm6350: Add *_wait_val values for GDSCs
clk: qcom: camcc-sm6350: Add *_wait_val values for GDSCs
clk: qcom: Fix missing error check for dev_pm_domain_attach()

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Merge tag 'v6.16-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-rockchip

Pull Rockchip clk driver updates from Heiko Stuebner:

- Ability to handle di

Merge tag 'v6.16-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-rockchip

Pull Rockchip clk driver updates from Heiko Stuebner:

- Ability to handle different "General Register Files" syscons, not
just a single system-one, plus ability to model individual gates
found there.

- For whatever reason Rockchip also moved the mmc-phase-clocks from the
clock-unit for the GRF on some newer socs like the rk3528 (before
moving them fully to the mmc controller itself on the rk3576), so add
a new clock-variant for the phases, reusing the new GRF handling.

- The old rk3036 got real handling of the usb480m mux and some PLL
rates were added.

* tag 'v6.16-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
clk: rockchip: rk3528: add slab.h header include
clk: rockchip: rk3576: add missing slab.h include
clk: rockchip: rename gate-grf clk file
clk: rockchip: rename branch_muxgrf to branch_grf_mux
clk: rockchip: Pass NULL as reg pointer when registering GRF MMC clocks
clk: rockchip: rk3036: mark ddrphy as critical
clk: rockchip: rk3036: fix implementation of usb480m clock mux
dt-bindings: clock: rk3036: add SCLK_USB480M clock-id
clk: rockchip: rk3528: Add SD/SDIO tuning clocks in GRF region
clk: rockchip: Support MMC clocks in GRF region
dt-bindings: clock: Add GRF clock definition for RK3528
clk: rockchip: add GATE_GRFs for SAI MCLKOUT to rk3576
clk: rockchip: introduce GRF gates
clk: rockchip: introduce auxiliary GRFs
dt-bindings: clock: rk3576: add IOC gated clocks
clk: rockchip: rk3568: Add PLL rate for 33.3MHz
clk: rockchip: Drop empty init callback for rk3588 PLL type
clk: rockchip: rk3588: Add PLL rate for 1500 MHz

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clk: rockchip: rename gate-grf clk file

All Rockchip clock types live in files starting with clk-foo, so rename
the newly added gate-grf-clock to follow that scheme.

Signed-off-by: Heiko Stuebner <

clk: rockchip: rename gate-grf clk file

All Rockchip clock types live in files starting with clk-foo, so rename
the newly added gate-grf-clock to follow that scheme.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Link: https://lore.kernel.org/r/20250508182752.1925313-3-heiko@sntech.de

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