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/freebsd/sys/contrib/device-tree/Bindings/clock/
H A Dsprd,sc9860-clk.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/clock/sprd,sc9860-clk.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Orson Zhai <orsonzhai@gmail.com>
11 - Baolin Wang <baolin.wang7@gmail.com>
12 - Chunyan Zhang <zhang.lyra@gmail.com>
17 - sprd,sc9860-agcp-gate
18 - sprd,sc9860-aonsecure-clk
19 - sprd,sc9860-aon-gate
[all …]
H A Dsprd,sc9860-clk.txt2 ------------------------
5 - compatible: should contain the following compatible strings:
6 - "sprd,sc9860-pmu-gate"
7 - "sprd,sc9860-pll"
8 - "sprd,sc9860-ap-clk"
9 - "sprd,sc9860-aon-prediv"
10 - "sprd,sc9860-apahb-gate"
11 - "sprd,sc9860-aon-gate"
12 - "sprd,sc9860-aonsecure-clk"
13 - "sprd,sc9860-agcp-gate"
[all …]
H A Dsprd,ums512-clk.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/clock/sprd,ums512-clk.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Orson Zhai <orsonzhai@gmail.com>
12 - Baolin Wang <baolin.wang7@gmail.com>
13 - Chunyan Zhang <zhang.lyra@gmail.com>
18 - sprd,ums512-apahb-gate
19 - sprd,ums512-ap-clk
20 - sprd,ums512-aonapb-clk
[all …]
H A Dsprd,sc9863a-clk.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/clock/sprd,sc9863a-cl
[all...]
H A Daltr_socfpga.txt5 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
8 - compatible : shall be one of the following:
9 "altr,socfpga-pll-clock" - for a PLL clock
10 "altr,socfpga-perip-clock" - The peripheral clock divided from the
12 "altr,socfpga-gate-clk" - Clocks that directly feed peripherals and
15 - reg : shall be the control register offset from CLOCK_MANAGER's base for the clock.
16 - clocks : shall be the input parent clock phandle for the clock. This is
18 - #clock-cells : from common clock binding, shall be set to 0.
21 - fixed-divider : If clocks have a fixed divider value, use this property.
22 - clk-gate : For "socfpga-gate-clk", clk-gate contains the gating register
[all …]
/freebsd/sys/contrib/device-tree/src/arm/intel/socfpga/
H A Dsocfpga.dtsi1 // SPDX-License-Identifier: GPL-2.0+
6 #include <dt-bindings/reset/altr,rst-mgr.h>
9 #address-cells = <1>;
10 #size-cells = <1>;
22 #address-cells = <1>;
23 #size-cells = <0>;
24 enable-metho
[all...]
H A Dsocfpga_arria10.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/reset/altr,rst-mgr-a10.h>
10 #address-cells = <1>;
11 #size-cells = <1>;
14 #address-cells = <1>;
15 #size-cells = <0>;
16 enable-method = "altr,socfpga-a10-smp";
19 compatible = "arm,cortex-a9";
22 next-level-cache = <&L2>;
[all …]
/freebsd/sys/arm/nvidia/tegra124/
H A Dtegra124_clk_per.c1 /*-
36 #include <dev/clk/clk.h>
38 #include <dt-bindings/clock/tegra124-car.h>
76 #define GATE(_id, cname, plist, _idx) \ macro
213 /* bank L -> 0-31 */
214 /* GATE(CPU, "cpu", "clk_m", L(0)), */
215 GATE(ISPB, "ispb", "clk_m", L(3)),
216 GATE(RTC, "rtc", "clk_s", L(4)),
217 GATE(TIMER, "timer", "clk_m", L(5)),
218 GATE(UARTA, "uarta", "pc_uarta" , L(6)),
[all …]
/freebsd/sys/arm64/nvidia/tegra210/
H A Dtegra210_clk_per.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
37 #include <dev/clk/clk.h>
39 #include <dt-bindings/clock/tegra210-car.h>
40 #include <dt-bindings/reset/tegra210-car.h>
71 #define GATE(_id, cname, plist, _idx) \ macro
308 /* bank L -> 0-31 */
309 GATE(ISPB, "ispb", "clk_m", L(3)),
310 GATE(RTC, "rtc", "clk_s", L(4)),
311 GATE(TIMER, "timer", "clk_m", L(5)),
[all …]
/freebsd/sys/dev/clk/allwinner/
H A Dccu_d1.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
46 #include <dev/clk/clk_div.h>
47 #include <dev/clk/clk_fixed.h>
48 #include <dev/clk/clk_mux.h>
50 #include <dev/clk/allwinner/aw_ccung.h>
52 #include <dt-bindings/clock/sun20i-d1-ccu.h>
53 #include <dt-bindings/reset/sun20i-d1-ccu.h>
125 CCU_GATE(CLK_BUS_DE, "bus-de", "psi-ahb", 0x60C, 0)
126 CCU_GATE(CLK_BUS_DI, "bus-di", "psi-ahb", 0x62C, 0)
[all …]
H A Dccu_a31.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
41 #include <dev/clk/clk_div.h>
42 #include <dev/clk/clk_fixed.h>
43 #include <dev/clk/clk_mux.h>
45 #include <dev/clk/allwinner/aw_ccung.h>
47 #include <dt-bindings/clock/sun6i-a31-ccu.h>
48 #include <dt-bindings/reset/sun6i-a31-ccu.h>
50 /* Non-exported clocks */
148 CCU_GATE(CLK_AHB1_MIPIDSI, "ahb1-mipidsi", "ahb1", 0x60, 1)
[all …]
H A Dccu_a83t.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
41 #include <dev/clk/clk_div.h>
42 #include <dev/clk/clk_fixed.h>
43 #include <dev/clk/clk_mux.h>
45 #include <dev/clk/allwinner/aw_ccung.h>
47 #include <dt-bindings/clock/sun8i-a83t-ccu.h>
48 #include <dt-bindings/reset/sun8i-a83t-ccu.h>
50 /* Non-exported clocks */
76 /* Non-exported fixed clocks */
[all …]
H A Dccu_a64.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
41 #include <dev/clk/clk_div.h>
42 #include <dev/clk/clk_fixed.h>
43 #include <dev/clk/clk_mux.h>
45 #include <dev/clk/allwinner/aw_ccung.h>
47 #include <dt-bindings/clock/sun50i-a64-ccu.h>
48 #include <dt-bindings/reset/sun50i-a64-ccu.h>
50 /* Non-exported clocks */
141 CCU_GATE(CLK_BUS_MIPI_DSI, "bus-mipi-dsi", "ahb1", 0x60, 1)
[all …]
H A Dccu_a10.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
41 #include <dev/clk/clk_div.h>
42 #include <dev/clk/clk_fixed.h>
43 #include <dev/clk/clk_mux.h>
45 #include <dev/clk/allwinner/aw_ccung.h>
47 #include <dt-bindings/clock/sun4i-a10-ccu.h>
48 #include <dt-bindings/clock/sun7i-a20-ccu.h>
49 #include <dt-bindings/reset/sun4i-a10-ccu.h>
51 /* Non-exported resets */
[all …]
H A Dccu_h3.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
45 #include <dev/clk/clk_div.h>
46 #include <dev/clk/clk_fixed.h>
47 #include <dev/clk/clk_mux.h>
53 #include <dev/clk/allwinner/aw_ccung.h>
55 #include <dt-bindings/clock/sun8i-h3-ccu.h>
56 #include <dt-bindings/reset/sun8i-h3-ccu.h>
58 /* Non-exported resets */
61 /* Non-exported clocks */
[all …]
H A Dccu_h6.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
41 #include <dev/clk/clk_div.h>
42 #include <dev/clk/clk_fixed.h>
43 #include <dev/clk/clk_mux.h>
45 #include <dev/clk/allwinner/aw_ccung.h>
47 #include <dt-bindings/clock/sun50i-h6-ccu.h>
48 #include <dt-bindings/reset/sun50i-h6-ccu.h>
50 /* Non-exported clocks */
117 CCU_GATE(CLK_BUS_PSI, "bus-psi", "psi_ahb1_ahb2", 0x79c, 0)
[all …]
/freebsd/sys/contrib/device-tree/Bindings/arm/altera/
H A Dsocfpga-clk-manager.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/arm/altera/socfpga-clk-manager.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Dinh Nguyen <dinguyen@kernel.org>
20 - const: altr,clk-mgr
30 "#address-cells":
33 "#size-cells":
37 "^osc[0-9]$":
40 "^[a-z0-9,_]+(clk|pll|clk_gate|clk_divided)(@[a-f0-9]+)?$":
[all …]
/freebsd/sys/arm/mv/clk/
H A Dperiph_clk_mux_gate.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
38 #include <dev/clk/clk.h>
39 #include <dev/clk/clk_div.h>
40 #include <dev/clk/clk_fixed.h>
41 #include <dev/clk/clk_gate.h>
42 #include <dev/clk/clk_mux.h>
54 * Register chain: fixed (freq/2) -> mux (choose fixed or parent frequency) ->
55 * gate (enable or disable clock).
64 struct clk_gate_def *gate; in a37x0_periph_register_mux_gate() local
[all …]
H A Dperiph_clk_gate.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
38 #include <dev/clk/clk.h>
39 #include <dev/clk/clk_div.h>
40 #include <dev/clk/clk_fixed.h>
41 #include <dev/clk/clk_gate.h>
42 #include <dev/clk/clk_mux.h>
51 * Regsiter gate clock (disable or enable clock).
58 struct clk_gate_def *gate; in a37x0_periph_gate_register_gate() local
62 dev_id = device_def->common_def.device_id; in a37x0_periph_gate_register_gate()
[all …]
H A Dperiph_clk_d.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
38 #include <dev/clk/clk.h>
39 #include <dev/clk/clk_div.h>
40 #include <dev/clk/clk_fixed.h>
41 #include <dev/clk/clk_gate.h>
42 #include <dev/clk/clk_mux.h>
53 * Register chain: mux (select proper TBG) -> div1 (first frequency divider) ->
54 * div2 (second frequency divider) -> mux (select divided freq.
55 * or xtal output) -> gate (enable or disable clock), which is also final node
[all …]
H A Dperiph_clk_fixed.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
38 #include <dev/clk/clk.h>
39 #include <dev/clk/clk_div.h>
40 #include <dev/clk/clk_fixed.h>
41 #include <dev/clk/clk_gate.h>
42 #include <dev/clk/clk_mux.h>
54 * fixed clock (output from xtal/2) -> mux (choose fixed or xtal frequency)
63 struct clk_gate_def *gate; in a37x0_periph_fixed_register_fixed() local
67 dev_id = device_def->common_def.device_id; in a37x0_periph_fixed_register_fixed()
[all …]
/freebsd/sys/arm64/freescale/imx/
H A Dimx_ccm.h1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
31 #include <dev/clk/clk.h>
32 #include <dev/clk/clk_div.h>
33 #include <dev/clk/clk_fixed.h>
34 #include <dev/clk/clk_gate.h>
35 #include <dev/clk/clk_link.h>
69 struct imx_clk_gate_def *gate; member
74 } clk; member
81 .clk.link = &(struct clk_link_def) { \
[all …]
/freebsd/sys/contrib/device-tree/src/mips/mobileye/
H A Deyeq5-clocks.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
6 #include <dt-bindings/clock/mobileye,eyeq5-clk.h>
11 compatible = "fixed-clock";
12 #clock-cells = <0>;
13 clock-frequency = <30000000>;
17 occ_cpu: occ-cpu {
18 compatible = "fixed-factor-clock";
20 #clock-cells = <0>;
21 clock-div = <1>;
22 clock-mult = <1>;
[all …]
H A Deyeq5-fixed-clocks.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
8 pll_cpu: pll-cpu {
9 compatible = "fixed-clock";
10 #clock-cells = <0>;
11 clock-frequency = <1500000000>;
14 pll_vdi: pll-vdi {
15 compatible = "fixed-clock";
16 #clock-cells = <0>;
17 clock-frequency = <1280000000>;
20 pll_per: pll-per {
[all …]
/freebsd/sys/dev/clk/rockchip/
H A Drk3568_pmucru.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
42 #include <dev/clk/clk_div.h>
43 #include <dev/clk/clk_fixed.h>
44 #include <dev/clk/clk_mux.h>
46 #include <dev/clk/rockchip/rk_cru.h>
47 #include <contrib/device-tree/include/dt-bindings/clock/rk3568-cru.h>
58 .clk.pll = &(struct rk_clk_pll_def) { \
163 GATE(XIN_OSC0_DIV, "xin_osc0_div", "xin_osc0_div_div", 0, 0),
164 GATE(CLK_RTC_32K, "clk_rtc_32k", "clk_rtc_32k_mux", 0, 1),
[all …]

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