1 /*-
2 * Copyright (c) 2016 Michal Meloun <mmel@FreeBSD.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 */
26
27 #include <sys/param.h>
28 #include <sys/systm.h>
29 #include <sys/bus.h>
30 #include <sys/lock.h>
31 #include <sys/mutex.h>
32 #include <sys/rman.h>
33
34 #include <machine/bus.h>
35
36 #include <dev/clk/clk.h>
37
38 #include <dt-bindings/clock/tegra124-car.h>
39 #include "tegra124_car.h"
40
41 /* The TEGRA124_CLK_XUSB_GATE is missing in current
42 * DT bindings, define it localy
43 */
44 #ifdef TEGRA124_CLK_XUSB_GATE
45 #error "TEGRA124_CLK_XUSB_GATE is now defined, revisit XUSB code!"
46 #else
47 #define TEGRA124_CLK_XUSB_GATE 143
48 #endif
49
50 /* Bits in base register. */
51 #define PERLCK_AMUX_MASK 0x0F
52 #define PERLCK_AMUX_SHIFT 16
53 #define PERLCK_AMUX_DIS (1 << 20)
54 #define PERLCK_UDIV_DIS (1 << 24)
55 #define PERLCK_ENA_MASK (1 << 28)
56 #define PERLCK_MUX_SHIFT 29
57 #define PERLCK_MUX_MASK 0x07
58
59 struct periph_def {
60 struct clknode_init_def clkdef;
61 uint32_t base_reg;
62 uint32_t div_width;
63 uint32_t div_mask;
64 uint32_t div_f_width;
65 uint32_t div_f_mask;
66 uint32_t flags;
67 };
68
69 struct pgate_def {
70 struct clknode_init_def clkdef;
71 uint32_t idx;
72 uint32_t flags;
73 };
74 #define PLIST(x) static const char *x[]
75
76 #define GATE(_id, cname, plist, _idx) \
77 { \
78 .clkdef.id = TEGRA124_CLK_##_id, \
79 .clkdef.name = cname, \
80 .clkdef.parent_names = (const char *[]){plist}, \
81 .clkdef.parent_cnt = 1, \
82 .clkdef.flags = CLK_NODE_STATIC_STRINGS, \
83 .idx = _idx, \
84 .flags = 0, \
85 }
86
87 /* Sources for multiplexors. */
88 PLIST(mux_a_N_audio_N_p_N_clkm) =
89 {"pllA_out0", NULL, "audio", NULL,
90 "pllP_out0", NULL, "clk_m"};
91 PLIST(mux_a_N_audio0_N_p_N_clkm) =
92 {"pllA_out0", NULL, "audio0", NULL,
93 "pllP_out0", NULL, "clk_m"};
94 PLIST(mux_a_N_audio1_N_p_N_clkm) =
95 {"pllA_out0", NULL, "audio1", NULL,
96 "pllP_out0", NULL, "clk_m"};
97 PLIST(mux_a_N_audio2_N_p_N_clkm) =
98 {"pllA_out0", NULL, "audio2", NULL,
99 "pllP_out0", NULL, "clk_m"};
100 PLIST(mux_a_N_audio3_N_p_N_clkm) =
101 {"pllA_out0", NULL, "audio3", NULL,
102 "pllP_out0", NULL, "clk_m"};
103 PLIST(mux_a_N_audio4_N_p_N_clkm) =
104 {"pllA_out0", NULL, "audio4", NULL,
105 "pllP_out0", NULL, "clk_m"};
106 PLIST(mux_a_clks_p_clkm_e) =
107 {"pllA_out0", "clk_s", "pllP_out0",
108 "clk_m", "pllE_out0"};
109 PLIST(mux_a_c2_c_c3_p_N_clkm) =
110 {"pllA_out0", "pllC2_out0", "pllC_out0", "pllC3_out0",
111 "pllP_out0", NULL, "clk_m"};
112
113 PLIST(mux_m_c_p_a_c2_c3) =
114 {"pllM_out0", "pllC_out0", "pllP_out0", "pllA_out0",
115 "pllC2_out0", "pllC3_out0"};
116 PLIST(mux_m_c_p_a_c2_c3_clkm) =
117 {"pllM_out0", "pllC_out0", "pllP_out0", "pllA_out0",
118 "pllC2_out0", "pllC3_out0", "clk_m"};
119 PLIST(mux_m_c_p_a_c2_c3_clkm_c4) =
120 {"pllM_out0", "pllC_out0", "pllP_out0", "pllA_out0",
121 "pllC2_out0", "pllC3_out0", "clk_m", "pllC4_out0"};
122 PLIST(mux_m_c_p_clkm_mud_c2_c3) =
123 {"pllM_out0", "pllC_out0", "pllP_out0", "clk_m",
124 "pllM_UD", "pllC2_out0", "pllC3_out0"};
125 PLIST(mux_m_c_p_clkm_mud_c2_c3_cud) =
126 {"pllM_out0", "pllC_out0", "pllP_out0", "clk_m",
127 "pllM_UD", "pllC2_out0", "pllC3_out0", "pllC_UD"};
128
129 PLIST(mux_m_c2_c_c3_p_N_a) =
130 {"pllM_out0", "pllC2_out0", "pllC_out0", "pllC3_out0",
131 "pllP_out0", NULL, "pllA_out0"};
132 PLIST(mux_m_c2_c_c3_p_N_a_c4) =
133 {"pllM_out0", "pllC2_out0", "pllC_out0", "pllC3_out0",
134 NULL, "pllA_out0", "pllC4_out0"};
135
136 PLIST(mux_p_N_c_N_N_N_clkm) =
137 {"pllP_out0", NULL, "pllC_out0", NULL,
138 NULL, NULL, "clk_m"};
139 PLIST(mux_p_N_c_N_m_N_clkm) =
140 {"pllP_out0", NULL, "pllC_out0", NULL,
141 "pllM_out0", NULL, "clk_m"};
142 PLIST(mux_p_c_c2_clkm) =
143 {"pllP_out0", "pllC_out0", "pllC2_out0", "clk_m"};
144 PLIST(mux_p_c2_c_c3_m) =
145 {"pllP_out0", "pllC2_out0", "pllC_out0", "pllC3_out0",
146 "pllM_out0"};
147 PLIST(mux_p_c2_c_c3_m_N_clkm) =
148 {"pllP_out0", "pllC2_out0", "pllC_out0", "pllC3_out0",
149 "pllM_out0", NULL, "clk_m"};
150 PLIST(mux_p_c2_c_c3_m_e_clkm) =
151 {"pllP_out0", "pllC2_out0", "pllC_out0", "pllC3_out0",
152 "pllM_out0", "pllE_out0", "clk_m"};
153 PLIST(mux_p_c2_c_c3_m_a_clkm) =
154 {"pllP_out0", "pllC2_out0", "pllC_out0", "pllC3_out0",
155 "pllM_out0", "pllA_out0", "clk_m"};
156 PLIST(mux_p_c2_c_c3_m_clks_clkm) =
157 {"pllP_out0", "pllC2_out0", "pllC_out0", "pllC3_out0",
158 "pllM_out0", "clk_s", "clk_m"};
159 PLIST(mux_p_c2_c_c3_clks_N_clkm) =
160 {"pllP_out0", "pllC2_out0", "pllC_out0", "pllC3_out0",
161 "clk_s", NULL, "clk_m"};
162 PLIST(mux_p_c2_c_c3_clkm_N_clks) =
163 {"pllP_out0", "pllC2_out0", "pllC_out0", "pllC3_out0",
164 "clk_m", NULL, "clk_s"};
165 PLIST(mux_p_clkm_clks_E) =
166 {"pllP_out0", "clk_m", "clk_s", "pllE_out0"};
167 PLIST(mux_p_m_d_a_c_d2_clkm) =
168 {"pllP_out0", "pllM_out0", "pllD_out0", "pllA_out0",
169 "pllC_out0", "pllD2_out0", "clk_m"};
170
171 PLIST(mux_clkm_N_u48_N_p_N_u480) =
172 {"clk_m", NULL, "pllU_48", NULL,
173 "pllP_out0", NULL, "pllU_480"};
174 PLIST(mux_clkm_p_c2_c_c3_refre) =
175 {"clk_m", "pllP_out0", "pllC2_out0", "pllC_out0",
176 "pllC3_out0", "pllREFE_out"};
177 PLIST(mux_clkm_refe_clks_u480_c_c2_c3_oscdiv) =
178 {"clk_m", "pllREFE_out", "clk_s", "pllU_480",
179 "pllC_out0", "pllC2_out0", "pllC3_out0", "osc_div_clk"};
180
181 PLIST(mux_sep_audio) =
182 {"pllA_out0", "pllC2_out0", "pllC_out0", "pllC3_out0",
183 "pllP_out0", NULL, "clk_m", NULL,
184 "spdif_in", "i2s0", "i2s1", "i2s2",
185 "i2s4", "pllA_out0", "ext_vimclk"};
186
187 static uint32_t clk_enable_reg[] = {
188 CLK_OUT_ENB_L,
189 CLK_OUT_ENB_H,
190 CLK_OUT_ENB_U,
191 CLK_OUT_ENB_V,
192 CLK_OUT_ENB_W,
193 CLK_OUT_ENB_X,
194 };
195
196 static uint32_t clk_reset_reg[] = {
197 RST_DEVICES_L,
198 RST_DEVICES_H,
199 RST_DEVICES_U,
200 RST_DEVICES_V,
201 RST_DEVICES_W,
202 RST_DEVICES_X,
203 };
204
205 #define L(n) ((0 * 32) + (n))
206 #define H(n) ((1 * 32) + (n))
207 #define U(n) ((2 * 32) + (n))
208 #define V(n) ((3 * 32) + (n))
209 #define W(n) ((4 * 32) + (n))
210 #define X(n) ((5 * 32) + (n))
211
212 static struct pgate_def pgate_def[] = {
213 /* bank L -> 0-31 */
214 /* GATE(CPU, "cpu", "clk_m", L(0)), */
215 GATE(ISPB, "ispb", "clk_m", L(3)),
216 GATE(RTC, "rtc", "clk_s", L(4)),
217 GATE(TIMER, "timer", "clk_m", L(5)),
218 GATE(UARTA, "uarta", "pc_uarta" , L(6)),
219 GATE(UARTB, "uartb", "pc_uartb", L(7)),
220 GATE(VFIR, "vfir", "pc_vfir", L(7)),
221 /* GATE(GPIO, "gpio", "clk_m", L(8)), */
222 GATE(SDMMC2, "sdmmc2", "pc_sdmmc2", L(9)),
223 GATE(SPDIF_OUT, "spdif_out", "pc_spdif_out", L(10)),
224 GATE(SPDIF_IN, "spdif_in", "pc_spdif_in", L(10)),
225 GATE(I2S1, "i2s1", "pc_i2s1", L(11)),
226 GATE(I2C1, "i2c1", "pc_i2c1", L(12)),
227 GATE(SDMMC1, "sdmmc1", "pc_sdmmc1", L(14)),
228 GATE(SDMMC4, "sdmmc4", "pc_sdmmc4", L(15)),
229 GATE(PWM, "pwm", "pc_pwm", L(17)),
230 GATE(I2S2, "i2s2", "pc_i2s2", L(18)),
231 GATE(VI, "vi", "pc_vi", L(20)),
232 GATE(USBD, "usbd", "clk_m", L(22)),
233 GATE(ISP, "isp", "pc_isp", L(23)),
234 GATE(DISP2, "disp2", "pc_disp2", L(26)),
235 GATE(DISP1, "disp1", "pc_disp1", L(27)),
236 GATE(HOST1X, "host1x", "pc_host1x", L(28)),
237 GATE(VCP, "vcp", "clk_m", L(29)),
238 GATE(I2S0, "i2s0", "pc_i2s0", L(30)),
239 /* GATE(CACHE2, "ccache2", "clk_m", L(31)), */
240
241 /* bank H -> 32-63 */
242 GATE(MC, "mem", "clk_m", H(0)),
243 /* GATE(AHBDMA, "ahbdma", "clk_m", H(1)), */
244 GATE(APBDMA, "apbdma", "clk_m", H(2)),
245 GATE(KBC, "kbc", "clk_s", H(4)),
246 /* GATE(STAT_MON, "stat_mon", "clk_s", H(5)), */
247 /* GATE(PMC, "pmc", "clk_s", H(6)), */
248 GATE(FUSE, "fuse", "clk_m", H(7)),
249 GATE(KFUSE, "kfuse", "clk_m", H(8)),
250 GATE(SBC1, "spi1", "pc_spi1", H(9)),
251 GATE(NOR, "snor", "pc_snor", H(10)),
252 /* GATE(JTAG2TBC, "jtag2tbc", "clk_m", H(11)), */
253 GATE(SBC2, "spi2", "pc_spi2", H(12)),
254 GATE(SBC3, "spi3", "pc_spi3", H(14)),
255 GATE(I2C5, "i2c5", "pc_i2c5", H(15)),
256 GATE(DSIA, "dsia", "dsia_mux", H(16)),
257 GATE(MIPI, "hsi", "pc_hsi", H(18)),
258 GATE(HDMI, "hdmi", "pc_hdmi", H(19)),
259 GATE(CSI, "csi", "pllP_out3", H(20)),
260 GATE(I2C2, "i2c2", "pc_i2c2", H(22)),
261 GATE(UARTC, "uartc", "pc_uartc", H(23)),
262 GATE(MIPI_CAL, "mipi_cal", "clk_m", H(24)),
263 GATE(EMC, "emc", "pc_emc_2x", H(25)),
264 GATE(USB2, "usb2", "clk_m", H(26)),
265 GATE(USB3, "usb3", "clk_m", H(27)),
266 GATE(VDE, "vde", "pc_vde", H(29)),
267 GATE(BSEA, "bsea", "clk_m", H(30)),
268 GATE(BSEV, "bsev", "clk_m", H(31)),
269
270 /* bank U -> 64-95 */
271 GATE(UARTD, "uartd", "pc_uartd", U(1)),
272 GATE(I2C3, "i2c3", "pc_i2c3", U(3)),
273 GATE(SBC4, "spi4", "pc_spi4", U(4)),
274 GATE(SDMMC3, "sdmmc3", "pc_sdmmc3", U(5)),
275 GATE(PCIE, "pcie", "clk_m", U(6)),
276 GATE(OWR, "owr", "pc_owr", U(7)),
277 GATE(AFI, "afi", "clk_m", U(8)),
278 GATE(CSITE, "csite", "pc_csite", U(9)),
279 /* GATE(AVPUCQ, "avpucq", clk_m, U(11)), */
280 GATE(TRACE, "traceclkin", "pc_traceclkin", U(13)),
281 GATE(SOC_THERM, "soc_therm", "pc_soc_therm", U(14)),
282 GATE(DTV, "dtv", "clk_m", U(15)),
283 GATE(I2CSLOW, "i2c_slow", "pc_i2c_slow", U(17)),
284 GATE(DSIB, "dsib", "dsib_mux", U(18)),
285 GATE(TSEC, "tsec", "pc_tsec", U(19)),
286 /* GATE(IRAMA, "irama", "clk_m", U(20)), */
287 /* GATE(IRAMB, "iramb", "clk_m", U(21)), */
288 /* GATE(IRAMC, "iramc", "clk_m", U(22)), */
289 /* GATE(IRAMD, "iramd", "clk_m", U(23)), */
290 /* GATE(CRAM2, "cram2", "clk_m", U(24)), */
291 GATE(XUSB_HOST, "xusb_core_host", "pc_xusb_core_host", U(25)),
292 /* GATE(M_DOUBLER, "m_doubler", "clk_m", U(26)), */
293 GATE(MSENC, "msenc", "pc_msenc", U(27)),
294 GATE(CSUS, "sus_out", "clk_m", U(28)),
295 /* GATE(DEVD2_OUT, "devd2_out", "clk_m", U(29)), */
296 /* GATE(DEVD1_OUT, "devd1_out", "clk_m", U(30)), */
297 GATE(XUSB_DEV, "xusb_core_dev", "pc_xusb_core_dev", U(31)),
298
299 /* bank V -> 96-127 */
300 /* GATE(CPUG, "cpug", "clk_m", V(0)), */
301 /* GATE(CPULP, "cpuLP", "clk_m", V(1)), */
302 GATE(MSELECT, "mselect", "pc_mselect", V(3)),
303 GATE(TSENSOR, "tsensor", "pc_tsensor", V(4)),
304 GATE(I2S3, "i2s3", "pc_i2s3", V(5)),
305 GATE(I2S4, "i2s4", "pc_i2s4", V(6)),
306 GATE(I2C4, "i2c4", "pc_i2c4", V(7)),
307 GATE(SBC5, "spi5", "pc_spi5", V(8)),
308 GATE(SBC6, "spi6", "pc_spi6", V(9)),
309 GATE(D_AUDIO, "audio", "pc_audio", V(10)),
310 GATE(APBIF, "apbif", "clk_m", V(11)),
311 GATE(DAM0, "dam0", "pc_dam0", V(12)),
312 GATE(DAM1, "dam1", "pc_dam1", V(13)),
313 GATE(DAM2, "dam2", "pc_dam2", V(14)),
314 GATE(HDA2CODEC_2X, "hda2codec_2x", "pc_hda2codec_2x", V(15)),
315 /* GATE(ATOMICS, "atomics", "clk_m", V(16)), */
316 /* GATE(SPDIF_DOUBLER, "spdif_doubler", "clk_m", V(22)), */
317 GATE(ACTMON, "actmon", "pc_actmon", V(23)),
318 GATE(EXTERN1, "extperiph1", "pc_extperiph1", V(24)),
319 GATE(EXTERN2, "extperiph2", "pc_extperiph2", V(25)),
320 GATE(EXTERN3, "extperiph3", "pc_extperiph3", V(26)),
321 GATE(SATA_OOB, "sata_oob", "pc_sata_oob", V(27)),
322 GATE(SATA, "sata", "pc_sata", V(28)),
323 GATE(HDA, "hda", "pc_hda", V(29)),
324
325 /* bank W -> 128-159*/
326 GATE(HDA2HDMI, "hda2hdmi", "clk_m", W(0)),
327 GATE(SATA_COLD, "sata_cold", "clk_m", W(1)), /* Reset only */
328 /* GATE(PCIERX0, "pcierx0", "clk_m", W(2)), */
329 /* GATE(PCIERX1, "pcierx1", "clk_m", W(3)), */
330 /* GATE(PCIERX2, "pcierx2", "clk_m", W(4)), */
331 /* GATE(PCIERX3, "pcierx3", "clk_m", W(5)), */
332 /* GATE(PCIERX4, "pcierx4", "clk_m", W(6)), */
333 /* GATE(PCIERX5, "pcierx5", "clk_m", W(7)), */
334 /* GATE(CEC, "cec", "clk_m", W(8)), */
335 /* GATE(PCIE2_IOBIST, "pcie2_iobist", "clk_m", W(9)), */
336 /* GATE(EMC_IOBIST, "emc_iobist", "clk_m", W(10)), */
337 /* GATE(HDMI_IOBIST, "hdmi_iobist", "clk_m", W(11)), */
338 /* GATE(SATA_IOBIST, "sata_iobist", "clk_m", W(12)), */
339 /* GATE(MIPI_IOBIST, "mipi_iobist", "clk_m", W(13)), */
340 GATE(XUSB_GATE, "xusb_gate", "clk_m", W(15)),
341 GATE(CILAB, "cilab", "pc_cilab", W(16)),
342 GATE(CILCD, "cilcd", "pc_cilcd", W(17)),
343 GATE(CILE, "cile", "pc_cile", W(18)),
344 GATE(DSIALP, "dsia_lp", "pc_dsia_lp", W(19)),
345 GATE(DSIBLP, "dsib_lp", "pc_dsib_lp", W(20)),
346 GATE(ENTROPY, "entropy", "pc_entropy", W(21)),
347 GATE(AMX, "amx", "pc_amx", W(25)),
348 GATE(ADX, "adx", "pc_adx", W(26)),
349 GATE(DFLL_REF, "dvfs_ref", "pc_dvfs_ref", W(27)),
350 GATE(DFLL_SOC, "dvfs_soc", "pc_dvfs_soc", W(27)),
351 GATE(XUSB_SS, "xusb_ss", "xusb_ss_mux", W(28)),
352 /* GATE(EMC_LATENCY, "emc_latency", "pc_emc_latency", W(29)), */
353
354 /* bank X -> 160-191*/
355 /* GATE(SPARE, "spare", "clk_m", X(0)), */
356 /* GATE(CAM_MCLK, "CAM_MCLK", "clk_m", X(4)), */
357 /* GATE(CAM_MCLK2, "CAM_MCLK2", "clk_m", X(5)), */
358 GATE(I2C6, "i2c6", "pc_i2c6", X(6)),
359 GATE(VIM2_CLK, "vim2_clk", "clk_m", X(11)),
360 /* GATE(EMC_DLL, "emc_dll", "pc_emc_dll", X(14)), */
361 GATE(HDMI_AUDIO, "hdmi_audio", "pc_hdmi_audio", X(16)),
362 GATE(CLK72MHZ, "clk72mhz", "pc_clk72mhz", X(17)),
363 GATE(VIC03, "vic", "pc_vic", X(18)),
364 GATE(ADX1, "adx1", "pc_adx1", X(20)),
365 GATE(DPAUX, "dpaux", "clk_m", X(21)),
366 GATE(SOR0_LVDS, "sor0", "pc_sor0", X(22)),
367 GATE(GPU, "gpu", "osc_div_clk", X(24)),
368 GATE(AMX1, "amx1", "pc_amx1", X(26)),
369 };
370
371 /* Peripheral clock clock */
372 #define DCF_HAVE_MUX 0x0100 /* Block with multipexor */
373 #define DCF_HAVE_ENA 0x0200 /* Block with enable bit */
374 #define DCF_HAVE_DIV 0x0400 /* Block with divider */
375
376 /* Mark block with additional bits / functionality. */
377 #define DCF_IS_MASK 0x00FF
378 #define DCF_IS_UART 0x0001
379 #define DCF_IS_VI 0x0002
380 #define DCF_IS_HOST1X 0x0003
381 #define DCF_IS_XUSB_SS 0x0004
382 #define DCF_IS_EMC_DLL 0x0005
383 #define DCF_IS_SATA 0x0006
384 #define DCF_IS_VIC 0x0007
385 #define DCF_IS_AUDIO 0x0008
386 #define DCF_IS_SOR0 0x0009
387 #define DCF_IS_EMC 0x000A
388
389 /* Basic pheripheral clock */
390 #define PER_CLK(_id, cn, pl, r, diw, fiw, f) \
391 { \
392 .clkdef.id = _id, \
393 .clkdef.name = cn, \
394 .clkdef.parent_names = pl, \
395 .clkdef.parent_cnt = nitems(pl), \
396 .clkdef.flags = CLK_NODE_STATIC_STRINGS, \
397 .base_reg = r, \
398 .div_width = diw, \
399 .div_f_width = fiw, \
400 .flags = f, \
401 }
402
403 /* Mux with fractional 8.1 divider. */
404 #define CLK_8_1(id, cn, pl, r, f) \
405 PER_CLK(id, cn, pl, r, 8, 1, (f) | DCF_HAVE_MUX | DCF_HAVE_DIV)
406
407 /* Mux with fractional 16.1 divider. */
408 #define CLK16_1(id, cn, pl, r, f) \
409 PER_CLK(id, cn, pl, r, 16, 1, (f) | DCF_HAVE_MUX | DCF_HAVE_DIV)
410 /* Mux with integer 16bits divider. */
411 #define CLK16_0(id, cn, pl, r, f) \
412 PER_CLK(id, cn, pl, r, 16, 0, (f) | DCF_HAVE_MUX | DCF_HAVE_DIV)
413 /* Mux wihout divider. */
414 #define CLK_0_0(id, cn, pl, r, f) \
415 PER_CLK(id, cn, pl, r, 0, 0, (f) | DCF_HAVE_MUX)
416
417 static struct periph_def periph_def[] = {
418 CLK_8_1(0, "pc_i2s1", mux_a_N_audio1_N_p_N_clkm, CLK_SOURCE_I2S1, DCF_HAVE_ENA),
419 CLK_8_1(0, "pc_i2s2", mux_a_N_audio2_N_p_N_clkm, CLK_SOURCE_I2S2, DCF_HAVE_ENA),
420 CLK_8_1(0, "pc_spdif_out", mux_a_N_audio_N_p_N_clkm, CLK_SOURCE_SPDIF_OUT, 0),
421 CLK_8_1(0, "pc_spdif_in", mux_p_c2_c_c3_m, CLK_SOURCE_SPDIF_IN, 0),
422 CLK_8_1(0, "pc_pwm", mux_p_c2_c_c3_clks_N_clkm, CLK_SOURCE_PWM, 0),
423 CLK_8_1(0, "pc_spi2", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_SPI2, 0),
424 CLK_8_1(0, "pc_spi3", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_SPI3, 0),
425 CLK16_0(0, "pc_i2c5", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_I2C5, 0),
426 CLK16_0(0, "pc_i2c1", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_I2C1, 0),
427 CLK_8_1(0, "pc_spi1", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_SPI1, 0),
428 CLK_0_0(0, "pc_disp1", mux_p_m_d_a_c_d2_clkm, CLK_SOURCE_DISP1, 0),
429 CLK_0_0(0, "pc_disp2", mux_p_m_d_a_c_d2_clkm, CLK_SOURCE_DISP2, 0),
430 CLK_8_1(0, "pc_isp", mux_m_c_p_a_c2_c3_clkm_c4, CLK_SOURCE_ISP, 0),
431 CLK_8_1(0, "pc_vi", mux_m_c2_c_c3_p_N_a_c4, CLK_SOURCE_VI, DCF_IS_VI),
432 CLK_8_1(0, "pc_sdmmc1", mux_p_c2_c_c3_m_e_clkm, CLK_SOURCE_SDMMC1, 0),
433 CLK_8_1(0, "pc_sdmmc2", mux_p_c2_c_c3_m_e_clkm, CLK_SOURCE_SDMMC2, 0),
434 CLK_8_1(0, "pc_sdmmc4", mux_p_c2_c_c3_m_e_clkm, CLK_SOURCE_SDMMC4, 0),
435 CLK_8_1(0, "pc_vfir", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_VFIR, 0),
436 CLK_8_1(0, "pc_hsi", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_HSI, 0),
437 CLK16_1(0, "pc_uarta", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_UARTA, DCF_IS_UART),
438 CLK16_1(0, "pc_uartb", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_UARTB, DCF_IS_UART),
439 CLK_8_1(0, "pc_host1x", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_HOST1X, DCF_IS_HOST1X),
440 CLK_8_1(0, "pc_hdmi", mux_p_m_d_a_c_d2_clkm, CLK_SOURCE_HDMI, 0),
441 CLK16_0(0, "pc_i2c2", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_I2C2, 0),
442 CLK_8_1(0, "pc_emc_2x", mux_m_c_p_clkm_mud_c2_c3_cud, CLK_SOURCE_EMC, DCF_IS_EMC),
443 CLK16_1(0, "pc_uartc", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_UARTC, DCF_IS_UART),
444 CLK_8_1(0, "pc_vi_sensor", mux_m_c2_c_c3_p_N_a, CLK_SOURCE_VI_SENSOR, 0),
445 CLK_8_1(0, "pc_spi4", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_SPI4, 0),
446 CLK16_0(0, "pc_i2c3", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_I2C3, 0),
447 CLK_8_1(0, "pc_sdmmc3", mux_p_c2_c_c3_m_e_clkm, CLK_SOURCE_SDMMC3, 0),
448 CLK16_1(0, "pc_uartd", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_UARTD, DCF_IS_UART),
449 CLK_8_1(0, "pc_vde", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_VDE, 0),
450 CLK_8_1(0, "pc_owr", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_OWR, 0),
451 CLK_8_1(0, "pc_snor", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_NOR, 0),
452 CLK_8_1(0, "pc_csite", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_CSITE, 0),
453 CLK_8_1(0, "pc_i2s0", mux_a_N_audio0_N_p_N_clkm, CLK_SOURCE_I2S0, 0),
454 /* DTV xxx */
455 CLK_8_1(0, "pc_msenc", mux_m_c2_c_c3_p_N_a, CLK_SOURCE_MSENC, 0),
456 CLK_8_1(0, "pc_tsec", mux_p_c2_c_c3_m_a_clkm, CLK_SOURCE_TSEC, 0),
457 /* SPARE2 */
458
459 CLK_8_1(0, "pc_mselect", mux_p_c2_c_c3_m_clks_clkm, CLK_SOURCE_MSELECT, 0),
460 CLK_8_1(0, "pc_tsensor", mux_p_c2_c_c3_clkm_N_clks, CLK_SOURCE_TSENSOR, 0),
461 CLK_8_1(0, "pc_i2s3", mux_a_N_audio3_N_p_N_clkm, CLK_SOURCE_I2S3, DCF_HAVE_ENA),
462 CLK_8_1(0, "pc_i2s4", mux_a_N_audio4_N_p_N_clkm, CLK_SOURCE_I2S4, DCF_HAVE_ENA),
463 CLK16_0(0, "pc_i2c4", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_I2C4, 0),
464 CLK_8_1(0, "pc_spi5", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_SPI5, 0),
465 CLK_8_1(0, "pc_spi6", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_SPI6, 0),
466 CLK_8_1(0, "pc_audio", mux_sep_audio, CLK_SOURCE_AUDIO, DCF_IS_AUDIO),
467 CLK_8_1(0, "pc_dam0", mux_sep_audio, CLK_SOURCE_DAM0, DCF_IS_AUDIO),
468 CLK_8_1(0, "pc_dam1", mux_sep_audio, CLK_SOURCE_DAM1, DCF_IS_AUDIO),
469 CLK_8_1(0, "pc_dam2", mux_sep_audio, CLK_SOURCE_DAM2, DCF_IS_AUDIO),
470 CLK_8_1(0, "pc_hda2codec_2x", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_HDA2CODEC_2X, 0),
471 CLK_8_1(0, "pc_actmon", mux_p_c2_c_c3_clks_N_clkm, CLK_SOURCE_ACTMON, 0),
472 CLK_8_1(0, "pc_extperiph1", mux_a_clks_p_clkm_e, CLK_SOURCE_EXTPERIPH1, 0),
473 CLK_8_1(0, "pc_extperiph2", mux_a_clks_p_clkm_e, CLK_SOURCE_EXTPERIPH2, 0),
474 CLK_8_1(0, "pc_extperiph3", mux_a_clks_p_clkm_e, CLK_SOURCE_EXTPERIPH3, 0),
475 CLK_8_1(0, "pc_i2c_slow", mux_p_c2_c_c3_clks_N_clkm, CLK_SOURCE_I2C_SLOW, 0),
476 /* SYS */
477 CLK_8_1(0, "pc_sor0", mux_p_m_d_a_c_d2_clkm, CLK_SOURCE_SOR0, DCF_IS_SOR0),
478 CLK_8_1(0, "pc_sata_oob", mux_p_N_c_N_m_N_clkm, CLK_SOURCE_SATA_OOB, 0),
479 CLK_8_1(0, "pc_sata", mux_p_N_c_N_m_N_clkm, CLK_SOURCE_SATA, DCF_IS_SATA),
480 CLK_8_1(0, "pc_hda", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_HDA, 0),
481 CLK_8_1(TEGRA124_CLK_XUSB_HOST_SRC,
482 "pc_xusb_core_host", mux_clkm_p_c2_c_c3_refre, CLK_SOURCE_XUSB_CORE_HOST, 0),
483 CLK_8_1(TEGRA124_CLK_XUSB_FALCON_SRC,
484 "pc_xusb_falcon", mux_clkm_p_c2_c_c3_refre, CLK_SOURCE_XUSB_FALCON, 0),
485 CLK_8_1(TEGRA124_CLK_XUSB_FS_SRC,
486 "pc_xusb_fs", mux_clkm_N_u48_N_p_N_u480, CLK_SOURCE_XUSB_FS, 0),
487 CLK_8_1(TEGRA124_CLK_XUSB_DEV_SRC,
488 "pc_xusb_core_dev", mux_clkm_p_c2_c_c3_refre, CLK_SOURCE_XUSB_CORE_DEV, 0),
489 CLK_8_1(TEGRA124_CLK_XUSB_SS_SRC,
490 "pc_xusb_ss", mux_clkm_refe_clks_u480_c_c2_c3_oscdiv, CLK_SOURCE_XUSB_SS, DCF_IS_XUSB_SS),
491 CLK_8_1(0, "pc_cilab", mux_p_N_c_N_N_N_clkm, CLK_SOURCE_CILAB, 0),
492 CLK_8_1(0, "pc_cilcd", mux_p_N_c_N_N_N_clkm, CLK_SOURCE_CILCD, 0),
493 CLK_8_1(0, "pc_cile", mux_p_N_c_N_N_N_clkm, CLK_SOURCE_CILE, 0),
494 CLK_8_1(0, "pc_dsia_lp", mux_p_N_c_N_N_N_clkm, CLK_SOURCE_DSIA_LP, 0),
495 CLK_8_1(0, "pc_dsib_lp", mux_p_N_c_N_N_N_clkm, CLK_SOURCE_DSIB_LP, 0),
496 CLK_8_1(0, "pc_entropy", mux_p_clkm_clks_E, CLK_SOURCE_ENTROPY, 0),
497 CLK_8_1(0, "pc_dvfs_ref", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_DVFS_REF, DCF_HAVE_ENA),
498 CLK_8_1(0, "pc_dvfs_soc", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_DVFS_SOC, DCF_HAVE_ENA),
499 CLK_8_1(0, "pc_traceclkin", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_TRACECLKIN, 0),
500 CLK_8_1(0, "pc_adx", mux_a_c2_c_c3_p_N_clkm, CLK_SOURCE_ADX, DCF_HAVE_ENA),
501 CLK_8_1(0, "pc_amx", mux_a_c2_c_c3_p_N_clkm, CLK_SOURCE_AMX, DCF_HAVE_ENA),
502 CLK_8_1(0, "pc_emc_latency", mux_m_c_p_clkm_mud_c2_c3, CLK_SOURCE_EMC_LATENCY, 0),
503 CLK_8_1(0, "pc_soc_therm", mux_m_c_p_a_c2_c3, CLK_SOURCE_SOC_THERM, 0),
504 CLK_8_1(0, "pc_vi_sensor2", mux_m_c2_c_c3_p_N_a, CLK_SOURCE_VI_SENSOR2, 0),
505 CLK16_0(0, "pc_i2c6", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_I2C6, 0),
506 CLK_8_1(0, "pc_emc_dll", mux_m_c_p_clkm_mud_c2_c3, CLK_SOURCE_EMC_DLL, DCF_IS_EMC_DLL),
507 CLK_8_1(0, "pc_hdmi_audio", mux_p_c_c2_clkm, CLK_SOURCE_HDMI_AUDIO, 0),
508 CLK_8_1(0, "pc_clk72mhz", mux_p_c_c2_clkm, CLK_SOURCE_CLK72MHZ, 0),
509 CLK_8_1(0, "pc_adx1", mux_a_c2_c_c3_p_N_clkm, CLK_SOURCE_ADX1, DCF_HAVE_ENA),
510 CLK_8_1(0, "pc_amx1", mux_a_c2_c_c3_p_N_clkm, CLK_SOURCE_AMX1, DCF_HAVE_ENA),
511 CLK_8_1(0, "pc_vic", mux_m_c_p_a_c2_c3_clkm, CLK_SOURCE_VIC, DCF_IS_VIC),
512 };
513
514 static int periph_init(struct clknode *clk, device_t dev);
515 static int periph_recalc(struct clknode *clk, uint64_t *freq);
516 static int periph_set_freq(struct clknode *clk, uint64_t fin,
517 uint64_t *fout, int flags, int *stop);
518 static int periph_set_mux(struct clknode *clk, int idx);
519
520 struct periph_sc {
521 device_t clkdev;
522 uint32_t base_reg;
523 uint32_t div_shift;
524 uint32_t div_width;
525 uint32_t div_mask;
526 uint32_t div_f_width;
527 uint32_t div_f_mask;
528 uint32_t flags;
529
530 uint32_t divider;
531 int mux;
532 };
533
534 static clknode_method_t periph_methods[] = {
535 /* Device interface */
536 CLKNODEMETHOD(clknode_init, periph_init),
537 CLKNODEMETHOD(clknode_recalc_freq, periph_recalc),
538 CLKNODEMETHOD(clknode_set_freq, periph_set_freq),
539 CLKNODEMETHOD(clknode_set_mux, periph_set_mux),
540 CLKNODEMETHOD_END
541 };
542 DEFINE_CLASS_1(tegra124_periph, tegra124_periph_class, periph_methods,
543 sizeof(struct periph_sc), clknode_class);
544
545 static int
periph_init(struct clknode * clk,device_t dev)546 periph_init(struct clknode *clk, device_t dev)
547 {
548 struct periph_sc *sc;
549 uint32_t reg;
550 sc = clknode_get_softc(clk);
551
552 DEVICE_LOCK(sc);
553 if (sc->flags & DCF_HAVE_ENA)
554 MD4(sc, sc->base_reg, PERLCK_ENA_MASK, PERLCK_ENA_MASK);
555
556 RD4(sc, sc->base_reg, ®);
557 DEVICE_UNLOCK(sc);
558
559 /* Stnadard mux. */
560 if (sc->flags & DCF_HAVE_MUX)
561 sc->mux = (reg >> PERLCK_MUX_SHIFT) & PERLCK_MUX_MASK;
562 else
563 sc->mux = 0;
564 if (sc->flags & DCF_HAVE_DIV)
565 sc->divider = (reg & sc->div_mask) + 2;
566 else
567 sc->divider = 1;
568 if ((sc->flags & DCF_IS_MASK) == DCF_IS_UART) {
569 if (!(reg & PERLCK_UDIV_DIS))
570 sc->divider = 2;
571 }
572
573 /* AUDIO MUX */
574 if ((sc->flags & DCF_IS_MASK) == DCF_IS_AUDIO) {
575 if (!(reg & PERLCK_AMUX_DIS) && (sc->mux == 7)) {
576 sc->mux = 8 +
577 ((reg >> PERLCK_AMUX_SHIFT) & PERLCK_MUX_MASK);
578 }
579 }
580 clknode_init_parent_idx(clk, sc->mux);
581 return(0);
582 }
583
584 static int
periph_set_mux(struct clknode * clk,int idx)585 periph_set_mux(struct clknode *clk, int idx)
586 {
587 struct periph_sc *sc;
588 uint32_t reg;
589
590 sc = clknode_get_softc(clk);
591 if (!(sc->flags & DCF_HAVE_MUX))
592 return (ENXIO);
593
594 sc->mux = idx;
595 DEVICE_LOCK(sc);
596 RD4(sc, sc->base_reg, ®);
597 reg &= ~(PERLCK_MUX_MASK << PERLCK_MUX_SHIFT);
598 if ((sc->flags & DCF_IS_MASK) == DCF_IS_AUDIO) {
599 reg &= ~PERLCK_AMUX_DIS;
600 reg &= ~(PERLCK_MUX_MASK << PERLCK_AMUX_SHIFT);
601
602 if (idx <= 7) {
603 reg |= idx << PERLCK_MUX_SHIFT;
604 } else {
605 reg |= 7 << PERLCK_MUX_SHIFT;
606 reg |= (idx - 8) << PERLCK_AMUX_SHIFT;
607 }
608 } else {
609 reg |= idx << PERLCK_MUX_SHIFT;
610 }
611 WR4(sc, sc->base_reg, reg);
612 DEVICE_UNLOCK(sc);
613
614 return(0);
615 }
616
617 static int
periph_recalc(struct clknode * clk,uint64_t * freq)618 periph_recalc(struct clknode *clk, uint64_t *freq)
619 {
620 struct periph_sc *sc;
621 uint32_t reg;
622
623 sc = clknode_get_softc(clk);
624
625 if (sc->flags & DCF_HAVE_DIV) {
626 DEVICE_LOCK(sc);
627 RD4(sc, sc->base_reg, ®);
628 DEVICE_UNLOCK(sc);
629 *freq = (*freq << sc->div_f_width) / sc->divider;
630 }
631 return (0);
632 }
633
634 static int
periph_set_freq(struct clknode * clk,uint64_t fin,uint64_t * fout,int flags,int * stop)635 periph_set_freq(struct clknode *clk, uint64_t fin, uint64_t *fout,
636 int flags, int *stop)
637 {
638 struct periph_sc *sc;
639 uint64_t tmp, divider;
640
641 sc = clknode_get_softc(clk);
642 if (!(sc->flags & DCF_HAVE_DIV)) {
643 *stop = 0;
644 return (0);
645 }
646
647 tmp = fin << sc->div_f_width;
648 divider = tmp / *fout;
649 if ((tmp % *fout) != 0)
650 divider++;
651
652 if (divider < (1 << sc->div_f_width))
653 divider = 1 << (sc->div_f_width - 1);
654
655 if (flags & CLK_SET_DRYRUN) {
656 if (((flags & (CLK_SET_ROUND_UP | CLK_SET_ROUND_DOWN)) == 0) &&
657 (*fout != (tmp / divider)))
658 return (ERANGE);
659 } else {
660 DEVICE_LOCK(sc);
661 MD4(sc, sc->base_reg, sc->div_mask,
662 (divider - (1 << sc->div_f_width)));
663 DEVICE_UNLOCK(sc);
664 sc->divider = divider;
665 }
666 *fout = tmp / divider;
667 *stop = 1;
668 return (0);
669 }
670
671 static int
periph_register(struct clkdom * clkdom,struct periph_def * clkdef)672 periph_register(struct clkdom *clkdom, struct periph_def *clkdef)
673 {
674 struct clknode *clk;
675 struct periph_sc *sc;
676
677 clk = clknode_create(clkdom, &tegra124_periph_class, &clkdef->clkdef);
678 if (clk == NULL)
679 return (1);
680
681 sc = clknode_get_softc(clk);
682 sc->clkdev = clknode_get_device(clk);
683 sc->base_reg = clkdef->base_reg;
684 sc->div_width = clkdef->div_width;
685 sc->div_mask = (1 <<clkdef->div_width) - 1;
686 sc->div_f_width = clkdef->div_f_width;
687 sc->div_f_mask = (1 <<clkdef->div_f_width) - 1;
688 sc->flags = clkdef->flags;
689
690 clknode_register(clkdom, clk);
691 return (0);
692 }
693
694 /* -------------------------------------------------------------------------- */
695 static int pgate_init(struct clknode *clk, device_t dev);
696 static int pgate_set_gate(struct clknode *clk, bool enable);
697 static int pgate_get_gate(struct clknode *clk, bool *enableD);
698
699 struct pgate_sc {
700 device_t clkdev;
701 uint32_t idx;
702 uint32_t flags;
703 uint32_t enabled;
704
705 };
706
707 static clknode_method_t pgate_methods[] = {
708 /* Device interface */
709 CLKNODEMETHOD(clknode_init, pgate_init),
710 CLKNODEMETHOD(clknode_set_gate, pgate_set_gate),
711 CLKNODEMETHOD(clknode_get_gate, pgate_get_gate),
712 CLKNODEMETHOD_END
713 };
714 DEFINE_CLASS_1(tegra124_pgate, tegra124_pgate_class, pgate_methods,
715 sizeof(struct pgate_sc), clknode_class);
716
717 static uint32_t
get_enable_reg(int idx)718 get_enable_reg(int idx)
719 {
720 KASSERT(idx / 32 < nitems(clk_enable_reg),
721 ("Invalid clock index for enable: %d", idx));
722 return (clk_enable_reg[idx / 32]);
723 }
724
725 static uint32_t
get_reset_reg(int idx)726 get_reset_reg(int idx)
727 {
728 KASSERT(idx / 32 < nitems(clk_reset_reg),
729 ("Invalid clock index for reset: %d", idx));
730 return (clk_reset_reg[idx / 32]);
731 }
732
733 static int
pgate_init(struct clknode * clk,device_t dev)734 pgate_init(struct clknode *clk, device_t dev)
735 {
736 struct pgate_sc *sc;
737 uint32_t ena_reg, rst_reg, mask;
738
739 sc = clknode_get_softc(clk);
740 mask = 1 << (sc->idx % 32);
741
742 DEVICE_LOCK(sc);
743 RD4(sc, get_enable_reg(sc->idx), &ena_reg);
744 RD4(sc, get_reset_reg(sc->idx), &rst_reg);
745 DEVICE_UNLOCK(sc);
746
747 sc->enabled = ena_reg & mask ? 1 : 0;
748 clknode_init_parent_idx(clk, 0);
749
750 return(0);
751 }
752
753 static int
pgate_set_gate(struct clknode * clk,bool enable)754 pgate_set_gate(struct clknode *clk, bool enable)
755 {
756 struct pgate_sc *sc;
757 uint32_t reg, mask, base_reg;
758
759 sc = clknode_get_softc(clk);
760 mask = 1 << (sc->idx % 32);
761 sc->enabled = enable;
762 base_reg = get_enable_reg(sc->idx);
763
764 DEVICE_LOCK(sc);
765 MD4(sc, base_reg, mask, enable ? mask : 0);
766 RD4(sc, base_reg, ®);
767 DEVICE_UNLOCK(sc);
768
769 DELAY(2);
770 return(0);
771 }
772
773 static int
pgate_get_gate(struct clknode * clk,bool * enabled)774 pgate_get_gate(struct clknode *clk, bool *enabled)
775 {
776 struct pgate_sc *sc;
777 uint32_t reg, mask, base_reg;
778
779 sc = clknode_get_softc(clk);
780 mask = 1 << (sc->idx % 32);
781 base_reg = get_enable_reg(sc->idx);
782
783 DEVICE_LOCK(sc);
784 RD4(sc, base_reg, ®);
785 DEVICE_UNLOCK(sc);
786 *enabled = reg & mask ? true: false;
787
788 return(0);
789 }
790 int
tegra124_hwreset_by_idx(struct tegra124_car_softc * sc,intptr_t idx,bool reset)791 tegra124_hwreset_by_idx(struct tegra124_car_softc *sc, intptr_t idx, bool reset)
792 {
793 uint32_t reg, mask, reset_reg;
794
795 mask = 1 << (idx % 32);
796 reset_reg = get_reset_reg(idx);
797
798 CLKDEV_DEVICE_LOCK(sc->dev);
799 CLKDEV_MODIFY_4(sc->dev, reset_reg, mask, reset ? mask : 0);
800 CLKDEV_READ_4(sc->dev, reset_reg, ®);
801 CLKDEV_DEVICE_UNLOCK(sc->dev);
802
803 return(0);
804 }
805
806 static int
pgate_register(struct clkdom * clkdom,struct pgate_def * clkdef)807 pgate_register(struct clkdom *clkdom, struct pgate_def *clkdef)
808 {
809 struct clknode *clk;
810 struct pgate_sc *sc;
811
812 clk = clknode_create(clkdom, &tegra124_pgate_class, &clkdef->clkdef);
813 if (clk == NULL)
814 return (1);
815
816 sc = clknode_get_softc(clk);
817 sc->clkdev = clknode_get_device(clk);
818 sc->idx = clkdef->idx;
819 sc->flags = clkdef->flags;
820
821 clknode_register(clkdom, clk);
822 return (0);
823 }
824
825 void
tegra124_periph_clock(struct tegra124_car_softc * sc)826 tegra124_periph_clock(struct tegra124_car_softc *sc)
827 {
828 int i, rv;
829
830 for (i = 0; i < nitems(periph_def); i++) {
831 rv = periph_register(sc->clkdom, &periph_def[i]);
832 if (rv != 0)
833 panic("tegra124_periph_register failed");
834 }
835 for (i = 0; i < nitems(pgate_def); i++) {
836 rv = pgate_register(sc->clkdom, &pgate_def[i]);
837 if (rv != 0)
838 panic("tegra124_pgate_register failed");
839 }
840
841 }
842