Lines Matching +full:clk +full:- +full:gate
1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
37 #include <dev/clk/clk.h>
39 #include <dt-bindings/clock/tegra210-car.h>
40 #include <dt-bindings/reset/tegra210-car.h>
71 #define GATE(_id, cname, plist, _idx) \ macro
308 /* bank L -> 0-31 */
309 GATE(ISPB, "ispb", "clk_m", L(3)),
310 GATE(RTC, "rtc", "clk_s", L(4)),
311 GATE(TIMER, "timer", "clk_m", L(5)),
312 GATE(UARTA, "uarta", "pc_uarta" , L(6)),
313 GATE(UARTB, "uartb", "pc_uartb", L(7)),
314 GATE(GPIO, "gpio", "clk_m", L(8)),
315 GATE(SDMMC2, "sdmmc2", "pc_sdmmc2", L(9)),
316 GATE(SPDIF_OUT, "spdif_out", "pc_spdif_out", L(10)),
317 GATE(SPDIF_IN, "spdif_in", "pc_spdif_in", L(10)),
318 GATE(I2S1, "i2s2", "pc_i2s2", L(11)),
319 GATE(I2C1, "i2c1", "pc_i2c1", L(12)),
320 GATE(SDMMC1, "sdmmc1", "pc_sdmmc1", L(14)),
321 GATE(SDMMC4, "sdmmc4", "pc_sdmmc4", L(15)),
322 GATE(PWM, "pwm", "pc_pwm", L(17)),
323 GATE(I2S2, "i2s3", "pc_i2s3", L(18)),
324 GATE(VI, "vi", "pc_vi", L(20)),
325 GATE(USBD, "usbd", "clk_m", L(22)),
326 GATE(ISP, "isp", "pc_isp", L(23)),
327 GATE(DISP2, "disp2", "pc_disp2", L(26)),
328 GATE(DISP1, "disp1", "pc_disp1", L(27)),
329 GATE(HOST1X, "host1x", "pc_host1x", L(28)),
330 GATE(I2S0, "i2s1", "pc_i2s1", L(30)),
332 /* bank H -> 32-63 */
333 GATE(MC, "mem", "clk_m", H(0)),
334 GATE(AHBDMA, "ahbdma", "clk_m", H(1)),
335 GATE(APBDMA, "apbdma", "clk_m", H(2)),
336 GATE(STAT_MON, "stat_mon", "clk_s", H(5)),
337 GATE(PMC, "pmc", "clk_s", H(6)),
338 GATE(FUSE, "fuse", "clk_m", H(7)),
339 GATE(KFUSE, "kfuse", "clk_m", H(8)),
340 GATE(SBC1, "spi1", "pc_spi1", H(9)),
341 GATE(SBC2, "spi2", "pc_spi2", H(12)),
342 GATE(SBC3, "spi3", "pc_spi3", H(14)),
343 GATE(I2C5, "i2c5", "pc_i2c5", H(15)),
344 GATE(DSIA, "dsia", "pllD_dsi_csi", H(16)),
345 GATE(CSI, "csi", "pllP_out3", H(20)),
346 GATE(I2C2, "i2c2", "pc_i2c2", H(22)),
347 GATE(UARTC, "uartc", "pc_uartc", H(23)),
348 GATE(MIPI_CAL, "mipi_cal", "clk_m", H(24)),
349 GATE(EMC, "emc", "pc_emc", H(25)),
350 GATE(USB2, "usb2", "clk_m", H(26)),
351 GATE(BSEV, "bsev", "clk_m", H(31)),
353 /* bank U -> 64-95 */
354 GATE(UARTD, "uartd", "pc_uartd", U(1)),
355 GATE(I2C3, "i2c3", "pc_i2c3", U(3)),
356 GATE(SBC4, "spi4", "pc_spi4", U(4)),
357 GATE(SDMMC3, "sdmmc3", "pc_sdmmc3", U(5)),
358 GATE(PCIE, "pcie", "clk_m", U(6)),
359 GATE(AFI, "afi", "clk_m", U(8)),
360 GATE(CSITE, "csite", "pc_csite", U(9)),
361 GATE(SOC_THERM, "soc_therm", "pc_soc_therm", U(14)),
362 GATE(DTV, "dtv", "clk_m", U(15)),
363 GATE(I2CSLOW, "i2c_slow", "pc_i2c_slow", U(17)),
364 GATE(DSIB, "dsib", "pllD_dsi_csi", U(18)),
365 GATE(TSEC, "tsec", "pc_tsec", U(19)),
366 GATE(IRAMA, "irama", "clk_m", U(20)),
367 GATE(IRAMB, "iramb", "clk_m", U(21)),
368 GATE(IRAMC, "iramc", "clk_m", U(22)),
369 GATE(IRAMD, "iramd", "clk_m", U(23)),
370 GATE(CRAM2, "cram2", "clk_m", U(24)),
371 GATE(XUSB_HOST, "xusb_host", "pc_xusb_core_host", U(25)),
372 GATE(M_DOUBLER, "m_doubler", "clk_m", U(26)),
373 GATE(CSUS, "sus_out", "clk_m", U(28)),
374 GATE(DEVD2_OUT, "devd2_out", "clk_m", U(29)),
375 GATE(DEVD1_OUT, "devd1_out", "clk_m", U(30)),
376 GATE(XUSB_DEV, "xusb_core_dev", "pc_xusb_core_dev", U(31)),
378 /* bank V -> 96-127 */
379 GATE(CPUG, "cpug", "clk_m", V(0)),
380 GATE(MSELECT, "mselect", "pc_mselect", V(3)),
381 GATE(TSENSOR, "tsensor", "pc_tsensor", V(4)),
382 GATE(I2S4, "i2s5", "pc_i2s5", V(5)),
383 GATE(I2S3, "i2s4", "pc_i2s4", V(6)),
384 GATE(I2C4, "i2c4", "pc_i2c4", V(7)),
385 GATE(D_AUDIO, "ahub", "pc_ahub", V(10)),
386 GATE(APB2APE, "apb2ape", "clk_m", V(11)),
387 GATE(HDA2CODEC_2X, "hda2codec_2x", "pc_hda2codec_2x", V(15)),
388 GATE(ATOMICS, "atomics", "clk_m", V(16)),
389 GATE(SPDIF_2X, "spdif_doubler", "clk_m", V(22)),
390 GATE(ACTMON, "actmon", "pc_actmon", V(23)),
391 GATE(EXTERN1, "extperiph1", "pc_extperiph1", V(24)),
392 GATE(EXTERN2, "extperiph2", "pc_extperiph2", V(25)),
393 GATE(EXTERN3, "extperiph3", "pc_extperiph3", V(26)),
394 GATE(SATA_OOB, "sata_oob", "pc_sata_oob", V(27)),
395 GATE(SATA, "sata", "pc_sata", V(28)),
396 GATE(HDA, "hda", "pc_hda", V(29)),
398 /* bank W -> 128-159*/
399 GATE(HDA2HDMI, "hda2hdmi", "clk_m", W(0)),
400 /* GATE(SATA_COLD, "sata_cold", "clk_m", W(1)),*/ /* Reset only */
401 GATE(PCIERX0, "pcierx0", "clk_m", W(2)),
402 GATE(PCIERX1, "pcierx1", "clk_m", W(3)),
403 GATE(PCIERX2, "pcierx2", "clk_m", W(4)),
404 GATE(PCIERX3, "pcierx3", "clk_m", W(5)),
405 GATE(PCIERX4, "pcierx4", "clk_m", W(6)),
406 GATE(PCIERX5, "pcierx5", "clk_m", W(7)),
407 GATE(CEC, "cec", "clk_m", W(8)),
408 GATE(PCIE2_IOBIST, "pcie2_iobist", "clk_m", W(9)),
409 GATE(EMC_IOBIST, "emc_iobist", "clk_m", W(10)),
410 GATE(SATA_IOBIST, "sata_iobist", "clk_m", W(12)),
411 GATE(MIPI_IOBIST, "mipi_iobist", "clk_m", W(13)),
412 GATE(XUSB_GATE, "xusb_gate", "clk_m", W(15)),
413 GATE(CILAB, "cilab", "pc_cilab", W(16)),
414 GATE(CILCD, "cilcd", "pc_cilcd", W(17)),
415 GATE(CILE, "cilef", "pc_cilef", W(18)),
416 GATE(DSIALP, "dsia_lp", "pc_dsia_lp", W(19)),
417 GATE(DSIBLP, "dsib_lp", "pc_dsib_lp", W(20)),
418 GATE(ENTROPY, "entropy", "pc_entropy", W(21)),
419 GATE(DFLL_REF, "dvfs_ref", "pc_dvfs_ref", W(27)),
420 GATE(DFLL_SOC, "dvfs_soc", "pc_dvfs_soc", W(27)),
421 GATE(XUSB_SS, "xusb_ss", "pc_xusb_ss", W(28)),
422 GATE(EMC_LATENCY, "emc_latency", "pc_emc_latency", W(29)),
423 GATE(MC1, "mc1", "clk_m", W(30)),
425 /* bank X -> 160-191*/
426 /*GATE(SPARE, "spare", "clk_m", X(0)), */
427 GATE(DMIC1, "dmic1", "clk_m", X(1)),
428 GATE(DMIC2, "dmic2", "clk_m", X(2)),
429 GATE(ETR, "etr", "clk_m", X(3)),
430 GATE(CAM_MCLK, "CAM_MCLK", "clk_m", X(4)),
431 GATE(CAM_MCLK2, "CAM_MCLK2", "clk_m", X(5)),
432 GATE(I2C6, "i2c6", "pc_i2c6", X(6)),
433 GATE(MC_CAPA, "mc_capa", "clk_m", X(7)),
434 GATE(MC_CBPA, "mc_cbpa", "clk_m", X(8)),
435 GATE(MC_CPU, "mc_cpu", "clk_m", X(9)),
436 GATE(MC_BBC, "mc_bbc", "clk_m", X(10)),
437 GATE(VIM2_CLK, "vim2_clk", "clk_m", X(11)),
438 GATE(MIPIBIF, "mipibif", "clk_m", X(13)),
439 GATE(EMC_DLL, "emc_dll", "pc_emc_dll", X(14)),
440 GATE(UART_FST_MIPI_CAL, "uart_fst_mipi_cal", "clk_m", X(17)),
441 GATE(VIC03, "vic", "pc_vic", X(18)),
442 GATE(DPAUX, "dpaux", "dpaux_div", X(21)),
443 GATE(SOR0, "sor0", "pc_sor0", X(22)),
444 GATE(SOR1, "sor1", "pc_sor1", X(23)),
445 GATE(GPU, "gpu", "osc_div_clk", X(24)),
446 GATE(DBGAPB, "dbgapb", "clk_m", X(25)),
447 GATE(HPLL_ADSP, "hpll_adsp", "clk_m", X(26)),
448 GATE(PLLP_ADSP, "pllp_adsp", "clk_m", X(27)),
449 GATE(PLLA_ADSP, "plla_adsp", "clk_m", X(28)),
450 GATE(PLLG_REF, "pllg_ref", "clk_m", X(29)),
452 /* bank Y -> 192-224*/
453 /* GATE(SPARE1, "spare1", "clk_m", Y(0)), */
454 GATE(SDMMC_LEGACY, "sdmmc_legacy_tm", "pc_sdmmc_legacy_tm", Y(1)),
455 GATE(NVDEC, "nvdec", "pc_nvdec", Y(2)),
456 GATE(NVJPG, "nvjpg", "clk_m", Y(3)),
457 GATE(AXIAP, "axiap", "clk_m", Y(4)),
458 GATE(DMIC3, "dmic3", "clk_m", Y(5)),
459 GATE(APE, "ape", "clk_m", Y(6)),
460 GATE(ADSP, "adsp", "clk_m", Y(7)),
461 GATE(MC_CDPA, "mc_cdpa", "clk_m", Y(8)),
462 GATE(MC_CCPA, "mc_ccpa", "clk_m", Y(9)),
463 GATE(MAUD, "mc_maud", "clk_m", Y(10)),
464 GATE(TSECB, "tsecb", "clk_m", Y(14)),
465 GATE(DPAUX1, "dpaux1", "dpaux1_div", Y(15)),
466 GATE(VI_I2C, "vi_i2c", "clk_m", Y(16)),
467 GATE(HSIC_TRK, "hsic_trk", "clk_m", Y(17)),
468 GATE(USB2_TRK, "usb2_trk", "clk_m", Y(18)),
469 GATE(QSPI, "qspi", "clk_m", Y(19)),
470 GATE(UARTAPE, "uarape", "clk_m", Y(20)),
471 GATE(ADSP_NEON, "adspneon", "clk_m", Y(26)),
472 GATE(NVENC, "nvenc", "clk_m", Y(27)),
473 GATE(IQC2, "iqc2", "clk_m", Y(28)),
474 GATE(IQC1, "iqc1", "clk_m", Y(29)),
475 GATE(SOR_SAFE, "sor_safe", "sor_safe_div", Y(30)),
476 GATE(PLL_P_OUT_CPU, "pllp_out_cpu", "clk_m", Y(31)),
627 static int periph_init(struct clknode *clk, device_t dev);
628 static int periph_recalc(struct clknode *clk, uint64_t *freq);
629 static int periph_set_freq(struct clknode *clk, uint64_t fin,
631 static int periph_set_mux(struct clknode *clk, int idx);
659 periph_init(struct clknode *clk, device_t dev) in periph_init() argument
663 sc = clknode_get_softc(clk); in periph_init()
666 if (sc->flags & DCF_HAVE_ENA) in periph_init()
667 MD4(sc, sc->base_reg, PERLCK_ENA_MASK, PERLCK_ENA_MASK); in periph_init()
669 RD4(sc, sc->base_reg, ®); in periph_init()
673 if (sc->flags & DCF_HAVE_MUX) in periph_init()
674 sc->mux = (reg >> PERLCK_MUX_SHIFT) & PERLCK_MUX_MASK; in periph_init()
676 sc->mux = 0; in periph_init()
677 if (sc->flags & DCF_HAVE_DIV) in periph_init()
678 sc->divider = (reg & sc->div_mask) + 2; in periph_init()
680 sc->divider = 1; in periph_init()
681 if ((sc->flags & DCF_IS_MASK) == DCF_IS_UART) { in periph_init()
683 sc->divider = 2; in periph_init()
687 if ((sc->flags & DCF_IS_MASK) == DCF_IS_AHUB) { in periph_init()
688 if (!(reg & PERLCK_AMUX_DIS) && (sc->mux == 7)) { in periph_init()
689 sc->mux = 8 + in periph_init()
693 clknode_init_parent_idx(clk, sc->mux); in periph_init()
698 periph_set_mux(struct clknode *clk, int idx) in periph_set_mux() argument
704 sc = clknode_get_softc(clk); in periph_set_mux()
705 if (!(sc->flags & DCF_HAVE_MUX)) in periph_set_mux()
708 sc->mux = idx; in periph_set_mux()
710 RD4(sc, sc->base_reg, ®); in periph_set_mux()
712 if ((sc->flags & DCF_IS_MASK) == DCF_IS_AHUB) { in periph_set_mux()
720 reg |= (idx - 8) << PERLCK_AMUX_SHIFT; in periph_set_mux()
725 WR4(sc, sc->base_reg, reg); in periph_set_mux()
732 periph_recalc(struct clknode *clk, uint64_t *freq) in periph_recalc() argument
737 sc = clknode_get_softc(clk); in periph_recalc()
739 if (sc->flags & DCF_HAVE_DIV) { in periph_recalc()
741 RD4(sc, sc->base_reg, ®); in periph_recalc()
743 *freq = (*freq << sc->div_f_width) / sc->divider; in periph_recalc()
749 periph_set_freq(struct clknode *clk, uint64_t fin, uint64_t *fout, in periph_set_freq() argument
755 sc = clknode_get_softc(clk); in periph_set_freq()
756 if (!(sc->flags & DCF_HAVE_DIV)) { in periph_set_freq()
761 tmp = fin << sc->div_f_width; in periph_set_freq()
766 if (divider < (1 << sc->div_f_width)) in periph_set_freq()
767 divider = 1 << (sc->div_f_width - 1); in periph_set_freq()
775 MD4(sc, sc->base_reg, sc->div_mask, in periph_set_freq()
776 (divider - (1 << sc->div_f_width))); in periph_set_freq()
778 sc->divider = divider; in periph_set_freq()
788 struct clknode *clk; in periph_register() local
791 clk = clknode_create(clkdom, &tegra210_periph_class, &clkdef->clkdef); in periph_register()
792 if (clk == NULL) in periph_register()
795 sc = clknode_get_softc(clk); in periph_register()
796 sc->clkdev = clknode_get_device(clk); in periph_register()
797 sc->base_reg = clkdef->base_reg; in periph_register()
798 sc->div_width = clkdef->div_width; in periph_register()
799 sc->div_mask = (1 <<clkdef->div_width) - 1; in periph_register()
800 sc->div_f_width = clkdef->div_f_width; in periph_register()
801 sc->div_f_mask = (1 <<clkdef->div_f_width) - 1; in periph_register()
802 sc->flags = clkdef->flags; in periph_register()
804 clknode_register(clkdom, clk); in periph_register()
808 /* -------------------------------------------------------------------------- */
809 static int pgate_init(struct clknode *clk, device_t dev);
810 static int pgate_set_gate(struct clknode *clk, bool enable);
811 static int pgate_get_gate(struct clknode *clk, bool *enabled);
848 pgate_init(struct clknode *clk, device_t dev) in pgate_init() argument
853 sc = clknode_get_softc(clk); in pgate_init()
854 mask = 1 << (sc->idx % 32); in pgate_init()
857 RD4(sc, get_enable_reg(sc->idx), &ena_reg); in pgate_init()
858 RD4(sc, get_reset_reg(sc->idx), &rst_reg); in pgate_init()
861 sc->enabled = ena_reg & mask ? 1 : 0; in pgate_init()
862 clknode_init_parent_idx(clk, 0); in pgate_init()
868 pgate_set_gate(struct clknode *clk, bool enable) in pgate_set_gate() argument
873 sc = clknode_get_softc(clk); in pgate_set_gate()
874 mask = 1 << (sc->idx % 32); in pgate_set_gate()
875 sc->enabled = enable; in pgate_set_gate()
876 base_reg = get_enable_reg(sc->idx); in pgate_set_gate()
888 pgate_get_gate(struct clknode *clk, bool *enabled) in pgate_get_gate() argument
893 sc = clknode_get_softc(clk); in pgate_get_gate()
894 mask = 1 << (sc->idx % 32); in pgate_get_gate()
895 base_reg = get_enable_reg(sc->idx); in pgate_get_gate()
910 CLKDEV_DEVICE_LOCK(sc->dev); in tegra210_hwreset_by_idx()
912 CLKDEV_MODIFY_4(sc->dev, DFLL_BASE, DFLL_BASE_DVFS_DFLL_RESET, in tegra210_hwreset_by_idx()
914 CLKDEV_READ_4(sc->dev, DFLL_BASE, ®); in tegra210_hwreset_by_idx()
919 CLKDEV_WRITE_4(sc->dev, reset_reg, mask); in tegra210_hwreset_by_idx()
920 CLKDEV_READ_4(sc->dev, reset_reg, ®); in tegra210_hwreset_by_idx()
925 CLKDEV_MODIFY_4(sc->dev, reset_reg, mask, reset ? mask : 0); in tegra210_hwreset_by_idx()
926 CLKDEV_READ_4(sc->dev, reset_reg, ®); in tegra210_hwreset_by_idx()
928 CLKDEV_DEVICE_UNLOCK(sc->dev); in tegra210_hwreset_by_idx()
936 struct clknode *clk; in pgate_register() local
939 clk = clknode_create(clkdom, &tegra210_pgate_class, &clkdef->clkdef); in pgate_register()
940 if (clk == NULL) in pgate_register()
943 sc = clknode_get_softc(clk); in pgate_register()
944 sc->clkdev = clknode_get_device(clk); in pgate_register()
945 sc->idx = clkdef->idx; in pgate_register()
946 sc->flags = clkdef->flags; in pgate_register()
948 clknode_register(clkdom, clk); in pgate_register()
958 rv = periph_register(sc->clkdom, &periph_def[i]); in tegra210_periph_clock()
963 rv = pgate_register(sc->clkdom, &pgate_def[i]); in tegra210_periph_clock()