1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2/* 3 * Copyright 2023 Mobileye Vision Technologies Ltd. 4 */ 5 6/ { 7 /* Fixed clock */ 8 pll_cpu: pll-cpu { 9 compatible = "fixed-clock"; 10 #clock-cells = <0>; 11 clock-frequency = <1500000000>; 12 }; 13 14 pll_vdi: pll-vdi { 15 compatible = "fixed-clock"; 16 #clock-cells = <0>; 17 clock-frequency = <1280000000>; 18 }; 19 20 pll_per: pll-per { 21 compatible = "fixed-clock"; 22 #clock-cells = <0>; 23 clock-frequency = <2000000000>; 24 }; 25 26 pll_ddr0: pll-ddr0 { 27 compatible = "fixed-clock"; 28 #clock-cells = <0>; 29 clock-frequency = <1857210000>; 30 }; 31 32 pll_ddr1: pll-ddr1 { 33 compatible = "fixed-clock"; 34 #clock-cells = <0>; 35 clock-frequency = <1857210000>; 36 }; 37 38/* PLL_CPU derivatives */ 39 occ_cpu: occ-cpu { 40 compatible = "fixed-factor-clock"; 41 clocks = <&pll_cpu>; 42 #clock-cells = <0>; 43 clock-div = <1>; 44 clock-mult = <1>; 45 }; 46 si_css0_ref_clk: si-css0-ref-clk { /* gate ClkRstGen_si_css0_ref */ 47 compatible = "fixed-factor-clock"; 48 clocks = <&occ_cpu>; 49 #clock-cells = <0>; 50 clock-div = <1>; 51 clock-mult = <1>; 52 }; 53 cpc_clk: cpc-clk { 54 compatible = "fixed-factor-clock"; 55 clocks = <&si_css0_ref_clk>; 56 #clock-cells = <0>; 57 clock-div = <1>; 58 clock-mult = <1>; 59 }; 60 core0_clk: core0-clk { 61 compatible = "fixed-factor-clock"; 62 clocks = <&si_css0_ref_clk>; 63 #clock-cells = <0>; 64 clock-div = <1>; 65 clock-mult = <1>; 66 }; 67 core1_clk: core1-clk { 68 compatible = "fixed-factor-clock"; 69 clocks = <&si_css0_ref_clk>; 70 #clock-cells = <0>; 71 clock-div = <1>; 72 clock-mult = <1>; 73 }; 74 core2_clk: core2-clk { 75 compatible = "fixed-factor-clock"; 76 clocks = <&si_css0_ref_clk>; 77 #clock-cells = <0>; 78 clock-div = <1>; 79 clock-mult = <1>; 80 }; 81 core3_clk: core3-clk { 82 compatible = "fixed-factor-clock"; 83 clocks = <&si_css0_ref_clk>; 84 #clock-cells = <0>; 85 clock-div = <1>; 86 clock-mult = <1>; 87 }; 88 cm_clk: cm-clk { 89 compatible = "fixed-factor-clock"; 90 clocks = <&si_css0_ref_clk>; 91 #clock-cells = <0>; 92 clock-div = <1>; 93 clock-mult = <1>; 94 }; 95 mem_clk: mem-clk { 96 compatible = "fixed-factor-clock"; 97 clocks = <&si_css0_ref_clk>; 98 #clock-cells = <0>; 99 clock-div = <1>; 100 clock-mult = <1>; 101 }; 102 occ_isram: occ-isram { 103 compatible = "fixed-factor-clock"; 104 clocks = <&pll_cpu>; 105 #clock-cells = <0>; 106 clock-div = <2>; 107 clock-mult = <1>; 108 }; 109 isram_clk: isram-clk { /* gate ClkRstGen_isram */ 110 compatible = "fixed-factor-clock"; 111 clocks = <&occ_isram>; 112 #clock-cells = <0>; 113 clock-div = <1>; 114 clock-mult = <1>; 115 }; 116 occ_dbu: occ-dbu { 117 compatible = "fixed-factor-clock"; 118 clocks = <&pll_cpu>; 119 #clock-cells = <0>; 120 clock-div = <10>; 121 clock-mult = <1>; 122 }; 123 si_dbu_tp_pclk: si-dbu-tp-pclk { /* gate ClkRstGen_dbu */ 124 compatible = "fixed-factor-clock"; 125 clocks = <&occ_dbu>; 126 #clock-cells = <0>; 127 clock-div = <1>; 128 clock-mult = <1>; 129 }; 130/* PLL_VDI derivatives */ 131 occ_vdi: occ-vdi { 132 compatible = "fixed-factor-clock"; 133 clocks = <&pll_vdi>; 134 #clock-cells = <0>; 135 clock-div = <2>; 136 clock-mult = <1>; 137 }; 138 vdi_clk: vdi-clk { /* gate ClkRstGen_vdi */ 139 compatible = "fixed-factor-clock"; 140 clocks = <&occ_vdi>; 141 #clock-cells = <0>; 142 clock-div = <1>; 143 clock-mult = <1>; 144 }; 145 occ_can_ser: occ-can-ser { 146 compatible = "fixed-factor-clock"; 147 clocks = <&pll_vdi>; 148 #clock-cells = <0>; 149 clock-div = <16>; 150 clock-mult = <1>; 151 }; 152 can_ser_clk: can-ser-clk { /* gate ClkRstGen_can_ser */ 153 compatible = "fixed-factor-clock"; 154 clocks = <&occ_can_ser>; 155 #clock-cells = <0>; 156 clock-div = <1>; 157 clock-mult = <1>; 158 }; 159 i2c_ser_clk: i2c-ser-clk { 160 compatible = "fixed-factor-clock"; 161 clocks = <&pll_vdi>; 162 #clock-cells = <0>; 163 clock-div = <20>; 164 clock-mult = <1>; 165 }; 166/* PLL_PER derivatives */ 167 occ_periph: occ-periph { 168 compatible = "fixed-factor-clock"; 169 clocks = <&pll_per>; 170 #clock-cells = <0>; 171 clock-div = <16>; 172 clock-mult = <1>; 173 }; 174 periph_clk: periph-clk { 175 compatible = "fixed-factor-clock"; 176 clocks = <&occ_periph>; 177 #clock-cells = <0>; 178 clock-div = <1>; 179 clock-mult = <1>; 180 }; 181 can_clk: can-clk { 182 compatible = "fixed-factor-clock"; 183 clocks = <&occ_periph>; 184 #clock-cells = <0>; 185 clock-div = <1>; 186 clock-mult = <1>; 187 }; 188 spi_clk: spi-clk { 189 compatible = "fixed-factor-clock"; 190 clocks = <&occ_periph>; 191 #clock-cells = <0>; 192 clock-div = <1>; 193 clock-mult = <1>; 194 }; 195 uart_clk: uart-clk { 196 compatible = "fixed-factor-clock"; 197 clocks = <&occ_periph>; 198 #clock-cells = <0>; 199 clock-div = <1>; 200 clock-mult = <1>; 201 }; 202 i2c_clk: i2c-clk { 203 compatible = "fixed-factor-clock"; 204 clocks = <&occ_periph>; 205 #clock-cells = <0>; 206 clock-div = <1>; 207 clock-mult = <1>; 208 clock-output-names = "i2c_clk"; 209 }; 210 timer_clk: timer-clk { 211 compatible = "fixed-factor-clock"; 212 clocks = <&occ_periph>; 213 #clock-cells = <0>; 214 clock-div = <1>; 215 clock-mult = <1>; 216 clock-output-names = "timer_clk"; 217 }; 218 gpio_clk: gpio-clk { 219 compatible = "fixed-factor-clock"; 220 clocks = <&occ_periph>; 221 #clock-cells = <0>; 222 clock-div = <1>; 223 clock-mult = <1>; 224 clock-output-names = "gpio_clk"; 225 }; 226 emmc_sys_clk: emmc-sys-clk { 227 compatible = "fixed-factor-clock"; 228 clocks = <&pll_per>; 229 #clock-cells = <0>; 230 clock-div = <10>; 231 clock-mult = <1>; 232 clock-output-names = "emmc_sys_clk"; 233 }; 234 ccf_ctrl_clk: ccf-ctrl-clk { 235 compatible = "fixed-factor-clock"; 236 clocks = <&pll_per>; 237 #clock-cells = <0>; 238 clock-div = <4>; 239 clock-mult = <1>; 240 clock-output-names = "ccf_ctrl_clk"; 241 }; 242 occ_mjpeg_core: occ-mjpeg-core { 243 compatible = "fixed-factor-clock"; 244 clocks = <&pll_per>; 245 #clock-cells = <0>; 246 clock-div = <2>; 247 clock-mult = <1>; 248 clock-output-names = "occ_mjpeg_core"; 249 }; 250 hsm_clk: hsm-clk { /* gate ClkRstGen_hsm */ 251 compatible = "fixed-factor-clock"; 252 clocks = <&occ_mjpeg_core>; 253 #clock-cells = <0>; 254 clock-div = <1>; 255 clock-mult = <1>; 256 clock-output-names = "hsm_clk"; 257 }; 258 mjpeg_core_clk: mjpeg-core-clk { /* gate ClkRstGen_mjpeg_gen */ 259 compatible = "fixed-factor-clock"; 260 clocks = <&occ_mjpeg_core>; 261 #clock-cells = <0>; 262 clock-div = <1>; 263 clock-mult = <1>; 264 clock-output-names = "mjpeg_core_clk"; 265 }; 266 fcmu_a_clk: fcmu-a-clk { 267 compatible = "fixed-factor-clock"; 268 clocks = <&pll_per>; 269 #clock-cells = <0>; 270 clock-div = <20>; 271 clock-mult = <1>; 272 clock-output-names = "fcmu_a_clk"; 273 }; 274 occ_pci_sys: occ-pci-sys { 275 compatible = "fixed-factor-clock"; 276 clocks = <&pll_per>; 277 #clock-cells = <0>; 278 clock-div = <8>; 279 clock-mult = <1>; 280 clock-output-names = "occ_pci_sys"; 281 }; 282 pclk: pclk { 283 compatible = "fixed-clock"; 284 #clock-cells = <0>; 285 clock-frequency = <250000000>; /* 250MHz */ 286 }; 287 tsu_clk: tsu-clk { 288 compatible = "fixed-clock"; 289 #clock-cells = <0>; 290 clock-frequency = <125000000>; /* 125MHz */ 291 }; 292}; 293