Lines Matching +full:clk +full:- +full:gate
1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
31 #include <dev/clk/clk.h>
32 #include <dev/clk/clk_div.h>
33 #include <dev/clk/clk_fixed.h>
34 #include <dev/clk/clk_gate.h>
35 #include <dev/clk/clk_link.h>
69 struct imx_clk_gate_def *gate; member
74 } clk; member
81 .clk.link = &(struct clk_link_def) { \
94 .clk.mux = &(struct imx_clk_mux_def) { \
111 .clk.fixed = &(struct clk_fixed_def) { \
123 .clk.fixed = &(struct clk_fixed_def) { \
134 /* Clock gate */
135 #define GATE(_id, _name, _pname, _o, _shift) \ macro
138 .clk.gate = &(struct imx_clk_gate_def) { \
150 /* Root clock gate */
154 .clk.gate = &(struct imx_clk_gate_def) { \
166 /* Composite clock with GATE, MUX, PRE_DIV, and POST_DIV */
170 .clk.composite = &(struct imx_clk_composite_def) { \
185 .clk.composite = &(struct imx_clk_composite_def) { \
199 .clk.frac_pll = &(struct imx_clk_frac_pll_def) { \
212 .clk.div = &(struct clk_div_def) { \