1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2021 Semihalf.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 */
27
28 #include <sys/param.h>
29 #include <sys/bus.h>
30 #include <sys/kernel.h>
31 #include <sys/module.h>
32 #include <sys/mutex.h>
33 #include <sys/rman.h>
34 #include <machine/bus.h>
35
36 #include <dev/fdt/simplebus.h>
37
38 #include <dev/clk/clk.h>
39 #include <dev/clk/clk_div.h>
40 #include <dev/clk/clk_fixed.h>
41 #include <dev/clk/clk_gate.h>
42 #include <dev/clk/clk_mux.h>
43
44 #include <dev/ofw/ofw_bus.h>
45 #include <dev/ofw/ofw_bus_subr.h>
46
47 #include "clkdev_if.h"
48 #include "periph.h"
49
50 #define PARENT_CNT 2
51
52 /*
53 * Register clock with fixed frequency divider clock. Chain consists of:
54 * fixed clock (output from xtal/2) -> mux (choose fixed or xtal frequency)
55 */
56
57 int
a37x0_periph_fixed_register_fixed(struct clkdom * clkdom,struct a37x0_periph_clknode_def * device_def)58 a37x0_periph_fixed_register_fixed(struct clkdom *clkdom,
59 struct a37x0_periph_clknode_def *device_def)
60 {
61 const char *parent_names[PARENT_CNT];
62 struct clk_fixed_def fixed_def;
63 struct clk_gate_def *gate;
64 struct clk_mux_def *mux;
65 int error, dev_id;
66
67 dev_id = device_def->common_def.device_id;
68 mux = &device_def->clk_def.fixed.mux;
69 gate = &device_def->clk_def.fixed.gate;
70 fixed_def = device_def->clk_def.fixed.fixed;
71
72 fixed_def.clkdef.parent_names = &device_def->common_def.xtal;
73 fixed_def.clkdef.parent_cnt = 1;
74 fixed_def.clkdef.id = A37x0_INTERNAL_CLK_ID(dev_id, FIXED1_POS);
75 fixed_def.clkdef.flags = 0;
76 fixed_def.mult = 1;
77 fixed_def.div = 2;
78 fixed_def.freq = 0;
79
80 parent_names[0] = device_def->common_def.xtal;
81 parent_names[1] = fixed_def.clkdef.name;
82
83 error = clknode_fixed_register(clkdom, &fixed_def);
84 if (error)
85 goto fail;
86
87 a37x0_periph_set_props(&mux->clkdef, parent_names ,PARENT_CNT);
88 error = a37x0_periph_create_mux(clkdom, mux,
89 A37x0_INTERNAL_CLK_ID(dev_id, MUX_POS));
90 if (error)
91 goto fail;
92
93 a37x0_periph_set_props(&gate->clkdef, &mux->clkdef.name, 1);
94 error = a37x0_periph_create_gate(clkdom, gate,
95 dev_id);
96 if (error)
97 goto fail;
98
99 fail:
100
101 return (error);
102 }
103