/linux/Documentation/devicetree/bindings/interrupt-controller/ |
H A D | csky,apb-intc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/csky,apb-intc.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: C-SKY APB Interrupt Controller 10 - Guo Ren <guoren@kernel.org> 13 C-SKY APB Interrupt Controller is a simple soc interrupt controller on the apb 16 - csky,apb-intc is used in a lot of csky fpgas and socs, it support 64 irq nums. 17 - csky,dual-apb-intc consists of 2 apb-intc and 128 irq nums supported. 18 - csky,gx6605s-intc is gx6605s soc internal irq interrupt controller, 64 irq nums. [all …]
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H A D | starfive,jh8100-intc.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 3 --- 4 $id: http://devicetree.org/schemas/interrupt-controller/starfive,jh8100-intc.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 11 to handle high-level input interrupt signals. It also send the output 12 interrupt signal to RISC-V PLIC. 15 - Changhuang Liang <changhuang.liang@starfivetech.com> 19 const: starfive,jh8100-intc 25 description: APB clock for the interrupt controller 29 description: APB reset for the interrupt controller [all …]
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/linux/arch/arc/boot/dts/ |
H A D | axc001.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only 3 * Copyright (C) 2013-15 Synopsys, Inc. (www.synopsys.com) 15 #address-cells = <2>; 16 #size-cells = <2>; 19 compatible = "simple-bus"; 20 #address-cells = <1>; 21 #size-cells = <1>; 26 #clock-cells = <0>; 27 compatible = "fixed-clock"; 28 clock-frequency = <750000000>; [all …]
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H A D | axc003_idu.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only 7 * Device tree for AXC003 CPU card: HS38x2 (Dual Core) with IDU intc 14 #address-cells = <2>; 15 #size-cells = <2>; 18 compatible = "simple-bus"; 19 #address-cells = <1>; 20 #size-cells = <1>; 24 input_clk: input-clk { 25 #clock-cells = <0>; 26 compatible = "fixed-clock"; [all …]
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H A D | axc003.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only 3 * Copyright (C) 2014-15 Synopsys, Inc. (www.synopsys.com) 14 #address-cells = <2>; 15 #size-cells = <2>; 18 compatible = "simple-bus"; 19 #address-cells = <1>; 20 #size-cells = <1>; 24 input_clk: input-clk { 25 #clock-cells = <0>; 26 compatible = "fixed-clock"; [all …]
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H A D | vdk_axc003_idu.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only 8 * HS38x2 (Dual Core) with IDU intc (VDK version) 15 #address-cells = <1>; 16 #size-cells = <1>; 19 compatible = "simple-bus"; 20 #address-cells = <1>; 21 #size-cells = <1>; 26 #clock-cells = <0>; 27 compatible = "fixed-clock"; 28 clock-frequency = <50000000>; [all …]
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H A D | vdk_axc003.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only 14 #address-cells = <1>; 15 #size-cells = <1>; 18 compatible = "simple-bus"; 19 #address-cells = <1>; 20 #size-cells = <1>; 25 #clock-cells = <0>; 26 compatible = "fixed-clock"; 27 clock-frequency = <50000000>; 30 core_intc: archs-intc@cpu { [all …]
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H A D | hsdk.dts | 1 // SPDX-License-Identifier: GPL-2.0-only 9 /dts-v1/; 11 #include <dt-bindings/gpio/gpio.h> 12 #include <dt-bindings/reset/snps,hsdk-reset.h> 18 #address-cells = <2>; 19 #size-cells = <2>; 22 … "earlycon=uart8250,mmio32,0xf0005000,115200n8 console=ttyS0,115200n8 debug print-fatal-signals=1"; 30 #address-cells = <1>; 31 #size-cells = <0>; 62 input_clk: input-clk { [all …]
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H A D | abilis_tb10x.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only 12 compatible = "abilis,arc-tb10x"; 13 #address-cells = <1>; 14 #size-cells = <1>; 17 #address-cells = <1>; 18 #size-cells = <0>; 28 compatible = "snps,arc-timer"; 30 interrupt-parent = <&intc>; 36 compatible = "snps,arc-timer"; 41 #address-cells = <1>; [all …]
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/linux/arch/riscv/boot/dts/sophgo/ |
H A D | sg2044.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 6 #include <dt-bindings/clock/sophgo,sg2044-pll.h> 7 #include <dt-bindings/clock/sophgo,sg2044-clk.h> 8 #include <dt-bindings/interrupt-controller/irq.h> 9 #include <dt-bindings/gpio/gpio.h> 10 #include <dt-bindings/pinctrl/pinctrl-sg2044.h> 12 #include "sg2044-cpus.dtsi" 13 #include "sg2044-reset.h" 24 compatible = "fixed-clock"; 25 clock-output-names = "osc"; [all …]
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/linux/drivers/irqchip/ |
H A D | irq-csky-apb-intc.c | 1 // SPDX-License-Identifier: GPL-2.0 2 // Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd. 44 * IFR_offset is NEN_offset - 8. 50 unsigned long ifr = ct->regs.mask - 8; in irq_ck_mask_set_bit() 51 u32 mask = d->mask; in irq_ck_mask_set_bit() 53 guard(raw_spinlock)(&gc->lock); in irq_ck_mask_set_bit() 54 *ct->mask_cache |= mask; in irq_ck_mask_set_bit() 55 irq_reg_writel(gc, *ct->mask_cache, ct->regs.mask); in irq_ck_mask_set_bit() 65 gc->reg_base = reg_base; in ck_set_gc() 66 gc->chip_types[0].regs.mask = mask_reg; in ck_set_gc() [all …]
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/linux/arch/arm/boot/dts/marvell/ |
H A D | pxa910.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only 7 #include <dt-bindings/clock/marvell,pxa910.h> 10 #address-cells = <1>; 11 #size-cells = <1>; 22 #address-cells = <1>; 23 #size-cells = <1>; 24 compatible = "simple-bus"; 25 interrupt-parent = <&intc>; 28 L2: l2-cache { 29 compatible = "marvell,tauros2-cache"; [all …]
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H A D | pxa168.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only 7 #include <dt-bindings/clock/marvell,pxa168.h> 10 #address-cells = <1>; 11 #size-cells = <1>; 22 #address-cells = <1>; 23 #size-cells = <1>; 24 compatible = "simple-bus"; 25 interrupt-parent = <&intc>; 29 compatible = "mrvl,axi-bus", "simple-bus"; 30 #address-cells = <1>; [all …]
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H A D | mmp2.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only 7 #include <dt-bindings/clock/marvell,mmp2.h> 8 #include <dt-bindings/power/marvell,mmp2.h> 9 #include <dt-bindings/clock/marvell,mmp2-audio.h> 12 #address-cells = <1>; 13 #size-cells = <1>; 25 #address-cells = <1>; 26 #size-cells = <1>; 27 compatible = "simple-bus"; 28 interrupt-parent = <&intc>; [all …]
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/linux/arch/arm/boot/dts/unisoc/ |
H A D | rda8810pl.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 9 #include <dt-bindings/interrupt-controller/irq.h> 13 interrupt-parent = <&intc>; 14 #address-cells = <1>; 15 #size-cells = <1>; 18 #address-cells = <1>; 19 #size-cells = <0>; 23 compatible = "arm,cortex-a5"; 29 compatible = "mmio-sram"; 31 #address-cells = <1>; [all …]
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/linux/arch/arc/plat-axs10x/ |
H A D | axs10x.c | 1 // SPDX-License-Identifier: GPL-2.0-only 5 * Copyright (C) 2013-15 Synopsys, Inc. (www.synopsys.com) 11 #include <asm/asm-offsets.h> 30 * Peripherals on CPU Card and Mother Board are wired to cpu intc via in axs10x_enable_gpio_intc_wire() 31 * intermediate DW APB GPIO blocks (mainly for debouncing) in axs10x_enable_gpio_intc_wire() 33 * --------------------- in axs10x_enable_gpio_intc_wire() 34 * | snps,arc700-intc | in axs10x_enable_gpio_intc_wire() 35 * --------------------- in axs10x_enable_gpio_intc_wire() 37 * ------------------- ------------------- in axs10x_enable_gpio_intc_wire() 38 * | snps,dw-apb-gpio | | snps,dw-apb-gpio | in axs10x_enable_gpio_intc_wire() [all …]
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/linux/arch/arm64/boot/dts/intel/ |
H A D | socfpga_agilex.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 6 /dts-v1/; 7 #include <dt-bindings/reset/altr,rst-mgr-s10.h> 8 #include <dt-bindings/gpio/gpio.h> 9 #include <dt-bindings/interrupt-controller/arm-gic.h> 10 #include <dt-bindings/clock/agilex-clock.h> 13 compatible = "intel,socfpga-agilex"; 14 #address-cells = <2>; 15 #size-cells = <2>; 17 reserved-memory { [all …]
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/linux/arch/arm64/boot/dts/altera/ |
H A D | socfpga_stratix10.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only 6 /dts-v1/; 7 #include <dt-bindings/reset/altr,rst-mgr-s10.h> 8 #include <dt-bindings/gpio/gpio.h> 9 #include <dt-bindings/clock/stratix10-clock.h> 12 compatible = "altr,socfpga-stratix10"; 13 #address-cells = <2>; 14 #size-cells = <2>; 16 reserved-memory { 17 #address-cells = <2>; [all …]
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/linux/arch/arc/plat-hsdk/ |
H A D | platform.c | 1 // SPDX-License-Identifier: GPL-2.0-only 33 * Peripherals on CPU Card are wired to cpu intc via intermediate in hsdk_enable_gpio_intc_wire() 34 * DW APB GPIO blocks (mainly for debouncing) in hsdk_enable_gpio_intc_wire() 36 * --------------------- in hsdk_enable_gpio_intc_wire() 37 * | snps,archs-intc | in hsdk_enable_gpio_intc_wire() 38 * --------------------- in hsdk_enable_gpio_intc_wire() 40 * ---------------------- in hsdk_enable_gpio_intc_wire() 41 * | snps,archs-idu-intc | in hsdk_enable_gpio_intc_wire() 42 * ---------------------- in hsdk_enable_gpio_intc_wire() 46 * ------------------- in hsdk_enable_gpio_intc_wire() [all …]
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/linux/arch/mips/boot/dts/loongson/ |
H A D | loongson1.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 3 * Copyright (c) 2023-2025 Keguang Zhang <keguang.zhang@gmail.com> 6 /dts-v1/; 8 #include <dt-bindings/clock/loongson,ls1x-clk.h> 9 #include <dt-bindings/interrupt-controller/irq.h> 12 #address-cells = <1>; 13 #size-cells = <1>; 16 compatible = "fixed-clock"; 17 clock-output-names = "xtal"; 18 #clock-cells = <0>; [all …]
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/linux/arch/arm64/boot/dts/amlogic/ |
H A D | amlogic-a5.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 6 #include "amlogic-a4-common.dtsi" 7 #include "amlogic-a5-reset.h" 8 #include <dt-bindings/power/amlogic,a5-pwrc.h> 11 #address-cells = <2>; 12 #size-cells = <0>; 16 compatible = "arm,cortex-a55"; 18 enable-method = "psci"; 23 compatible = "arm,cortex-a55"; 25 enable-method = "psci"; [all …]
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/linux/arch/riscv/boot/dts/canaan/ |
H A D | k210.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+ 3 * Copyright (C) 2019-20 Sean Anderson <seanga2@gmail.com> 6 #include <dt-bindings/clock/k210-clk.h> 7 #include <dt-bindings/pinctrl/k210-fpioa.h> 8 #include <dt-bindings/reset/k210-rst.h> 12 * Although the K210 is a 64-bit CPU, the address bus is only 32-bits 15 #address-cells = <1>; 16 #size-cells = <1>; 17 compatible = "canaan,kendryte-k210"; 21 * Since this is a non-ratified draft specification, the kernel does not [all …]
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/linux/arch/arm/boot/dts/intel/socfpga/ |
H A D | socfpga.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+ 6 #include <dt-bindings/reset/altr,rst-mgr.h> 9 #address-cells = <1>; 10 #size-cells = <1>; 22 #address-cells = <1>; 23 #size-cells = <0>; 24 enable-method = "altr,socfpga-smp"; 27 compatible = "arm,cortex-a9"; 30 next-level-cache = <&L2>; 33 compatible = "arm,cortex-a9"; [all …]
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/linux/arch/arm/boot/dts/moxa/ |
H A D | moxart.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* moxart.dtsi - Device Tree Include file for MOXA ART family SoC 7 #include <dt-bindings/interrupt-controller/irq.h> 10 #address-cells = <1>; 11 #size-cells = <1>; 14 interrupt-parent = <&intc>; 17 #address-cells = <1>; 18 #size-cells = <0>; 28 #address-cells = <1>; 29 #size-cells = <0>; [all …]
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/linux/arch/arm/boot/dts/nspire/ |
H A D | nspire.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only 7 #address-cells = <1>; 8 #size-cells = <1>; 9 interrupt-parent = <&intc>; 12 #address-cells = <1>; 13 #size-cells = <0>; 16 compatible = "arm,arm926ej-s"; 27 compatible = "mmio-sram"; 29 #address-cells = <1>; 30 #size-cells = <1>; [all …]
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