1*6428fcf2SKeguang Zhang// SPDX-License-Identifier: GPL-2.0 2*6428fcf2SKeguang Zhang/* 3*6428fcf2SKeguang Zhang * Copyright (c) 2023-2025 Keguang Zhang <keguang.zhang@gmail.com> 4*6428fcf2SKeguang Zhang */ 5*6428fcf2SKeguang Zhang 6*6428fcf2SKeguang Zhang/dts-v1/; 7*6428fcf2SKeguang Zhang 8*6428fcf2SKeguang Zhang#include <dt-bindings/clock/loongson,ls1x-clk.h> 9*6428fcf2SKeguang Zhang#include <dt-bindings/interrupt-controller/irq.h> 10*6428fcf2SKeguang Zhang 11*6428fcf2SKeguang Zhang/ { 12*6428fcf2SKeguang Zhang #address-cells = <1>; 13*6428fcf2SKeguang Zhang #size-cells = <1>; 14*6428fcf2SKeguang Zhang 15*6428fcf2SKeguang Zhang xtal: clock { 16*6428fcf2SKeguang Zhang compatible = "fixed-clock"; 17*6428fcf2SKeguang Zhang clock-output-names = "xtal"; 18*6428fcf2SKeguang Zhang #clock-cells = <0>; 19*6428fcf2SKeguang Zhang }; 20*6428fcf2SKeguang Zhang 21*6428fcf2SKeguang Zhang cpus { 22*6428fcf2SKeguang Zhang #address-cells = <1>; 23*6428fcf2SKeguang Zhang #size-cells = <0>; 24*6428fcf2SKeguang Zhang 25*6428fcf2SKeguang Zhang cpu0: cpu@0 { 26*6428fcf2SKeguang Zhang reg = <0>; 27*6428fcf2SKeguang Zhang device_type = "cpu"; 28*6428fcf2SKeguang Zhang clocks = <&clkc LS1X_CLKID_CPU>; 29*6428fcf2SKeguang Zhang #clock-cells = <1>; 30*6428fcf2SKeguang Zhang }; 31*6428fcf2SKeguang Zhang }; 32*6428fcf2SKeguang Zhang 33*6428fcf2SKeguang Zhang cpu_intc: interrupt-controller { 34*6428fcf2SKeguang Zhang compatible = "mti,cpu-interrupt-controller"; 35*6428fcf2SKeguang Zhang interrupt-controller; 36*6428fcf2SKeguang Zhang #interrupt-cells = <1>; 37*6428fcf2SKeguang Zhang #address-cells = <0>; 38*6428fcf2SKeguang Zhang }; 39*6428fcf2SKeguang Zhang 40*6428fcf2SKeguang Zhang soc: bus@1fd00000 { 41*6428fcf2SKeguang Zhang compatible = "simple-bus"; 42*6428fcf2SKeguang Zhang #address-cells = <1>; 43*6428fcf2SKeguang Zhang #size-cells = <1>; 44*6428fcf2SKeguang Zhang ranges = <0x0 0x1fd00000 0x130000>; 45*6428fcf2SKeguang Zhang 46*6428fcf2SKeguang Zhang intc0: interrupt-controller@1040 { 47*6428fcf2SKeguang Zhang compatible = "loongson,ls1x-intc"; 48*6428fcf2SKeguang Zhang reg = <0x1040 0x18>; 49*6428fcf2SKeguang Zhang interrupt-controller; 50*6428fcf2SKeguang Zhang interrupt-parent = <&cpu_intc>; 51*6428fcf2SKeguang Zhang interrupts = <2>; 52*6428fcf2SKeguang Zhang #interrupt-cells = <2>; 53*6428fcf2SKeguang Zhang }; 54*6428fcf2SKeguang Zhang 55*6428fcf2SKeguang Zhang intc1: interrupt-controller@1058 { 56*6428fcf2SKeguang Zhang compatible = "loongson,ls1x-intc"; 57*6428fcf2SKeguang Zhang reg = <0x1058 0x18>; 58*6428fcf2SKeguang Zhang interrupt-controller; 59*6428fcf2SKeguang Zhang interrupt-parent = <&cpu_intc>; 60*6428fcf2SKeguang Zhang interrupts = <3>; 61*6428fcf2SKeguang Zhang #interrupt-cells = <2>; 62*6428fcf2SKeguang Zhang }; 63*6428fcf2SKeguang Zhang 64*6428fcf2SKeguang Zhang intc2: interrupt-controller@1070 { 65*6428fcf2SKeguang Zhang compatible = "loongson,ls1x-intc"; 66*6428fcf2SKeguang Zhang reg = <0x1070 0x18>; 67*6428fcf2SKeguang Zhang interrupt-controller; 68*6428fcf2SKeguang Zhang interrupt-parent = <&cpu_intc>; 69*6428fcf2SKeguang Zhang interrupts = <4>; 70*6428fcf2SKeguang Zhang #interrupt-cells = <2>; 71*6428fcf2SKeguang Zhang }; 72*6428fcf2SKeguang Zhang 73*6428fcf2SKeguang Zhang intc3: interrupt-controller@1088 { 74*6428fcf2SKeguang Zhang compatible = "loongson,ls1x-intc"; 75*6428fcf2SKeguang Zhang reg = <0x1088 0x18>; 76*6428fcf2SKeguang Zhang interrupt-controller; 77*6428fcf2SKeguang Zhang interrupt-parent = <&cpu_intc>; 78*6428fcf2SKeguang Zhang interrupts = <5>; 79*6428fcf2SKeguang Zhang #interrupt-cells = <2>; 80*6428fcf2SKeguang Zhang }; 81*6428fcf2SKeguang Zhang 82*6428fcf2SKeguang Zhang gpio0: gpio@10c0 { 83*6428fcf2SKeguang Zhang compatible = "loongson,ls1x-gpio"; 84*6428fcf2SKeguang Zhang reg = <0x10c0 0x4>; 85*6428fcf2SKeguang Zhang gpio-controller; 86*6428fcf2SKeguang Zhang #gpio-cells = <2>; 87*6428fcf2SKeguang Zhang }; 88*6428fcf2SKeguang Zhang 89*6428fcf2SKeguang Zhang gpio1: gpio@10c4 { 90*6428fcf2SKeguang Zhang compatible = "loongson,ls1x-gpio"; 91*6428fcf2SKeguang Zhang reg = <0x10c4 0x4>; 92*6428fcf2SKeguang Zhang gpio-controller; 93*6428fcf2SKeguang Zhang #gpio-cells = <2>; 94*6428fcf2SKeguang Zhang }; 95*6428fcf2SKeguang Zhang }; 96*6428fcf2SKeguang Zhang 97*6428fcf2SKeguang Zhang apb: bus@1fe40000 { 98*6428fcf2SKeguang Zhang compatible = "simple-bus"; 99*6428fcf2SKeguang Zhang #address-cells = <1>; 100*6428fcf2SKeguang Zhang #size-cells = <1>; 101*6428fcf2SKeguang Zhang ranges = <0x0 0x1fe40000 0xc0000>; 102*6428fcf2SKeguang Zhang 103*6428fcf2SKeguang Zhang uart0: serial@0 { 104*6428fcf2SKeguang Zhang compatible = "ns16550a"; 105*6428fcf2SKeguang Zhang reg = <0x0 0x8>; 106*6428fcf2SKeguang Zhang clocks = <&clkc LS1X_CLKID_APB>; 107*6428fcf2SKeguang Zhang interrupt-parent = <&intc0>; 108*6428fcf2SKeguang Zhang interrupts = <2 IRQ_TYPE_LEVEL_HIGH>; 109*6428fcf2SKeguang Zhang status = "disabled"; 110*6428fcf2SKeguang Zhang }; 111*6428fcf2SKeguang Zhang 112*6428fcf2SKeguang Zhang uart1: serial@4000 { 113*6428fcf2SKeguang Zhang compatible = "ns16550a"; 114*6428fcf2SKeguang Zhang reg = <0x4000 0x8>; 115*6428fcf2SKeguang Zhang clocks = <&clkc LS1X_CLKID_APB>; 116*6428fcf2SKeguang Zhang interrupt-parent = <&intc0>; 117*6428fcf2SKeguang Zhang status = "disabled"; 118*6428fcf2SKeguang Zhang }; 119*6428fcf2SKeguang Zhang 120*6428fcf2SKeguang Zhang uart2: serial@8000 { 121*6428fcf2SKeguang Zhang compatible = "ns16550a"; 122*6428fcf2SKeguang Zhang reg = <0x8000 0x8>; 123*6428fcf2SKeguang Zhang clocks = <&clkc LS1X_CLKID_APB>; 124*6428fcf2SKeguang Zhang interrupt-parent = <&intc0>; 125*6428fcf2SKeguang Zhang status = "disabled"; 126*6428fcf2SKeguang Zhang }; 127*6428fcf2SKeguang Zhang 128*6428fcf2SKeguang Zhang uart3: serial@c000 { 129*6428fcf2SKeguang Zhang compatible = "ns16550a"; 130*6428fcf2SKeguang Zhang reg = <0xc000 0x8>; 131*6428fcf2SKeguang Zhang clocks = <&clkc LS1X_CLKID_APB>; 132*6428fcf2SKeguang Zhang interrupt-parent = <&intc0>; 133*6428fcf2SKeguang Zhang status = "disabled"; 134*6428fcf2SKeguang Zhang }; 135*6428fcf2SKeguang Zhang }; 136*6428fcf2SKeguang Zhang}; 137