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/freebsd/sys/contrib/device-tree/Bindings/interrupt-controller/
H A Driscv,cpu-intc.txt1 RISC-V Hart-Level Interrupt Controller (HLIC)
2 ---------------------------------------------
4 RISC-V cores include Control Status Registers (CSRs) which are local to each
5 CPU core (HART in RISC-V terminology) and can be read or written by software.
10 The RISC-V supervisor ISA manual specifies three interrupt sources that are
13 timer interrupt comes from an architecturally mandated real-time timer that is
14 controlled via Supervisor Binary Interface (SBI) calls and CSR reads. External
16 via the platform-level interrupt controller (PLIC).
18 All RISC-V systems that conform to the supervisor ISA specification are
27 - compatible : "riscv,cpu-intc"
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H A Driscv,cpu-intc.yaml1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/riscv,cpu-intc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V Hart-Level Interrupt Controller (HLIC)
10 RISC-V cores include Control Status Registers (CSRs) which are local to
11 each CPU core (HART in RISC-V terminology) and can be read or written by
16 The RISC-V supervisor ISA manual specifies three interrupt sources that are
19 cores. The timer interrupt comes from an architecturally mandated real-
20 time timer that is controlled via Supervisor Binary Interface (SBI) calls
[all …]
H A Driscv,imsics.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/riscv,imsics.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V Incoming MSI Controller (IMSIC)
10 - Anup Patel <anup@brainfault.org>
13 The RISC-V advanced interrupt architecture (AIA) defines a per-CPU incoming
14 MSI controller (IMSIC) for handling MSIs in a RISC-V platform. The RISC-V
15 AIA specification can be found at https://github.com/riscv/riscv-aia.
17 The IMSIC is a per-CPU (or per-HART) device with separate interrupt file
[all …]
H A Dsifive,plic-1.0.0.txt1 SiFive Platform-Level Interrupt Controller (PLIC)
2 -------------------------------------------------
4 SiFive SOCs include an implementation of the Platform-Level Interrupt Controller
5 (PLIC) high-level specification in the RISC-V Privileged Architecture
10 in an 4 core system with 2-way SMT, you have 8 harts and probably at least two
11 privilege modes per hart; machine mode and supervisor mode.
13 Each interrupt can be enabled on per-context basis. Any context can claim
21 While the PLIC supports both edge-triggered and level-triggered interrupts,
23 specified in the PLIC device-tree binding.
25 While the RISC-V ISA doesn't specify a memory layout for the PLIC, the
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H A Dsifive,plic-1.0.0.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
4 ---
5 $id: http://devicetree.org/schemas/interrupt-controller/sifive,plic-1.0.0.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: SiFive Platform-Level Interrupt Controller (PLIC)
11 SiFive SoCs and other RISC-V SoCs include an implementation of the
12 Platform-Level Interrupt Controller (PLIC) high-level specification in
13 the RISC-V Privileged Architecture specification. The PLIC connects all
18 in an 4 core system with 2-way SMT, you have 8 harts and probably at least two
19 privilege modes per hart; machine mode and supervisor mode.
[all …]
/freebsd/sys/contrib/device-tree/Bindings/riscv/
H A Dextensions.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V ISA extensions
10 - Paul Walmsley <paul.walmsley@sifive.com>
11 - Palmer Dabbelt <palmer@sifive.com>
12 - Conor Dooley <conor@kernel.org>
15 RISC-V has a large number of extensions, some of which are "standard"
16 extensions, meaning they are ratified by RISC-V International, and others
36 Identifies the specific RISC-V instruction set architecture
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/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVFeatures.td1 //===-- RISCVFeatures.td - RISC-V Features and Extensions --*- tablegen -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 //===----------------------------------------------------------------------===//
10 // RISC-V subtarget features and instruction predicates.
11 //===----------------------------------------------------------------------===//
13 // Subclass of SubtargetFeature to be used when the feature is also a RISC-V
16 // name - Name of the extension in lower case.
17 // major - Major version of extension.
18 // minor - Minor version of extension.
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H A DRISCVSystemOperands.td1 //===- RISCVSystemOperands.td ------------------------------*- tablegen -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
10 // RISC-V system instruction.
12 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
18 //===----------------------------------------------------------------------===//
30 // Privilege Access: Read and Write = 0, 1, 2; Read-Only = 3.
32 // bits<2> ReadWrite = op{11 - 10};
33 // bits<2> XMode = op{9 - 8};
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/freebsd/lib/libpmc/pmu-events/arch/arm64/
H A Drecommended.json3 "PublicDescription": "Attributable Level 1 data cache access, read",
9 "PublicDescription": "Attributable Level 1 data cache access, write",
15 "PublicDescription": "Attributable Level 1 data cache refill, read",
21 "PublicDescription": "Attributable Level 1 data cache refill, write",
27 "PublicDescription": "Attributable Level 1 data cache refill, inner",
33 "PublicDescription": "Attributable Level 1 data cache refill, outer",
39 "PublicDescription": "Attributable Level 1 data cache Write-Back, victim",
42 "BriefDescription": "L1D cache Write-Back, victim"
45 "PublicDescription": "Level 1 data cache Write-Back, cleaning and coherency",
48 "BriefDescription": "L1D cache Write-Back, cleaning and coherency"
[all …]
H A Darmv8-recommended.json3 "PublicDescription": "Attributable Level 1 data cache access, read",
9 "PublicDescription": "Attributable Level 1 data cache access, write",
15 "PublicDescription": "Attributable Level 1 data cache refill, read",
21 "PublicDescription": "Attributable Level 1 data cache refill, write",
27 "PublicDescription": "Attributable Level 1 data cache refill, inner",
33 "PublicDescription": "Attributable Level 1 data cache refill, outer",
39 "PublicDescription": "Attributable Level 1 data cache Write-Back, victim",
42 "BriefDescription": "L1D cache Write-Back, victim"
45 "PublicDescription": "Level 1 data cache Write-Back, cleaning and coherency",
48 "BriefDescription": "L1D cache Write-Back, cleaning and coherency"
[all …]
/freebsd/sys/powerpc/include/
H A Dpte.h1 /*-
2 * SPDX-License-Identifier: BSD-4-Clause
46 /* 32-bit PTE */
56 /* 64-bit (long) PTE */
82 /* 32-bit PTE definitions */
100 #define PTE_SW 0x00000001 /* Super. Write-Only (U: RO, S: RW) */
101 #define PTE_BW 0x00000002 /* Supervisor (U: RW, S: RW) */
108 /* 64-bit PTE definitions */
125 #define EXTEND_PTE(x) UINT64_C(x) /* make constants 64-bit */
141 #define LPTE_SW EXTEND_PTE( PTE_SW ) /* Super. Write-Only */
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H A Ducontext.h1 /*-
2 * SPDX-License-Identifier: BSD-4-Clause
50 __uint64_t mc_vsxfpreg[32]; /* low-order half of VSR0-31 */
65 uint64_t mc_vsxfpreg[32]; /* low-order half of VSR0-31 */
69 /* GPRs and supervisor-level regs */
81 /* floating-point state */
/freebsd/share/man/man7/
H A Dmitigations.71 .\"-
2 .\" SPDX-License-Identifer: BSD-2-Clause
42 Some of these mitigations have run-time controls to enable them on a global
43 or per-process basis, some are optionally enabled or disabled at compile time,
48 .Bl -bullet -compact
58 Relocation Read-Only (RELRO)
64 Supervisor Mode Memory Protection
107 ASLR can be enabled on both a global and per-process basis.
110 knobs for 32- and 64-bit processes.
111 It can be or disabled on a per-process basis via
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/freebsd/sys/riscv/riscv/
H A Didentcpu.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2015-2016 Ruslan Bukin <br@bsdpad.com>
11 * FA8750-10-C-0237 ("CTSRD"), as part of the DARPA CRASH research programme.
75 /* Supervisor-mode extension support. */
84 u_int isa_extensions; /* Single-letter extensions. */
97 * Micro-architecture tables.
104 #define MARCHID_END { -1ul, NULL }
106 /* Open-source RISC-V architecture IDs; globally allocated. */
116 { MARCHID_SIFIVE_U7, "6/7/P200/X200-Series Processor" },
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H A Dlocore.S1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2015-2018 Ruslan Bukin <br@bsdpad.com>
6 * Copyright (c) 2019-2021 Mitchell Horne <mhorne@FreeBSD.org>
7 * Copyright (c) 2022-2024 The FreeBSD Foundation
11 * FA8750-10-C-0237 ("CTSRD"), as part of the DARPA CRASH research programme.
58 * - a0 = hart ID
59 * - a1 = dtbp
78 * We must jump to mpentry in the non-BSP case because the offset is
79 * too large to fit in a 12-bit branch immediate.
[all …]
H A Dplic.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
10 * and Technology) under DARPA contract HR0011-18-C-0016 ("ECATS"), as part of
52 #include <dt-bindings/interrupt-controller/irq.h>
70 (_sc->contexts[_cpu].enable_offset + ((_irq) / 32) * sizeof(uint32_t))
72 (_sc->contexts[_cpu].context_offset + PLIC_CONTEXT_THRESHOLD)
74 (_sc->contexts[_cpu].context_offset + PLIC_CONTEXT_CLAIM)
107 { "sifive,plic-1.0.0", 1 },
108 { "thead,c900-plic", 1 },
113 bus_read_4(sc->mem_res, (reg))
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/freebsd/sys/contrib/xen/arch-x86/
H A Dcpufeatureset.h2 * arch-x86/cpufeatureset.h
32 * Simply #include <public/arch-x86/cpufeatureset.h>
78 * first space in the comment immediately following the feature value. Note -
91 * Lower case => Can be opted-in to, but not available by default.
94 /* Intel-defined CPU features, CPUID level 0x00000001.edx, word 0 */
100 XEN_CPUFEATURE(MSR, 0*32+ 5) /*A Model-Specific Registers, RDMSR, WRMSR */
111 XEN_CPUFEATURE(PSE36, 0*32+17) /*S 36-bit PSEs */
118 XEN_CPUFEATURE(SSE2, 0*32+26) /*A Streaming SIMD Extensions-2 */
120 XEN_CPUFEATURE(HTT, 0*32+28) /*!A Hyper-Threading Technology */
124 /* Intel-defined CPU features, CPUID level 0x00000001.ecx, word 1 */
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/freebsd/contrib/libarchive/libarchive/
H A Darchive_write_add_filter_lrzip.c1 /*-
2 * Copyright (c) 2003-2007 Tim Kientzle
70 data->pdata = __archive_write_program_allocate("lrzip"); in archive_write_add_filter_lrzip()
71 if (data->pdata == NULL) { in archive_write_add_filter_lrzip()
77 f->name = "lrzip"; in archive_write_add_filter_lrzip()
78 f->code = ARCHIVE_FILTER_LRZIP; in archive_write_add_filter_lrzip()
79 f->data = data; in archive_write_add_filter_lrzip()
80 f->open = archive_write_lrzip_open; in archive_write_add_filter_lrzip()
81 f->options = archive_write_lrzip_options; in archive_write_add_filter_lrzip()
82 f->writ in archive_write_add_filter_lrzip()
[all...]
H A Darchive_write_add_filter_lzop.c1 /*-
67 unsigned char level;
114 /* Level */
117 * -OS Unix
118 * -Stdout
119 * -Stdin
120 * -Adler32 used for uncompressed data 4 bytes */
150 f->name = "lzop"; in archive_write_add_filter_lzop()
151 f->code = ARCHIVE_FILTER_LZOP; in archive_write_add_filter_lzop()
152 f->dat in archive_write_add_filter_lzop()
68 unsigned char level; global() member
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H A Darchive_write_add_filter_bzip2.c1 /*-
2 * Copyright (c) 2003-2007 Tim Kientzle
86 archive_check_magic(&a->archive, ARCHIVE_WRITE_MAGIC, in archive_write_add_filter_bzip2()
91 archive_set_error(&a->archive, ENOMEM, "Out of memory"); in archive_write_add_filter_bzip2()
94 data->compression_level = 9; /* default */ in archive_write_add_filter_bzip2()
96 f->data = data; in archive_write_add_filter_bzip2()
97 f->options = &archive_compressor_bzip2_options; in archive_write_add_filter_bzip2()
98 f->close = &archive_compressor_bzip2_close; in archive_write_add_filter_bzip2()
99 f->free = &archive_compressor_bzip2_free; in archive_write_add_filter_bzip2()
100 f->open = &archive_compressor_bzip2_open; in archive_write_add_filter_bzip2()
[all …]
H A Darchive_write_add_filter_zstd.c1 /*-
3 * Copyright (c) 2023-2024 Klara, Inc.
85 #define CLEVEL_MIN -99
86 #define CLEVEL_STD_MIN 0 /* prior to 1.3.4 and more recent without using --fast */
88 #define CLEVEL_STD_MAX 19 /* without using --ultra */
120 archive_check_magic(&a->archive, ARCHIVE_WRITE_MAGIC, in archive_write_add_filter_zstd()
125 archive_set_error(&a->archive, ENOMEM, "Out of memory"); in archive_write_add_filter_zstd()
128 f->data = data; in archive_write_add_filter_zstd()
129 f->open = &archive_compressor_zstd_open; in archive_write_add_filter_zstd()
130 f->options = &archive_compressor_zstd_options; in archive_write_add_filter_zstd()
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/freebsd/sys/amd64/include/
H A Dpte.h1 /*-
2 * SPDX-License-Identifier: BSD-3-Clause
47 * Page-directory and page-table entries follow this format, with a few
50 /* ---- Intel Nomenclature ---- */
53 #define X86_PG_U 0x004 /* U/S User/Supervisor */
66 #define X86_PG_NX (1ul<<63) /* No-execute */
69 /* Page level cache control fields used to determine the PAT type */
99 #define PGEX_RSV 0x08 /* reserved PTE field is non-zero */
102 #define PGEX_SGX 0x8000 /* SGX-related */
/freebsd/contrib/llvm-project/llvm/lib/TargetParser/
H A DRISCVISAInfo.cpp1 //===-- RISCVISAInfo.cpp - RISC-V Arch String Parser ----------------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
84 outs() << "All available -march extensions for RISC-V\n\n"; in printSupportedExtensions()
103 PrintExtension(E.first, Version, DescMap["experimental-" + E.first]); in printSupportedExtensions()
114 outs() << "\nUse -march to specify the target's extension.\n" in printSupportedExtensions()
115 "For example, clang -march=rv32i_v1p0\n"; in printSupportedExtensions()
121 outs() << "Extensions enabled for the given RISC-V target\n\n"; in printEnabledExtensions()
141 if (EnabledFeatureNames.count("experimental-" + Name.str()) != 0) { in printEnabledExtensions()
149 PrintExtension(E.first, Version, DescMap["experimental-" + E.first]); in printEnabledExtensions()
[all …]
/freebsd/sys/contrib/device-tree/Bindings/
H A Dtrivial-devices.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/trivial-devices.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Rob Herring <robh@kernel.org>
27 spi-max-frequency: true
32 - enum:
34 - acbel,fsg032
35 … # SMBus/I2C Digital Temperature Sensor in 6-Pin SOT with SMBus Alert and Over Temperature Pin
36 - ad,ad7414 # Deprecated, use adi,ad7414
[all …]
/freebsd/contrib/llvm-project/clang/lib/Headers/
H A Duintrintrin.h1 /*===------------------ uintrintrin.h - UINTR intrinsics -------------------===
5 * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 *===-----------------------------------------------------------------------===
33 /// 64-bit mode, and software is not executing inside an enclave; otherwise,
34 /// each causes an invalid-opcode exception. Causes a transactional abort if
54 /// 64-bit mode, and software is not executing inside an enclave; otherwise,
55 /// each causes an invalid-opcode exception. Causes a transactional abort if
74 /// if CR4.UINT = 1, the logical processor is in 64-bit mode, and software is
75 /// not executing inside an enclave; otherwise, it causes an invalid-opcode
100 /// CR4.UINT = IA32_UINT_TT[0] = 1, the logical processor is in 64-bit mode,
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