1//===-- RISCVFeatures.td - RISC-V Features and Extensions --*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8 9//===----------------------------------------------------------------------===// 10// RISC-V subtarget features and instruction predicates. 11//===----------------------------------------------------------------------===// 12 13// Subclass of SubtargetFeature to be used when the feature is also a RISC-V 14// extension. Extensions have a version and may be experimental. 15// 16// name - Name of the extension in lower case. 17// major - Major version of extension. 18// minor - Minor version of extension. 19// desc - Description of extension. 20// implies - Extensions or features implied by this extension. 21// fieldname - name of field to create in RISCVSubtarget. By default replaces 22// uses the record name by replacing Feature with Has. 23// value - Value to assign to the field in RISCVSubtarget when this 24// extension is enabled. Usually "true", but can be changed. 25class RISCVExtension<string name, int major, int minor, string desc, 26 list<SubtargetFeature> implies = [], 27 string fieldname = !subst("Feature", "Has", NAME), 28 string value = "true"> 29 : SubtargetFeature<name, fieldname, value, desc, implies> { 30 // MajorVersion - The major version for this extension. 31 int MajorVersion = major; 32 33 // MinorVersion - The minor version for this extension. 34 int MinorVersion = minor; 35 36 // Experimental - Does extension require -menable-experimental-extensions. 37 bit Experimental = false; 38} 39 40// The groupID/bitmask of RISCVExtension is used to retrieve a specific bit value 41// from __riscv_feature_bits based on the groupID and bitmask. 42// groupID - groupID of extension 43// bitPos - bit position of extension bitmask 44class RISCVExtensionBitmask<bits<3> groupID, int bitPos> { 45 int GroupID = groupID; 46 int BitPos = bitPos; 47} 48 49// Version of RISCVExtension to be used for Experimental extensions. This 50// sets the Experimental flag and prepends experimental- to the -mattr name. 51class RISCVExperimentalExtension<string name, int major, int minor, string desc, 52 list<RISCVExtension> implies = [], 53 string fieldname = !subst("Feature", "Has", NAME), 54 string value = "true"> 55 : RISCVExtension<"experimental-"#name, major, minor, desc, implies, 56 fieldname, value> { 57 let Experimental = true; 58} 59 60// Integer Extensions 61 62def FeatureStdExtI 63 : RISCVExtension<"i", 2, 1, 64 "'I' (Base Integer Instruction Set)">, 65 RISCVExtensionBitmask<0, 8>; 66 67def FeatureStdExtE 68 : RISCVExtension<"e", 2, 0, 69 "Implements RV{32,64}E (provides 16 rather than 32 GPRs)">; 70 71def FeatureStdExtZic64b 72 : RISCVExtension<"zic64b", 1, 0, 73 "'Zic64b' (Cache Block Size Is 64 Bytes)">; 74 75def FeatureStdExtZicbom 76 : RISCVExtension<"zicbom", 1, 0, 77 "'Zicbom' (Cache-Block Management Instructions)">; 78def HasStdExtZicbom : Predicate<"Subtarget->hasStdExtZicbom()">, 79 AssemblerPredicate<(all_of FeatureStdExtZicbom), 80 "'Zicbom' (Cache-Block Management Instructions)">; 81 82def FeatureStdExtZicbop 83 : RISCVExtension<"zicbop", 1, 0, 84 "'Zicbop' (Cache-Block Prefetch Instructions)">; 85def HasStdExtZicbop : Predicate<"Subtarget->hasStdExtZicbop()">, 86 AssemblerPredicate<(all_of FeatureStdExtZicbop), 87 "'Zicbop' (Cache-Block Prefetch Instructions)">; 88 89def FeatureStdExtZicboz 90 : RISCVExtension<"zicboz", 1, 0, 91 "'Zicboz' (Cache-Block Zero Instructions)">, 92 RISCVExtensionBitmask<0, 37>; 93def HasStdExtZicboz : Predicate<"Subtarget->hasStdExtZicboz()">, 94 AssemblerPredicate<(all_of FeatureStdExtZicboz), 95 "'Zicboz' (Cache-Block Zero Instructions)">; 96 97def FeatureStdExtZiccamoa 98 : RISCVExtension<"ziccamoa", 1, 0, 99 "'Ziccamoa' (Main Memory Supports All Atomics in A)">; 100 101def FeatureStdExtZiccif 102 : RISCVExtension<"ziccif", 1, 0, 103 "'Ziccif' (Main Memory Supports Instruction Fetch with Atomicity Requirement)">; 104 105def FeatureStdExtZicclsm 106 : RISCVExtension<"zicclsm", 1, 0, 107 "'Zicclsm' (Main Memory Supports Misaligned Loads/Stores)">; 108 109def FeatureStdExtZiccrse 110 : RISCVExtension<"ziccrse", 1, 0, 111 "'Ziccrse' (Main Memory Supports Forward Progress on LR/SC Sequences)">; 112 113def FeatureStdExtZicsr 114 : RISCVExtension<"zicsr", 2, 0, 115 "'zicsr' (CSRs)">; 116def HasStdExtZicsr : Predicate<"Subtarget->hasStdExtZicsr()">, 117 AssemblerPredicate<(all_of FeatureStdExtZicsr), 118 "'Zicsr' (CSRs)">; 119 120def FeatureStdExtZicntr 121 : RISCVExtension<"zicntr", 2, 0, 122 "'Zicntr' (Base Counters and Timers)", 123 [FeatureStdExtZicsr]>; 124 125def FeatureStdExtZicond 126 : RISCVExtension<"zicond", 1, 0, 127 "'Zicond' (Integer Conditional Operations)">, 128 RISCVExtensionBitmask<0, 38>; 129def HasStdExtZicond : Predicate<"Subtarget->hasStdExtZicond()">, 130 AssemblerPredicate<(all_of FeatureStdExtZicond), 131 "'Zicond' (Integer Conditional Operations)">; 132 133def FeatureStdExtZifencei 134 : RISCVExtension<"zifencei", 2, 0, 135 "'Zifencei' (fence.i)">; 136def HasStdExtZifencei : Predicate<"Subtarget->hasStdExtZifencei()">, 137 AssemblerPredicate<(all_of FeatureStdExtZifencei), 138 "'Zifencei' (fence.i)">; 139 140def FeatureStdExtZihintpause 141 : RISCVExtension<"zihintpause", 2, 0, 142 "'Zihintpause' (Pause Hint)">, 143 RISCVExtensionBitmask<0, 40>; 144def HasStdExtZihintpause : Predicate<"Subtarget->hasStdExtZihintpause()">, 145 AssemblerPredicate<(all_of FeatureStdExtZihintpause), 146 "'Zihintpause' (Pause Hint)">; 147 148def FeatureStdExtZihintntl 149 : RISCVExtension<"zihintntl", 1, 0, 150 "'Zihintntl' (Non-Temporal Locality Hints)">, 151 RISCVExtensionBitmask<0, 39>; 152def HasStdExtZihintntl : Predicate<"Subtarget->hasStdExtZihintntl()">, 153 AssemblerPredicate<(all_of FeatureStdExtZihintntl), 154 "'Zihintntl' (Non-Temporal Locality Hints)">; 155 156def FeatureStdExtZihpm 157 : RISCVExtension<"zihpm", 2, 0, 158 "'Zihpm' (Hardware Performance Counters)", 159 [FeatureStdExtZicsr]>; 160 161def FeatureStdExtZimop : RISCVExtension<"zimop", 1, 0, 162 "'Zimop' (May-Be-Operations)">; 163def HasStdExtZimop : Predicate<"Subtarget->hasStdExtZimop()">, 164 AssemblerPredicate<(all_of FeatureStdExtZimop), 165 "'Zimop' (May-Be-Operations)">; 166 167def FeatureStdExtZicfilp 168 : RISCVExperimentalExtension<"zicfilp", 1, 0, 169 "'Zicfilp' (Landing pad)", 170 [FeatureStdExtZicsr]>; 171def HasStdExtZicfilp : Predicate<"Subtarget->hasStdExtZicfilp()">, 172 AssemblerPredicate<(all_of FeatureStdExtZicfilp), 173 "'Zicfilp' (Landing pad)">; 174def NoStdExtZicfilp : Predicate<"!Subtarget->hasStdExtZicfilp()">, 175 AssemblerPredicate<(all_of (not FeatureStdExtZicfilp))>; 176 177def FeatureStdExtZicfiss 178 : RISCVExperimentalExtension<"zicfiss", 1, 0, 179 "'Zicfiss' (Shadow stack)", 180 [FeatureStdExtZicsr, FeatureStdExtZimop]>; 181def HasStdExtZicfiss : Predicate<"Subtarget->hasStdExtZicfiss()">, 182 AssemblerPredicate<(all_of FeatureStdExtZicfiss), 183 "'Zicfiss' (Shadow stack)">; 184def NoHasStdExtZicfiss : Predicate<"!Subtarget->hasStdExtZicfiss()">; 185 186// Multiply Extensions 187 188def FeatureStdExtZmmul 189 : RISCVExtension<"zmmul", 1, 0, 190 "'Zmmul' (Integer Multiplication)">; 191def HasStdExtZmmul : Predicate<"Subtarget->hasStdExtZmmul()">, 192 AssemblerPredicate<(all_of FeatureStdExtZmmul), 193 "'Zmmul' (Integer Multiplication)">; 194 195def FeatureStdExtM 196 : RISCVExtension<"m", 2, 0, 197 "'M' (Integer Multiplication and Division)", 198 [FeatureStdExtZmmul]>, 199 RISCVExtensionBitmask<0, 12>; 200def HasStdExtM : Predicate<"Subtarget->hasStdExtM()">, 201 AssemblerPredicate<(all_of FeatureStdExtM), 202 "'M' (Integer Multiplication and Division)">; 203 204// Atomic Extensions 205 206def FeatureStdExtA 207 : RISCVExtension<"a", 2, 1, 208 "'A' (Atomic Instructions)">, 209 RISCVExtensionBitmask<0, 0>; 210def HasStdExtA : Predicate<"Subtarget->hasStdExtA()">, 211 AssemblerPredicate<(all_of FeatureStdExtA), 212 "'A' (Atomic Instructions)">; 213 214def FeatureStdExtZtso 215 : RISCVExtension<"ztso", 1, 0, 216 "'Ztso' (Memory Model - Total Store Order)">, 217 RISCVExtensionBitmask<0, 47>; 218def HasStdExtZtso : Predicate<"Subtarget->hasStdExtZtso()">, 219 AssemblerPredicate<(all_of FeatureStdExtZtso), 220 "'Ztso' (Memory Model - Total Store Order)">; 221def NotHasStdExtZtso : Predicate<"!Subtarget->hasStdExtZtso()">; 222 223def FeatureStdExtZa64rs : RISCVExtension<"za64rs", 1, 0, 224 "'Za64rs' (Reservation Set Size of at Most 64 Bytes)">; 225 226def FeatureStdExtZa128rs : RISCVExtension<"za128rs", 1, 0, 227 "'Za128rs' (Reservation Set Size of at Most 128 Bytes)">; 228 229def FeatureStdExtZaamo 230 : RISCVExtension<"zaamo", 1, 0, 231 "'Zaamo' (Atomic Memory Operations)">; 232def HasStdExtAOrZaamo 233 : Predicate<"Subtarget->hasStdExtA() || Subtarget->hasStdExtZaamo()">, 234 AssemblerPredicate<(any_of FeatureStdExtA, FeatureStdExtZaamo), 235 "'A' (Atomic Instructions) or " 236 "'Zaamo' (Atomic Memory Operations)">; 237 238def FeatureStdExtZabha 239 : RISCVExtension<"zabha", 1, 0, 240 "'Zabha' (Byte and Halfword Atomic Memory Operations)">; 241def HasStdExtZabha : Predicate<"Subtarget->hasStdExtZabha()">, 242 AssemblerPredicate<(all_of FeatureStdExtZabha), 243 "'Zabha' (Byte and Halfword Atomic Memory Operations)">; 244 245def FeatureStdExtZacas 246 : RISCVExperimentalExtension<"zacas", 1, 0, 247 "'Zacas' (Atomic Compare-And-Swap Instructions)">, 248 RISCVExtensionBitmask<0, 26>; 249def HasStdExtZacas : Predicate<"Subtarget->hasStdExtZacas()">, 250 AssemblerPredicate<(all_of FeatureStdExtZacas), 251 "'Zacas' (Atomic Compare-And-Swap Instructions)">; 252def NoStdExtZacas : Predicate<"!Subtarget->hasStdExtZacas()">; 253 254def FeatureStdExtZalasr 255 : RISCVExperimentalExtension<"zalasr", 0, 1, 256 "'Zalasr' (Load-Acquire and Store-Release Instructions)">; 257def HasStdExtZalasr : Predicate<"Subtarget->hasStdExtZalasr()">, 258 AssemblerPredicate<(all_of FeatureStdExtZalasr), 259 "'Zalasr' (Load-Acquire and Store-Release Instructions)">; 260 261def FeatureStdExtZalrsc 262 : RISCVExtension<"zalrsc", 1, 0, 263 "'Zalrsc' (Load-Reserved/Store-Conditional)">; 264def HasStdExtAOrZalrsc 265 : Predicate<"Subtarget->hasStdExtA() || Subtarget->hasStdExtZalrsc()">, 266 AssemblerPredicate<(any_of FeatureStdExtA, FeatureStdExtZalrsc), 267 "'A' (Atomic Instructions) or " 268 "'Zalrsc' (Load-Reserved/Store-Conditional)">; 269 270def FeatureStdExtZama16b 271 : RISCVExtension<"zama16b", 1, 0, 272 "'Zama16b' (Atomic 16-byte misaligned loads, stores and AMOs)">; 273 274def FeatureStdExtZawrs : RISCVExtension<"zawrs", 1, 0, 275 "'Zawrs' (Wait on Reservation Set)">; 276def HasStdExtZawrs : Predicate<"Subtarget->hasStdExtZawrs()">, 277 AssemblerPredicate<(all_of FeatureStdExtZawrs), 278 "'Zawrs' (Wait on Reservation Set)">; 279 280// Floating Point Extensions 281 282def FeatureStdExtF 283 : RISCVExtension<"f", 2, 2, 284 "'F' (Single-Precision Floating-Point)", 285 [FeatureStdExtZicsr]>, 286 RISCVExtensionBitmask<0, 5>; 287def HasStdExtF : Predicate<"Subtarget->hasStdExtF()">, 288 AssemblerPredicate<(all_of FeatureStdExtF), 289 "'F' (Single-Precision Floating-Point)">; 290 291def FeatureStdExtD 292 : RISCVExtension<"d", 2, 2, 293 "'D' (Double-Precision Floating-Point)", 294 [FeatureStdExtF]>, 295 RISCVExtensionBitmask<0, 3>; 296def HasStdExtD : Predicate<"Subtarget->hasStdExtD()">, 297 AssemblerPredicate<(all_of FeatureStdExtD), 298 "'D' (Double-Precision Floating-Point)">; 299 300def FeatureStdExtZfhmin 301 : RISCVExtension<"zfhmin", 1, 0, 302 "'Zfhmin' (Half-Precision Floating-Point Minimal)", 303 [FeatureStdExtF]>, 304 RISCVExtensionBitmask<0, 36>; 305def HasStdExtZfhmin : Predicate<"Subtarget->hasStdExtZfhmin()">, 306 AssemblerPredicate<(all_of FeatureStdExtZfhmin), 307 "'Zfh' (Half-Precision Floating-Point) or " 308 "'Zfhmin' (Half-Precision Floating-Point Minimal)">; 309 310def FeatureStdExtZfh 311 : RISCVExtension<"zfh", 1, 0, 312 "'Zfh' (Half-Precision Floating-Point)", 313 [FeatureStdExtZfhmin]>, 314 RISCVExtensionBitmask<0, 35>; 315def HasStdExtZfh : Predicate<"Subtarget->hasStdExtZfh()">, 316 AssemblerPredicate<(all_of FeatureStdExtZfh), 317 "'Zfh' (Half-Precision Floating-Point)">; 318def NoStdExtZfh : Predicate<"!Subtarget->hasStdExtZfh()">; 319 320def FeatureStdExtZfbfmin 321 : RISCVExtension<"zfbfmin", 1, 0, "'Zfbfmin' (Scalar BF16 Converts)", 322 [FeatureStdExtF]>; 323def HasStdExtZfbfmin : Predicate<"Subtarget->hasStdExtZfbfmin()">, 324 AssemblerPredicate<(all_of FeatureStdExtZfbfmin), 325 "'Zfbfmin' (Scalar BF16 Converts)">; 326 327def HasHalfFPLoadStoreMove 328 : Predicate<"Subtarget->hasHalfFPLoadStoreMove()">, 329 AssemblerPredicate<(any_of FeatureStdExtZfh, FeatureStdExtZfhmin, 330 FeatureStdExtZfbfmin), 331 "'Zfh' (Half-Precision Floating-Point) or " 332 "'Zfhmin' (Half-Precision Floating-Point Minimal) or " 333 "'Zfbfmin' (Scalar BF16 Converts)">; 334 335def FeatureStdExtZfa 336 : RISCVExtension<"zfa", 1, 0, 337 "'Zfa' (Additional Floating-Point)", 338 [FeatureStdExtF]>, 339 RISCVExtensionBitmask<0, 34>; 340def HasStdExtZfa : Predicate<"Subtarget->hasStdExtZfa()">, 341 AssemblerPredicate<(all_of FeatureStdExtZfa), 342 "'Zfa' (Additional Floating-Point)">; 343 344def FeatureStdExtZfinx 345 : RISCVExtension<"zfinx", 1, 0, 346 "'Zfinx' (Float in Integer)", 347 [FeatureStdExtZicsr]>; 348def HasStdExtZfinx : Predicate<"Subtarget->hasStdExtZfinx()">, 349 AssemblerPredicate<(all_of FeatureStdExtZfinx), 350 "'Zfinx' (Float in Integer)">; 351 352def FeatureStdExtZdinx 353 : RISCVExtension<"zdinx", 1, 0, 354 "'Zdinx' (Double in Integer)", 355 [FeatureStdExtZfinx]>; 356def HasStdExtZdinx : Predicate<"Subtarget->hasStdExtZdinx()">, 357 AssemblerPredicate<(all_of FeatureStdExtZdinx), 358 "'Zdinx' (Double in Integer)">; 359 360def FeatureStdExtZhinxmin 361 : RISCVExtension<"zhinxmin", 1, 0, 362 "'Zhinxmin' (Half Float in Integer Minimal)", 363 [FeatureStdExtZfinx]>; 364def HasStdExtZhinxmin : Predicate<"Subtarget->hasStdExtZhinxmin()">, 365 AssemblerPredicate<(all_of FeatureStdExtZhinxmin), 366 "'Zhinx' (Half Float in Integer) or " 367 "'Zhinxmin' (Half Float in Integer Minimal)">; 368 369def FeatureStdExtZhinx 370 : RISCVExtension<"zhinx", 1, 0, 371 "'Zhinx' (Half Float in Integer)", 372 [FeatureStdExtZhinxmin]>; 373def HasStdExtZhinx : Predicate<"Subtarget->hasStdExtZhinx()">, 374 AssemblerPredicate<(all_of FeatureStdExtZhinx), 375 "'Zhinx' (Half Float in Integer)">; 376def NoStdExtZhinx : Predicate<"!Subtarget->hasStdExtZhinx()">; 377 378// Compressed Extensions 379 380def FeatureStdExtC 381 : RISCVExtension<"c", 2, 0, 382 "'C' (Compressed Instructions)">, 383 RISCVExtensionBitmask<0, 2>; 384def HasStdExtC : Predicate<"Subtarget->hasStdExtC()">, 385 AssemblerPredicate<(all_of FeatureStdExtC), 386 "'C' (Compressed Instructions)">; 387 388def FeatureNoRVCHints 389 : SubtargetFeature<"no-rvc-hints", "EnableRVCHintInstrs", "false", 390 "Disable RVC Hint Instructions.">; 391def HasRVCHints : Predicate<"Subtarget->enableRVCHintInstrs()">, 392 AssemblerPredicate<(all_of(not FeatureNoRVCHints)), 393 "RVC Hint Instructions">; 394 395def FeatureStdExtZca 396 : RISCVExtension<"zca", 1, 0, 397 "'Zca' (part of the C extension, excluding compressed " 398 "floating point loads/stores)">; 399 400def HasStdExtCOrZca 401 : Predicate<"Subtarget->hasStdExtCOrZca()">, 402 AssemblerPredicate<(any_of FeatureStdExtC, FeatureStdExtZca), 403 "'C' (Compressed Instructions) or " 404 "'Zca' (part of the C extension, excluding " 405 "compressed floating point loads/stores)">; 406 407def FeatureStdExtZcb 408 : RISCVExtension<"zcb", 1, 0, 409 "'Zcb' (Compressed basic bit manipulation instructions)", 410 [FeatureStdExtZca]>; 411def HasStdExtZcb : Predicate<"Subtarget->hasStdExtZcb()">, 412 AssemblerPredicate<(all_of FeatureStdExtZcb), 413 "'Zcb' (Compressed basic bit manipulation instructions)">; 414 415def FeatureStdExtZcd 416 : RISCVExtension<"zcd", 1, 0, 417 "'Zcd' (Compressed Double-Precision Floating-Point Instructions)", 418 [FeatureStdExtD, FeatureStdExtZca]>; 419 420def HasStdExtCOrZcd 421 : Predicate<"Subtarget->hasStdExtCOrZcd()">, 422 AssemblerPredicate<(any_of FeatureStdExtC, FeatureStdExtZcd), 423 "'C' (Compressed Instructions) or " 424 "'Zcd' (Compressed Double-Precision Floating-Point Instructions)">; 425 426def FeatureStdExtZcf 427 : RISCVExtension<"zcf", 1, 0, 428 "'Zcf' (Compressed Single-Precision Floating-Point Instructions)", 429 [FeatureStdExtF, FeatureStdExtZca]>; 430 431def FeatureStdExtZcmp 432 : RISCVExtension<"zcmp", 1, 0, 433 "'Zcmp' (sequenced instructions for code-size reduction)", 434 [FeatureStdExtZca]>; 435def HasStdExtZcmp : Predicate<"Subtarget->hasStdExtZcmp() && !Subtarget->hasStdExtC()">, 436 AssemblerPredicate<(all_of FeatureStdExtZcmp), 437 "'Zcmp' (sequenced instructions for code-size reduction)">; 438 439def FeatureStdExtZcmt 440 : RISCVExtension<"zcmt", 1, 0, 441 "'Zcmt' (table jump instructions for code-size reduction)", 442 [FeatureStdExtZca, FeatureStdExtZicsr]>; 443def HasStdExtZcmt : Predicate<"Subtarget->hasStdExtZcmt()">, 444 AssemblerPredicate<(all_of FeatureStdExtZcmt), 445 "'Zcmt' (table jump instructions for code-size reduction)">; 446 447def FeatureStdExtZce 448 : RISCVExtension<"zce", 1, 0, 449 "'Zce' (Compressed extensions for microcontrollers)", 450 [FeatureStdExtZcb, FeatureStdExtZcmp, FeatureStdExtZcmt]>; 451 452def HasStdExtCOrZcfOrZce 453 : Predicate<"Subtarget->hasStdExtC() || Subtarget->hasStdExtZcf() " 454 "Subtarget->hasStdExtZce()">, 455 AssemblerPredicate<(any_of FeatureStdExtC, FeatureStdExtZcf, 456 FeatureStdExtZce), 457 "'C' (Compressed Instructions) or " 458 "'Zcf' (Compressed Single-Precision Floating-Point Instructions)">; 459 460def FeatureStdExtZcmop 461 : RISCVExtension<"zcmop", 1, 0, 462 "'Zcmop' (Compressed May-Be-Operations)", 463 [FeatureStdExtZca]>; 464def HasStdExtZcmop : Predicate<"Subtarget->hasStdExtZcmop()">, 465 AssemblerPredicate<(all_of FeatureStdExtZcmop), 466 "'Zcmop' (Compressed May-Be-Operations)">; 467 468// Bitmanip Extensions 469 470def FeatureStdExtZba 471 : RISCVExtension<"zba", 1, 0, 472 "'Zba' (Address Generation Instructions)">, 473 RISCVExtensionBitmask<0, 27>; 474def HasStdExtZba : Predicate<"Subtarget->hasStdExtZba()">, 475 AssemblerPredicate<(all_of FeatureStdExtZba), 476 "'Zba' (Address Generation Instructions)">; 477def NotHasStdExtZba : Predicate<"!Subtarget->hasStdExtZba()">; 478 479def FeatureStdExtZbb 480 : RISCVExtension<"zbb", 1, 0, 481 "'Zbb' (Basic Bit-Manipulation)">, 482 RISCVExtensionBitmask<0, 28>; 483def HasStdExtZbb : Predicate<"Subtarget->hasStdExtZbb()">, 484 AssemblerPredicate<(all_of FeatureStdExtZbb), 485 "'Zbb' (Basic Bit-Manipulation)">; 486def NoStdExtZbb : Predicate<"!Subtarget->hasStdExtZbb()">, 487 AssemblerPredicate<(all_of (not FeatureStdExtZbb))>; 488 489def FeatureStdExtZbc 490 : RISCVExtension<"zbc", 1, 0, 491 "'Zbc' (Carry-Less Multiplication)">, 492 RISCVExtensionBitmask<0, 29>; 493def HasStdExtZbc : Predicate<"Subtarget->hasStdExtZbc()">, 494 AssemblerPredicate<(all_of FeatureStdExtZbc), 495 "'Zbc' (Carry-Less Multiplication)">; 496 497def FeatureStdExtZbs 498 : RISCVExtension<"zbs", 1, 0, 499 "'Zbs' (Single-Bit Instructions)">, 500 RISCVExtensionBitmask<0, 33>; 501def HasStdExtZbs : Predicate<"Subtarget->hasStdExtZbs()">, 502 AssemblerPredicate<(all_of FeatureStdExtZbs), 503 "'Zbs' (Single-Bit Instructions)">; 504 505// Bitmanip Extensions for Cryptography Extensions 506 507def FeatureStdExtB 508 : RISCVExtension<"b", 1, 0, 509 "'B' (the collection of the Zba, Zbb, Zbs extensions)", 510 [FeatureStdExtZba, FeatureStdExtZbb, FeatureStdExtZbs]>; 511def HasStdExtB : Predicate<"Subtarget->hasStdExtB()">, 512 AssemblerPredicate<(all_of FeatureStdExtB), 513 "'B' (the collection of the Zba, Zbb, Zbs extensions)">; 514 515def FeatureStdExtZbkb 516 : RISCVExtension<"zbkb", 1, 0, 517 "'Zbkb' (Bitmanip instructions for Cryptography)">, 518 RISCVExtensionBitmask<0, 30>; 519def HasStdExtZbkb : Predicate<"Subtarget->hasStdExtZbkb()">, 520 AssemblerPredicate<(all_of FeatureStdExtZbkb), 521 "'Zbkb' (Bitmanip instructions for Cryptography)">; 522 523def FeatureStdExtZbkx 524 : RISCVExtension<"zbkx", 1, 0, 525 "'Zbkx' (Crossbar permutation instructions)">, 526 RISCVExtensionBitmask<0, 32>; 527def HasStdExtZbkx : Predicate<"Subtarget->hasStdExtZbkx()">, 528 AssemblerPredicate<(all_of FeatureStdExtZbkx), 529 "'Zbkx' (Crossbar permutation instructions)">; 530 531def HasStdExtZbbOrZbkb 532 : Predicate<"Subtarget->hasStdExtZbb() || Subtarget->hasStdExtZbkb()">, 533 AssemblerPredicate<(any_of FeatureStdExtZbb, FeatureStdExtZbkb), 534 "'Zbb' (Basic Bit-Manipulation) or " 535 "'Zbkb' (Bitmanip instructions for Cryptography)">; 536 537// The Carry-less multiply subextension for cryptography is a subset of basic 538// carry-less multiply subextension. The former should be enabled if the latter 539// is enabled. 540def FeatureStdExtZbkc 541 : RISCVExtension<"zbkc", 1, 0, 542 "'Zbkc' (Carry-less multiply instructions for " 543 "Cryptography)">, 544 RISCVExtensionBitmask<0, 31>; 545def HasStdExtZbkc 546 : Predicate<"Subtarget->hasStdExtZbkc()">, 547 AssemblerPredicate<(all_of FeatureStdExtZbkc), 548 "'Zbkc' (Carry-less multiply instructions for Cryptography)">; 549 550def HasStdExtZbcOrZbkc 551 : Predicate<"Subtarget->hasStdExtZbc() || Subtarget->hasStdExtZbkc()">, 552 AssemblerPredicate<(any_of FeatureStdExtZbc, FeatureStdExtZbkc), 553 "'Zbc' (Carry-Less Multiplication) or " 554 "'Zbkc' (Carry-less multiply instructions " 555 "for Cryptography)">; 556 557// Cryptography Extensions 558 559def FeatureStdExtZknd 560 : RISCVExtension<"zknd", 1, 0, 561 "'Zknd' (NIST Suite: AES Decryption)">, 562 RISCVExtensionBitmask<0, 41>; 563def HasStdExtZknd : Predicate<"Subtarget->hasStdExtZknd()">, 564 AssemblerPredicate<(all_of FeatureStdExtZknd), 565 "'Zknd' (NIST Suite: AES Decryption)">; 566 567def FeatureStdExtZkne 568 : RISCVExtension<"zkne", 1, 0, 569 "'Zkne' (NIST Suite: AES Encryption)">, 570 RISCVExtensionBitmask<0, 42>; 571def HasStdExtZkne : Predicate<"Subtarget->hasStdExtZkne()">, 572 AssemblerPredicate<(all_of FeatureStdExtZkne), 573 "'Zkne' (NIST Suite: AES Encryption)">; 574 575// Some instructions belong to both Zknd and Zkne subextensions. 576// They should be enabled if either has been specified. 577def HasStdExtZkndOrZkne 578 : Predicate<"Subtarget->hasStdExtZknd() || Subtarget->hasStdExtZkne()">, 579 AssemblerPredicate<(any_of FeatureStdExtZknd, FeatureStdExtZkne), 580 "'Zknd' (NIST Suite: AES Decryption) or " 581 "'Zkne' (NIST Suite: AES Encryption)">; 582 583def FeatureStdExtZknh 584 : RISCVExtension<"zknh", 1, 0, 585 "'Zknh' (NIST Suite: Hash Function Instructions)">, 586 RISCVExtensionBitmask<0, 43>; 587def HasStdExtZknh : Predicate<"Subtarget->hasStdExtZknh()">, 588 AssemblerPredicate<(all_of FeatureStdExtZknh), 589 "'Zknh' (NIST Suite: Hash Function Instructions)">; 590 591def FeatureStdExtZksed 592 : RISCVExtension<"zksed", 1, 0, 593 "'Zksed' (ShangMi Suite: SM4 Block Cipher Instructions)">, 594 RISCVExtensionBitmask<0, 44>; 595def HasStdExtZksed : Predicate<"Subtarget->hasStdExtZksed()">, 596 AssemblerPredicate<(all_of FeatureStdExtZksed), 597 "'Zksed' (ShangMi Suite: SM4 Block Cipher Instructions)">; 598 599def FeatureStdExtZksh 600 : RISCVExtension<"zksh", 1, 0, 601 "'Zksh' (ShangMi Suite: SM3 Hash Function Instructions)">, 602 RISCVExtensionBitmask<0, 45>; 603def HasStdExtZksh : Predicate<"Subtarget->hasStdExtZksh()">, 604 AssemblerPredicate<(all_of FeatureStdExtZksh), 605 "'Zksh' (ShangMi Suite: SM3 Hash Function Instructions)">; 606 607def FeatureStdExtZkr 608 : RISCVExtension<"zkr", 1, 0, 609 "'Zkr' (Entropy Source Extension)">; 610def HasStdExtZkr : Predicate<"Subtarget->hasStdExtZkr()">, 611 AssemblerPredicate<(all_of FeatureStdExtZkr), 612 "'Zkr' (Entropy Source Extension)">; 613 614def FeatureStdExtZkn 615 : RISCVExtension<"zkn", 1, 0, 616 "'Zkn' (NIST Algorithm Suite)", 617 [FeatureStdExtZbkb, 618 FeatureStdExtZbkc, 619 FeatureStdExtZbkx, 620 FeatureStdExtZkne, 621 FeatureStdExtZknd, 622 FeatureStdExtZknh]>; 623 624def FeatureStdExtZks 625 : RISCVExtension<"zks", 1, 0, 626 "'Zks' (ShangMi Algorithm Suite)", 627 [FeatureStdExtZbkb, 628 FeatureStdExtZbkc, 629 FeatureStdExtZbkx, 630 FeatureStdExtZksed, 631 FeatureStdExtZksh]>; 632 633def FeatureStdExtZkt 634 : RISCVExtension<"zkt", 1, 0, 635 "'Zkt' (Data Independent Execution Latency)">, 636 RISCVExtensionBitmask<0, 46>; 637 638def FeatureStdExtZk 639 : RISCVExtension<"zk", 1, 0, 640 "'Zk' (Standard scalar cryptography extension)", 641 [FeatureStdExtZkn, 642 FeatureStdExtZkr, 643 FeatureStdExtZkt]>; 644 645// Vector Extensions 646 647def FeatureStdExtZvl32b : RISCVExtension<"zvl32b", 1, 0, 648 "'Zvl' (Minimum Vector Length) 32", [], 649 "ZvlLen", "32">; 650 651foreach i = { 6-16 } in { 652 defvar I = !shl(1, i); 653 def FeatureStdExtZvl#I#b : 654 RISCVExtension<"zvl"#I#"b", 1, 0, 655 "'Zvl' (Minimum Vector Length) "#I, 656 [!cast<RISCVExtension>("FeatureStdExtZvl"#!srl(I, 1)#"b")], 657 "ZvlLen", !cast<string>(I)>; 658} 659 660def FeatureStdExtZve32x 661 : RISCVExtension<"zve32x", 1, 0, 662 "'Zve32x' (Vector Extensions for Embedded Processors " 663 "with maximal 32 EEW)", 664 [FeatureStdExtZicsr, FeatureStdExtZvl32b]>; 665 666 667def FeatureStdExtZve32f 668 : RISCVExtension<"zve32f", 1, 0, 669 "'Zve32f' (Vector Extensions for Embedded Processors " 670 "with maximal 32 EEW and F extension)", 671 [FeatureStdExtZve32x, FeatureStdExtF]>; 672 673def FeatureStdExtZve64x 674 : RISCVExtension<"zve64x", 1, 0, 675 "'Zve64x' (Vector Extensions for Embedded Processors " 676 "with maximal 64 EEW)", 677 [FeatureStdExtZve32x, FeatureStdExtZvl64b]>; 678 679def FeatureStdExtZve64f 680 : RISCVExtension<"zve64f", 1, 0, 681 "'Zve64f' (Vector Extensions for Embedded Processors " 682 "with maximal 64 EEW and F extension)", 683 [FeatureStdExtZve32f, FeatureStdExtZve64x]>; 684 685def FeatureStdExtZve64d 686 : RISCVExtension<"zve64d", 1, 0, 687 "'Zve64d' (Vector Extensions for Embedded Processors " 688 "with maximal 64 EEW, F and D extension)", 689 [FeatureStdExtZve64f, FeatureStdExtD]>; 690 691def FeatureStdExtV 692 : RISCVExtension<"v", 1, 0, 693 "'V' (Vector Extension for Application Processors)", 694 [FeatureStdExtZvl128b, FeatureStdExtZve64d]>, 695 RISCVExtensionBitmask<0, 21>; 696 697def FeatureStdExtZvfbfmin 698 : RISCVExtension<"zvfbfmin", 1, 0, "'Zvbfmin' (Vector BF16 Converts)", 699 [FeatureStdExtZve32f]>; 700def HasStdExtZvfbfmin : Predicate<"Subtarget->hasStdExtZvfbfmin()">, 701 AssemblerPredicate<(all_of FeatureStdExtZvfbfmin), 702 "'Zvfbfmin' (Vector BF16 Converts)">; 703 704def FeatureStdExtZvfbfwma 705 : RISCVExtension<"zvfbfwma", 1, 0, 706 "'Zvfbfwma' (Vector BF16 widening mul-add)", 707 [FeatureStdExtZvfbfmin, FeatureStdExtZfbfmin]>; 708def HasStdExtZvfbfwma : Predicate<"Subtarget->hasStdExtZvfbfwma()">, 709 AssemblerPredicate<(all_of FeatureStdExtZvfbfwma), 710 "'Zvfbfwma' (Vector BF16 widening mul-add)">; 711 712def FeatureStdExtZvfhmin 713 : RISCVExtension<"zvfhmin", 1, 0, 714 "'Zvfhmin' (Vector Half-Precision Floating-Point Minimal)", 715 [FeatureStdExtZve32f]>, 716 RISCVExtensionBitmask<0, 51>; 717 718def FeatureStdExtZvfh 719 : RISCVExtension<"zvfh", 1, 0, 720 "'Zvfh' (Vector Half-Precision Floating-Point)", 721 [FeatureStdExtZvfhmin, FeatureStdExtZfhmin]>, 722 RISCVExtensionBitmask<0, 50>; 723 724def HasStdExtZfhOrZvfh 725 : Predicate<"Subtarget->hasStdExtZfh() || Subtarget->hasStdExtZvfh()">, 726 AssemblerPredicate<(any_of FeatureStdExtZfh, FeatureStdExtZvfh), 727 "'Zfh' (Half-Precision Floating-Point) or " 728 "'Zvfh' (Vector Half-Precision Floating-Point)">; 729 730// Vector Cryptography and Bitmanip Extensions 731 732def FeatureStdExtZvkb 733 : RISCVExtension<"zvkb", 1, 0, 734 "'Zvkb' (Vector Bit-manipulation used in Cryptography)">, 735 RISCVExtensionBitmask<0, 52>; 736def HasStdExtZvkb : Predicate<"Subtarget->hasStdExtZvkb()">, 737 AssemblerPredicate<(all_of FeatureStdExtZvkb), 738 "'Zvkb' (Vector Bit-manipulation used in Cryptography)">; 739 740def FeatureStdExtZvbb 741 : RISCVExtension<"zvbb", 1, 0, 742 "'Zvbb' (Vector basic bit-manipulation instructions)", 743 [FeatureStdExtZvkb]>, 744 RISCVExtensionBitmask<0, 48>; 745def HasStdExtZvbb : Predicate<"Subtarget->hasStdExtZvbb()">, 746 AssemblerPredicate<(all_of FeatureStdExtZvbb), 747 "'Zvbb' (Vector basic bit-manipulation instructions)">; 748 749def FeatureStdExtZvbc 750 : RISCVExtension<"zvbc", 1, 0, 751 "'Zvbc' (Vector Carryless Multiplication)">, 752 RISCVExtensionBitmask<0, 49>; 753def HasStdExtZvbc : Predicate<"Subtarget->hasStdExtZvbc()">, 754 AssemblerPredicate<(all_of FeatureStdExtZvbc), 755 "'Zvbc' (Vector Carryless Multiplication)">; 756 757def FeatureStdExtZvkg 758 : RISCVExtension<"zvkg", 1, 0, 759 "'Zvkg' (Vector GCM instructions for Cryptography)">, 760 RISCVExtensionBitmask<0, 53>; 761def HasStdExtZvkg : Predicate<"Subtarget->hasStdExtZvkg()">, 762 AssemblerPredicate<(all_of FeatureStdExtZvkg), 763 "'Zvkg' (Vector GCM instructions for Cryptography)">; 764 765def FeatureStdExtZvkned 766 : RISCVExtension<"zvkned", 1, 0, 767 "'Zvkned' (Vector AES Encryption & Decryption (Single Round))">, 768 RISCVExtensionBitmask<0, 54>; 769def HasStdExtZvkned : Predicate<"Subtarget->hasStdExtZvkned()">, 770 AssemblerPredicate<(all_of FeatureStdExtZvkned), 771 "'Zvkned' (Vector AES Encryption & Decryption (Single Round))">; 772 773def FeatureStdExtZvknha 774 : RISCVExtension<"zvknha", 1, 0, 775 "'Zvknha' (Vector SHA-2 (SHA-256 only))">, 776 RISCVExtensionBitmask<0, 55>; 777def HasStdExtZvknha : Predicate<"Subtarget->hasStdExtZvknha()">, 778 AssemblerPredicate<(all_of FeatureStdExtZvknha), 779 "'Zvknha' (Vector SHA-2 (SHA-256 only))">; 780 781def FeatureStdExtZvknhb 782 : RISCVExtension<"zvknhb", 1, 0, 783 "'Zvknhb' (Vector SHA-2 (SHA-256 and SHA-512))", 784 [FeatureStdExtZve64x]>, 785 RISCVExtensionBitmask<0, 56>; 786def HasStdExtZvknhb : Predicate<"Subtarget->hasStdExtZvknhb()">, 787 AssemblerPredicate<(all_of FeatureStdExtZvknhb), 788 "'Zvknhb' (Vector SHA-2 (SHA-256 and SHA-512))">; 789 790def HasStdExtZvknhaOrZvknhb : Predicate<"Subtarget->hasStdExtZvknha() || Subtarget->hasStdExtZvknhb()">, 791 AssemblerPredicate<(any_of FeatureStdExtZvknha, FeatureStdExtZvknhb), 792 "'Zvknha' or 'Zvknhb' (Vector SHA-2)">; 793 794def FeatureStdExtZvksed 795 : RISCVExtension<"zvksed", 1, 0, 796 "'Zvksed' (SM4 Block Cipher Instructions)">, 797 RISCVExtensionBitmask<0, 57>; 798def HasStdExtZvksed : Predicate<"Subtarget->hasStdExtZvksed()">, 799 AssemblerPredicate<(all_of FeatureStdExtZvksed), 800 "'Zvksed' (SM4 Block Cipher Instructions)">; 801 802def FeatureStdExtZvksh 803 : RISCVExtension<"zvksh", 1, 0, 804 "'Zvksh' (SM3 Hash Function Instructions)">, 805 RISCVExtensionBitmask<0, 58>; 806def HasStdExtZvksh : Predicate<"Subtarget->hasStdExtZvksh()">, 807 AssemblerPredicate<(all_of FeatureStdExtZvksh), 808 "'Zvksh' (SM3 Hash Function Instructions)">; 809 810def FeatureStdExtZvkt 811 : RISCVExtension<"zvkt", 1, 0, 812 "'Zvkt' (Vector Data-Independent Execution Latency)">, 813 RISCVExtensionBitmask<0, 59>; 814 815// Zvk short-hand extensions 816 817def FeatureStdExtZvkn 818 : RISCVExtension<"zvkn", 1, 0, 819 "'Zvkn' (shorthand for 'Zvkned', 'Zvknhb', 'Zvkb', and " 820 "'Zvkt')", 821 [FeatureStdExtZvkned, FeatureStdExtZvknhb, 822 FeatureStdExtZvkb, FeatureStdExtZvkt]>; 823 824def FeatureStdExtZvknc 825 : RISCVExtension<"zvknc", 1, 0, 826 "'Zvknc' (shorthand for 'Zvknc' and 'Zvbc')", 827 [FeatureStdExtZvkn, FeatureStdExtZvbc]>; 828 829def FeatureStdExtZvkng 830 : RISCVExtension<"zvkng", 1, 0, 831 "'zvkng' (shorthand for 'Zvkn' and 'Zvkg')", 832 [FeatureStdExtZvkn, FeatureStdExtZvkg]>; 833 834def FeatureStdExtZvks 835 : RISCVExtension<"zvks", 1, 0, 836 "'Zvks' (shorthand for 'Zvksed', 'Zvksh', 'Zvkb', and " 837 "'Zvkt')", 838 [FeatureStdExtZvksed, FeatureStdExtZvksh, 839 FeatureStdExtZvkb, FeatureStdExtZvkt]>; 840 841def FeatureStdExtZvksc 842 : RISCVExtension<"zvksc", 1, 0, 843 "'Zvksc' (shorthand for 'Zvks' and 'Zvbc')", 844 [FeatureStdExtZvks, FeatureStdExtZvbc]>; 845 846def FeatureStdExtZvksg 847 : RISCVExtension<"zvksg", 1, 0, 848 "'Zvksg' (shorthand for 'Zvks' and 'Zvkg')", 849 [FeatureStdExtZvks, FeatureStdExtZvkg]>; 850// Vector instruction predicates 851 852def HasVInstructions : Predicate<"Subtarget->hasVInstructions()">, 853 AssemblerPredicate< 854 (any_of FeatureStdExtZve32x), 855 "'V' (Vector Extension for Application Processors), 'Zve32x' " 856 "(Vector Extensions for Embedded Processors)">; 857def HasVInstructionsI64 : Predicate<"Subtarget->hasVInstructionsI64()">, 858 AssemblerPredicate< 859 (any_of FeatureStdExtZve64x), 860 "'V' (Vector Extension for Application Processors) or 'Zve64x' " 861 "(Vector Extensions for Embedded Processors)">; 862def HasVInstructionsAnyF : Predicate<"Subtarget->hasVInstructionsAnyF()">, 863 AssemblerPredicate< 864 (any_of FeatureStdExtZve32f), 865 "'V' (Vector Extension for Application Processors), 'Zve32f' " 866 "(Vector Extensions for Embedded Processors)">; 867 868def HasVInstructionsF16Minimal : Predicate<"Subtarget->hasVInstructionsF16Minimal()">, 869 AssemblerPredicate<(any_of FeatureStdExtZvfhmin, FeatureStdExtZvfh), 870 "'Zvfhmin' (Vector Half-Precision Floating-Point Minimal) or " 871 "'Zvfh' (Vector Half-Precision Floating-Point)">; 872 873def HasVInstructionsBF16 : Predicate<"Subtarget->hasVInstructionsBF16()">; 874def HasVInstructionsF16 : Predicate<"Subtarget->hasVInstructionsF16()">; 875def HasVInstructionsF64 : Predicate<"Subtarget->hasVInstructionsF64()">; 876 877def HasVInstructionsFullMultiply : Predicate<"Subtarget->hasVInstructionsFullMultiply()">; 878 879// Hypervisor Extensions 880 881def FeatureStdExtH 882 : RISCVExtension<"h", 1, 0, 883 "'H' (Hypervisor)">; 884 885def HasStdExtH : Predicate<"Subtarget->hasStdExtH()">, 886 AssemblerPredicate<(all_of FeatureStdExtH), 887 "'H' (Hypervisor)">; 888 889// Supervisor extensions 890 891def FeatureStdExtShgatpa 892 : RISCVExtension<"shgatpa", 1, 0, 893 "'Sgatpa' (SvNNx4 mode supported for all modes supported by satp, as well as Bare)">; 894def FeatureStdExtShvsatpa 895 : RISCVExtension<"shvsatpa", 1, 0, 896 "'Svsatpa' (vsatp supports all modes supported by satp)">; 897 898def FeatureStdExtSmaia 899 : RISCVExtension<"smaia", 1, 0, 900 "'Smaia' (Advanced Interrupt Architecture Machine Level)">; 901def FeatureStdExtSsaia 902 : RISCVExtension<"ssaia", 1, 0, 903 "'Ssaia' (Advanced Interrupt Architecture Supervisor " 904 "Level)">; 905 906def FeatureStdExtSmcsrind 907 : RISCVExtension<"smcsrind", 1, 0, 908 "'Smcsrind' (Indirect CSR Access Machine Level)">; 909def FeatureStdExtSscsrind 910 : RISCVExtension<"sscsrind", 1, 0, 911 "'Sscsrind' (Indirect CSR Access Supervisor Level)">; 912 913def FeatureStdExtSmepmp 914 : RISCVExtension<"smepmp", 1, 0, 915 "'Smepmp' (Enhanced Physical Memory Protection)">; 916 917def FeatureStdExtSmcdeleg 918 : RISCVExtension<"smcdeleg", 1, 0, 919 "'Smcdeleg' (Counter Delegation Machine Level)">; 920def FeatureStdExtSsccfg 921 : RISCVExtension<"ssccfg", 1, 0, 922 "'Ssccfg' (Counter Configuration Supervisor Level)">; 923 924def FeatureStdExtSsccptr 925 : RISCVExtension<"ssccptr", 1, 0, 926 "'Ssccptr' (Main memory supports page table reads)">; 927 928def FeatureStdExtSscofpmf 929 : RISCVExtension<"sscofpmf", 1, 0, 930 "'Sscofpmf' (Count Overflow and Mode-Based Filtering)">; 931 932def FeatureStdExtShcounterenw 933 : RISCVExtension<"shcounterenw", 1, 0, 934 "'Shcounterenw' (Support writeable hcounteren enable " 935 "bit for any hpmcounter that is not read-only zero)">; 936def FeatureStdExtSscounterenw 937 : RISCVExtension<"sscounterenw", 1, 0, 938 "'Sscounterenw' (Support writeable scounteren enable " 939 "bit for any hpmcounter that is not read-only zero)">; 940 941def FeatureStdExtSmstateen 942 : RISCVExtension<"smstateen", 1, 0, 943 "'Smstateen' (Machine-mode view of the state-enable extension)">; 944def FeatureStdExtSsstateen 945 : RISCVExtension<"ssstateen", 1, 0, 946 "'Ssstateen' (Supervisor-mode view of the state-enable extension)">; 947 948def FeatureStdExtSsstrict 949 : RISCVExtension<"ssstrict", 1, 0, 950 "'Ssstrict' (No non-conforming extensions are present)">; 951 952def FeatureStdExtSstc 953 : RISCVExtension<"sstc", 1, 0, 954 "'Sstc' (Supervisor-mode timer interrupts)">; 955 956def FeaturesStdExtSsqosid 957 : RISCVExperimentalExtension<"ssqosid", 1, 0, 958 "'Ssqosid' (Quality-of-Service (QoS) Identifiers)">; 959 960def FeatureStdExtShtvala 961 : RISCVExtension<"shtvala", 1, 0, 962 "'Shtvala' (htval provides all needed values)">; 963def FeatureStdExtShvstvala 964 : RISCVExtension<"shvstvala", 1, 0, 965 "'Shvstvala' (vstval provides all needed values)">; 966def FeatureStdExtSstvala 967 : RISCVExtension<"sstvala", 1, 0, 968 "'Sstvala' (stval provides all needed values)">; 969 970def FeatureStdExtShvstvecd 971 : RISCVExtension<"shvstvecd", 1, 0, 972 "'Shvstvecd' (vstvec supports Direct mode)">; 973def FeatureStdExtSstvecd 974 : RISCVExtension<"sstvecd", 1, 0, 975 "'Sstvecd' (stvec supports Direct mode)">; 976 977def FeatureStdExtSsu64xl 978 : RISCVExtension<"ssu64xl", 1, 0, 979 "'Ssu64xl' (UXLEN=64 supported)">; 980 981def FeatureStdExtSvade 982 : RISCVExtension<"svade", 1, 0, 983 "'Svade' (Raise exceptions on improper A/D bits)">; 984 985def FeatureStdExtSvadu 986 : RISCVExtension<"svadu", 1, 0, 987 "'Svadu' (Hardware A/D updates)">; 988 989def FeatureStdExtSvbare 990 : RISCVExtension<"svbare", 1, 0, 991 "'Svbare' $(satp mode Bare supported)">; 992 993def FeatureStdExtSvinval 994 : RISCVExtension<"svinval", 1, 0, 995 "'Svinval' (Fine-Grained Address-Translation Cache Invalidation)">; 996def HasStdExtSvinval : Predicate<"Subtarget->hasStdExtSvinval()">, 997 AssemblerPredicate<(all_of FeatureStdExtSvinval), 998 "'Svinval' (Fine-Grained Address-Translation Cache Invalidation)">; 999 1000def FeatureStdExtSvnapot 1001 : RISCVExtension<"svnapot", 1, 0, 1002 "'Svnapot' (NAPOT Translation Contiguity)">; 1003 1004def FeatureStdExtSvpbmt 1005 : RISCVExtension<"svpbmt", 1, 0, 1006 "'Svpbmt' (Page-Based Memory Types)">; 1007 1008// Pointer Masking extensions 1009 1010// A supervisor-level extension that provides pointer masking for the next lower 1011// privilege mode (U-mode), and for VS- and VU-modes if the H extension is 1012// present. 1013def FeatureStdExtSsnpm 1014 : RISCVExperimentalExtension<"ssnpm", 1, 0, 1015 "'Ssnpm' (Supervisor-level Pointer Masking for next lower privilege mode)">; 1016 1017// A machine-level extension that provides pointer masking for the next lower 1018// privilege mode (S/HS if S-mode is implemented, or U-mode otherwise). 1019def FeatureStdExtSmnpm 1020 : RISCVExperimentalExtension<"smnpm", 1, 0, 1021 "'Smnpm' (Machine-level Pointer Masking for next lower privilege mode)">; 1022 1023// A machine-level extension that provides pointer masking for M-mode. 1024def FeatureStdExtSmmpm 1025 : RISCVExperimentalExtension<"smmpm", 1, 0, 1026 "'Smmpm' (Machine-level Pointer Masking for M-mode)">; 1027 1028// An extension that indicates that there is pointer-masking support available 1029// in supervisor mode, with some facility provided in the supervisor execution 1030// environment to control pointer masking. 1031def FeatureStdExtSspm 1032 : RISCVExperimentalExtension<"sspm", 1, 0, 1033 "'Sspm' (Indicates Supervisor-mode Pointer Masking)">; 1034 1035// An extension that indicates that there is pointer-masking support available 1036// in user mode, with some facility provided in the application execution 1037// environment to control pointer masking. 1038def FeatureStdExtSupm 1039 : RISCVExperimentalExtension<"supm", 1, 0, 1040 "'Supm' (Indicates User-mode Pointer Masking)">; 1041 1042//===----------------------------------------------------------------------===// 1043// Vendor extensions 1044//===----------------------------------------------------------------------===// 1045 1046// Ventana Extenions 1047 1048def FeatureVendorXVentanaCondOps 1049 : RISCVExtension<"xventanacondops", 1, 0, 1050 "'XVentanaCondOps' (Ventana Conditional Ops)">; 1051def HasVendorXVentanaCondOps : Predicate<"Subtarget->hasVendorXVentanaCondOps()">, 1052 AssemblerPredicate<(all_of FeatureVendorXVentanaCondOps), 1053 "'XVentanaCondOps' (Ventana Conditional Ops)">; 1054 1055// T-Head Extensions 1056 1057def FeatureVendorXTHeadBa 1058 : RISCVExtension<"xtheadba", 1, 0, 1059 "'XTHeadBa' (T-Head address calculation instructions)">; 1060def HasVendorXTHeadBa : Predicate<"Subtarget->hasVendorXTHeadBa()">, 1061 AssemblerPredicate<(all_of FeatureVendorXTHeadBa), 1062 "'XTHeadBa' (T-Head address calculation instructions)">; 1063 1064def FeatureVendorXTHeadBb 1065 : RISCVExtension<"xtheadbb", 1, 0, 1066 "'XTHeadBb' (T-Head basic bit-manipulation instructions)">; 1067def HasVendorXTHeadBb : Predicate<"Subtarget->hasVendorXTHeadBb()">, 1068 AssemblerPredicate<(all_of FeatureVendorXTHeadBb), 1069 "'XTHeadBb' (T-Head basic bit-manipulation instructions)">; 1070 1071def FeatureVendorXTHeadBs 1072 : RISCVExtension<"xtheadbs", 1, 0, 1073 "'XTHeadBs' (T-Head single-bit instructions)">; 1074def HasVendorXTHeadBs : Predicate<"Subtarget->hasVendorXTHeadBs()">, 1075 AssemblerPredicate<(all_of FeatureVendorXTHeadBs), 1076 "'XTHeadBs' (T-Head single-bit instructions)">; 1077 1078def FeatureVendorXTHeadCondMov 1079 : RISCVExtension<"xtheadcondmov", 1, 0, 1080 "'XTHeadCondMov' (T-Head conditional move instructions)">; 1081def HasVendorXTHeadCondMov : Predicate<"Subtarget->hasVendorXTHeadCondMov()">, 1082 AssemblerPredicate<(all_of FeatureVendorXTHeadCondMov), 1083 "'XTHeadCondMov' (T-Head conditional move instructions)">; 1084 1085def FeatureVendorXTHeadCmo 1086 : RISCVExtension<"xtheadcmo", 1, 0, 1087 "'XTHeadCmo' (T-Head cache management instructions)">; 1088def HasVendorXTHeadCmo : Predicate<"Subtarget->hasVendorXTHeadCmo()">, 1089 AssemblerPredicate<(all_of FeatureVendorXTHeadCmo), 1090 "'XTHeadCmo' (T-Head cache management instructions)">; 1091 1092def FeatureVendorXTHeadFMemIdx 1093 : RISCVExtension<"xtheadfmemidx", 1, 0, 1094 "'XTHeadFMemIdx' (T-Head FP Indexed Memory Operations)">; 1095def HasVendorXTHeadFMemIdx : Predicate<"Subtarget->hasVendorXTHeadFMemIdx()">, 1096 AssemblerPredicate<(all_of FeatureVendorXTHeadFMemIdx), 1097 "'XTHeadFMemIdx' (T-Head FP Indexed Memory Operations)">; 1098 1099def FeatureVendorXTHeadMac 1100 : RISCVExtension<"xtheadmac", 1, 0, 1101 "'XTHeadMac' (T-Head Multiply-Accumulate Instructions)">; 1102def HasVendorXTHeadMac : Predicate<"Subtarget->hasVendorXTHeadMac()">, 1103 AssemblerPredicate<(all_of FeatureVendorXTHeadMac), 1104 "'XTHeadMac' (T-Head Multiply-Accumulate Instructions)">; 1105 1106def FeatureVendorXTHeadMemIdx 1107 : RISCVExtension<"xtheadmemidx", 1, 0, 1108 "'XTHeadMemIdx' (T-Head Indexed Memory Operations)">; 1109def HasVendorXTHeadMemIdx : Predicate<"Subtarget->hasVendorXTHeadMemIdx()">, 1110 AssemblerPredicate<(all_of FeatureVendorXTHeadMemIdx), 1111 "'XTHeadMemIdx' (T-Head Indexed Memory Operations)">; 1112 1113def FeatureVendorXTHeadMemPair 1114 : RISCVExtension<"xtheadmempair", 1, 0, 1115 "'XTHeadMemPair' (T-Head two-GPR Memory Operations)">; 1116def HasVendorXTHeadMemPair : Predicate<"Subtarget->hasVendorXTHeadMemPair()">, 1117 AssemblerPredicate<(all_of FeatureVendorXTHeadMemPair), 1118 "'XTHeadMemPair' (T-Head two-GPR Memory Operations)">; 1119 1120def FeatureVendorXTHeadSync 1121 : RISCVExtension<"xtheadsync", 1, 0, 1122 "'XTHeadSync' (T-Head multicore synchronization instructions)">; 1123def HasVendorXTHeadSync : Predicate<"Subtarget->hasVendorXTHeadSync()">, 1124 AssemblerPredicate<(all_of FeatureVendorXTHeadSync), 1125 "'XTHeadSync' (T-Head multicore synchronization instructions)">; 1126 1127def FeatureVendorXTHeadVdot 1128 : RISCVExtension<"xtheadvdot", 1, 0, 1129 "'XTHeadVdot' (T-Head Vector Extensions for Dot)", 1130 [FeatureStdExtV]>; 1131def HasVendorXTHeadVdot : Predicate<"Subtarget->hasVendorXTHeadVdot()">, 1132 AssemblerPredicate<(all_of FeatureVendorXTHeadVdot), 1133 "'XTHeadVdot' (T-Head Vector Extensions for Dot)">; 1134 1135// SiFive Extensions 1136 1137def FeatureVendorXSfvcp 1138 : RISCVExtension<"xsfvcp", 1, 0, 1139 "'XSfvcp' (SiFive Custom Vector Coprocessor Interface Instructions)", 1140 [FeatureStdExtZve32x]>; 1141def HasVendorXSfvcp : Predicate<"Subtarget->hasVendorXSfvcp()">, 1142 AssemblerPredicate<(all_of FeatureVendorXSfvcp), 1143 "'XSfvcp' (SiFive Custom Vector Coprocessor Interface Instructions)">; 1144 1145def FeatureVendorXSfvqmaccdod 1146 : RISCVExtension<"xsfvqmaccdod", 1, 0, 1147 "'XSfvqmaccdod' (SiFive Int8 Matrix Multiplication Instructions (2-by-8 and 8-by-2))", 1148 [FeatureStdExtZve32x]>; 1149def HasVendorXSfvqmaccdod 1150 : Predicate<"Subtarget->hasVendorXSfvqmaccdod()">, 1151 AssemblerPredicate<(all_of FeatureVendorXSfvqmaccdod), 1152 "'XSfvqmaccdod' (SiFive Int8 Matrix Multiplication Instructions (2-by-8 and 8-by-2))">; 1153 1154def FeatureVendorXSfvqmaccqoq 1155 : RISCVExtension<"xsfvqmaccqoq", 1, 0, 1156 "'XSfvqmaccqoq' (SiFive Int8 Matrix Multiplication Instructions (4-by-8 and 8-by-4))", 1157 [FeatureStdExtZve32x]>; 1158def HasVendorXSfvqmaccqoq 1159 : Predicate<"Subtarget->hasVendorXSfvqmaccqoq()">, 1160 AssemblerPredicate<(all_of FeatureVendorXSfvqmaccqoq), 1161 "'XSfvqmaccqoq' (SiFive Int8 Matrix Multiplication Instructions (4-by-8 and 8-by-4))">; 1162 1163def FeatureVendorXSfvfwmaccqqq 1164 : RISCVExtension<"xsfvfwmaccqqq", 1, 0, 1165 "'XSfvfwmaccqqq' (SiFive Matrix Multiply Accumulate Instruction and 4-by-4))", 1166 [FeatureStdExtZvfbfmin]>; 1167def HasVendorXSfvfwmaccqqq 1168 : Predicate<"Subtarget->hasVendorXSfvfwmaccqqq()">, 1169 AssemblerPredicate<(all_of FeatureVendorXSfvfwmaccqqq), 1170 "'XSfvfwmaccqqq' (SiFive Matrix Multiply Accumulate Instruction and 4-by-4))">; 1171 1172def FeatureVendorXSfvfnrclipxfqf 1173 : RISCVExtension<"xsfvfnrclipxfqf", 1, 0, 1174 "'XSfvfnrclipxfqf' (SiFive FP32-to-int8 Ranged Clip Instructions)", 1175 [FeatureStdExtZve32f]>; 1176def HasVendorXSfvfnrclipxfqf 1177 : Predicate<"Subtarget->hasVendorXSfvfnrclipxfqf()">, 1178 AssemblerPredicate<(all_of FeatureVendorXSfvfnrclipxfqf), 1179 "'XSfvfnrclipxfqf' (SiFive FP32-to-int8 Ranged Clip Instructions)">; 1180 1181def FeatureVendorXSiFivecdiscarddlone 1182 : RISCVExtension<"xsifivecdiscarddlone", 1, 0, 1183 "'XSiFivecdiscarddlone' (SiFive sf.cdiscard.d.l1 Instruction)", []>; 1184def HasVendorXSiFivecdiscarddlone 1185 : Predicate<"Subtarget->hasVendorXSiFivecdiscarddlone()">, 1186 AssemblerPredicate<(all_of FeatureVendorXSiFivecdiscarddlone), 1187 "'XSiFivecdiscarddlone' (SiFive sf.cdiscard.d.l1 Instruction)">; 1188 1189def FeatureVendorXSiFivecflushdlone 1190 : RISCVExtension<"xsifivecflushdlone", 1, 0, 1191 "'XSiFivecflushdlone' (SiFive sf.cflush.d.l1 Instruction)", []>; 1192def HasVendorXSiFivecflushdlone 1193 : Predicate<"Subtarget->hasVendorXSiFivecflushdlone()">, 1194 AssemblerPredicate<(all_of FeatureVendorXSiFivecflushdlone), 1195 "'XSiFivecflushdlone' (SiFive sf.cflush.d.l1 Instruction)">; 1196 1197def FeatureVendorXSfcease 1198 : RISCVExtension<"xsfcease", 1, 0, 1199 "'XSfcease' (SiFive sf.cease Instruction)", []>; 1200def HasVendorXSfcease 1201 : Predicate<"Subtarget->hasVendorXSfcease()">, 1202 AssemblerPredicate<(all_of FeatureVendorXSfcease), 1203 "'XSfcease' (SiFive sf.cease Instruction)">; 1204 1205// Core-V Extensions 1206 1207def FeatureVendorXCVelw 1208 : RISCVExtension<"xcvelw", 1, 0, 1209 "'XCVelw' (CORE-V Event Load Word)">; 1210def HasVendorXCVelw 1211 : Predicate<"Subtarget->hasVendorXCVelw()">, 1212 AssemblerPredicate<(any_of FeatureVendorXCVelw), 1213 "'XCVelw' (CORE-V Event Load Word)">; 1214 1215def FeatureVendorXCVbitmanip 1216 : RISCVExtension<"xcvbitmanip", 1, 0, 1217 "'XCVbitmanip' (CORE-V Bit Manipulation)">; 1218def HasVendorXCVbitmanip 1219 : Predicate<"Subtarget->hasVendorXCVbitmanip()">, 1220 AssemblerPredicate<(all_of FeatureVendorXCVbitmanip), 1221 "'XCVbitmanip' (CORE-V Bit Manipulation)">; 1222 1223def FeatureVendorXCVmac 1224 : RISCVExtension<"xcvmac", 1, 0, 1225 "'XCVmac' (CORE-V Multiply-Accumulate)">; 1226def HasVendorXCVmac 1227 : Predicate<"Subtarget->hasVendorXCVmac()">, 1228 AssemblerPredicate<(all_of FeatureVendorXCVmac), 1229 "'XCVmac' (CORE-V Multiply-Accumulate)">; 1230 1231def FeatureVendorXCVmem 1232 : RISCVExtension<"xcvmem", 1, 0, 1233 "'XCVmem' (CORE-V Post-incrementing Load & Store)">; 1234def HasVendorXCVmem 1235 : Predicate<"Subtarget->hasVendorXCVmem()">, 1236 AssemblerPredicate<(any_of FeatureVendorXCVmem), 1237 "'XCVmem' (CORE-V Post-incrementing Load & Store)">; 1238 1239def FeatureVendorXCValu 1240 : RISCVExtension<"xcvalu", 1, 0, 1241 "'XCValu' (CORE-V ALU Operations)">; 1242def HasVendorXCValu 1243 : Predicate<"Subtarget->hasVendorXCValu()">, 1244 AssemblerPredicate<(all_of FeatureVendorXCValu), 1245 "'XCValu' (CORE-V ALU Operations)">; 1246 1247def FeatureVendorXCVsimd 1248 : RISCVExtension<"xcvsimd", 1, 0, 1249 "'XCVsimd' (CORE-V SIMD ALU)">; 1250def HasVendorXCVsimd 1251 : Predicate<"Subtarget->hasVendorXCVsimd()">, 1252 AssemblerPredicate<(any_of FeatureVendorXCVsimd), 1253 "'XCVsimd' (CORE-V SIMD ALU)">; 1254 1255def FeatureVendorXCVbi 1256 : RISCVExtension<"xcvbi", 1, 0, 1257 "'XCVbi' (CORE-V Immediate Branching)">; 1258def HasVendorXCVbi 1259 : Predicate<"Subtarget->hasVendorXCVbi()">, 1260 AssemblerPredicate<(all_of FeatureVendorXCVbi), 1261 "'XCVbi' (CORE-V Immediate Branching)">; 1262 1263// WCH / Nanjing Qinheng Microelectronics Extension(s) 1264 1265def FeatureVendorXwchc 1266 : RISCVExtension<"xwchc", 2, 2, 1267 "'Xwchc' (WCH/QingKe additional compressed opcodes)">; 1268def HasVendorXwchc 1269 : Predicate<"Subtarget->hasVendorXwchc()">, 1270 AssemblerPredicate<(all_of FeatureVendorXwchc), 1271 "'Xwchc' (WCH/QingKe additional compressed opcodes)">; 1272 1273//===----------------------------------------------------------------------===// 1274// LLVM specific features and extensions 1275//===----------------------------------------------------------------------===// 1276 1277// Feature32Bit exists to mark CPUs that support RV32 to distinquish them from 1278// tuning CPU names. 1279def Feature32Bit 1280 : SubtargetFeature<"32bit", "IsRV32", "true", "Implements RV32">; 1281def Feature64Bit 1282 : SubtargetFeature<"64bit", "IsRV64", "true", "Implements RV64">; 1283def IsRV64 : Predicate<"Subtarget->is64Bit()">, 1284 AssemblerPredicate<(all_of Feature64Bit), 1285 "RV64I Base Instruction Set">; 1286def IsRV32 : Predicate<"!Subtarget->is64Bit()">, 1287 AssemblerPredicate<(all_of (not Feature64Bit)), 1288 "RV32I Base Instruction Set">; 1289 1290defvar RV32 = DefaultMode; 1291def RV64 : HwMode<"+64bit", [IsRV64]>; 1292 1293def FeatureRelax 1294 : SubtargetFeature<"relax", "EnableLinkerRelax", "true", 1295 "Enable Linker relaxation.">; 1296 1297foreach i = {1-31} in 1298 def FeatureReserveX#i : 1299 SubtargetFeature<"reserve-x"#i, "UserReservedRegister[RISCV::X"#i#"]", 1300 "true", "Reserve X"#i>; 1301 1302def FeatureSaveRestore : SubtargetFeature<"save-restore", "EnableSaveRestore", 1303 "true", "Enable save/restore.">; 1304 1305def FeatureNoTrailingSeqCstFence : SubtargetFeature<"no-trailing-seq-cst-fence", 1306 "EnableTrailingSeqCstFence", 1307 "false", 1308 "Disable trailing fence for seq-cst store.">; 1309 1310def FeatureUnalignedScalarMem 1311 : SubtargetFeature<"unaligned-scalar-mem", "EnableUnalignedScalarMem", 1312 "true", "Has reasonably performant unaligned scalar " 1313 "loads and stores">; 1314 1315def FeatureUnalignedVectorMem 1316 : SubtargetFeature<"unaligned-vector-mem", "EnableUnalignedVectorMem", 1317 "true", "Has reasonably performant unaligned vector " 1318 "loads and stores">; 1319 1320def FeaturePostRAScheduler : SubtargetFeature<"use-postra-scheduler", 1321 "UsePostRAScheduler", "true", "Schedule again after register allocation">; 1322 1323def FeaturePredictableSelectIsExpensive 1324 : SubtargetFeature<"predictable-select-expensive", "PredictableSelectIsExpensive", "true", 1325 "Prefer likely predicted branches over selects">; 1326 1327def TuneOptimizedZeroStrideLoad 1328 : SubtargetFeature<"optimized-zero-stride-load", "HasOptimizedZeroStrideLoad", 1329 "true", "Optimized (perform fewer memory operations)" 1330 "zero-stride vector load">; 1331 1332def Experimental 1333 : SubtargetFeature<"experimental", "HasExperimental", 1334 "true", "Experimental intrinsics">; 1335 1336// Some vector hardware implementations do not process all VLEN bits in parallel 1337// and instead split over multiple cycles. DLEN refers to the datapath width 1338// that can be done in parallel. 1339def TuneDLenFactor2 1340 : SubtargetFeature<"dlen-factor-2", "DLenFactor2", "true", 1341 "Vector unit DLEN(data path width) is half of VLEN">; 1342 1343def TuneNoDefaultUnroll 1344 : SubtargetFeature<"no-default-unroll", "EnableDefaultUnroll", "false", 1345 "Disable default unroll preference.">; 1346 1347// SiFive 7 is able to fuse integer ALU operations with a preceding branch 1348// instruction. 1349def TuneShortForwardBranchOpt 1350 : SubtargetFeature<"short-forward-branch-opt", "HasShortForwardBranchOpt", 1351 "true", "Enable short forward branch optimization">; 1352def HasShortForwardBranchOpt : Predicate<"Subtarget->hasShortForwardBranchOpt()">; 1353def NoShortForwardBranchOpt : Predicate<"!Subtarget->hasShortForwardBranchOpt()">; 1354 1355// Some subtargets require a S2V transfer buffer to move scalars into vectors. 1356// FIXME: Forming .vx/.vf/.wx/.wf can reduce register pressure. 1357def TuneNoSinkSplatOperands 1358 : SubtargetFeature<"no-sink-splat-operands", "SinkSplatOperands", 1359 "false", "Disable sink splat operands to enable .vx, .vf," 1360 ".wx, and .wf instructions">; 1361 1362def TunePreferWInst 1363 : SubtargetFeature<"prefer-w-inst", "PreferWInst", "true", 1364 "Prefer instructions with W suffix">; 1365 1366def TuneConditionalCompressedMoveFusion 1367 : SubtargetFeature<"conditional-cmv-fusion", "HasConditionalCompressedMoveFusion", 1368 "true", "Enable branch+c.mv fusion">; 1369def HasConditionalMoveFusion : Predicate<"Subtarget->hasConditionalMoveFusion()">; 1370def NoConditionalMoveFusion : Predicate<"!Subtarget->hasConditionalMoveFusion()">; 1371 1372def TuneSiFive7 : SubtargetFeature<"sifive7", "RISCVProcFamily", "SiFive7", 1373 "SiFive 7-Series processors", 1374 [TuneNoDefaultUnroll, 1375 TuneShortForwardBranchOpt]>; 1376 1377def TuneVentanaVeyron : SubtargetFeature<"ventana-veyron", "RISCVProcFamily", "VentanaVeyron", 1378 "Ventana Veyron-Series processors">; 1379 1380// Assume that lock-free native-width atomics are available, even if the target 1381// and operating system combination would not usually provide them. The user 1382// is responsible for providing any necessary __sync implementations. Code 1383// built with this feature is not ABI-compatible with code built without this 1384// feature, if atomic variables are exposed across the ABI boundary. 1385def FeatureForcedAtomics : SubtargetFeature< 1386 "forced-atomics", "HasForcedAtomics", "true", 1387 "Assume that lock-free native-width atomics are available">; 1388def HasAtomicLdSt 1389 : Predicate<"Subtarget->hasStdExtA() || Subtarget->hasForcedAtomics()">; 1390 1391def FeatureTaggedGlobals : SubtargetFeature<"tagged-globals", 1392 "AllowTaggedGlobals", 1393 "true", "Use an instruction sequence for taking the address of a global " 1394 "that allows a memory tag in the upper address bits">; 1395 1396def FeatureForcedSWShadowStack : SubtargetFeature< 1397 "forced-sw-shadow-stack", "HasForcedSWShadowStack", "true", 1398 "Implement shadow stack with software.">; 1399def HasForcedSWShadowStack : Predicate<"Subtarget->hasForcedSWShadowStack()">; 1400