Lines Matching +full:supervisor +full:- +full:level
1 //===- RISCVSystemOperands.td ------------------------------*- tablegen -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
10 // RISC-V system instruction.
12 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
18 //===----------------------------------------------------------------------===//
30 // Privilege Access: Read and Write = 0, 1, 2; Read-Only = 3.
32 // bits<2> ReadWrite = op{11 - 10};
33 // bits<2> XMode = op{9 - 8};
34 // Check Extra field name and what bits 7-6 correspond to.
35 // bits<2> Extra = op{7 - 6};
37 // bits<6> Number = op{5 - 0};
71 // 2.3, 2.4, 2.5 and 2.6 in the RISC-V Instruction Set Manual
74 //===----------------------------------------------------------------------===//
75 // User Floating-Point CSRs
76 //===----------------------------------------------------------------------===//
82 //===----------------------------------------------------------------------===//
84 //===----------------------------------------------------------------------===//
89 // hpmcounter3-hpmcounter31 at 0xC03-0xC1F.
98 // hpmcounter3h-hpmcounter31h at 0xC83-0xC9F.
103 //===----------------------------------------------------------------------===//
104 // Supervisor Trap Setup
105 //===----------------------------------------------------------------------===//
114 //===----------------------------------------------------------------------===//
115 // Supervisor Configuration
116 //===----------------------------------------------------------------------===//
120 //===----------------------------------------------------------------------===//
121 // Supervisor Trap Handling
122 //===----------------------------------------------------------------------===//
130 //===----------------------------------------------------------------------===//
131 // Supervisor Protection and Translation
132 //===----------------------------------------------------------------------===//
136 //===----------------------------------------------------------------------===//
137 // Quality-of-Service(QoS) Identifiers (Ssqosid)
138 //===----------------------------------------------------------------------===//
141 //===----------------------------------------------------------------------===//
143 //===----------------------------------------------------------------------===//
147 //===----------------------------------------------------------------------===//
148 // Supervisor Count Overflow (defined in Sscofpmf)
149 //===----------------------------------------------------------------------===//
153 //===----------------------------------------------------------------------===//
155 //===----------------------------------------------------------------------===//
164 //===----------------------------------------------------------------------===//
166 //===----------------------------------------------------------------------===//
174 //===----------------------------------------------------------------------===//
176 //===----------------------------------------------------------------------===//
182 //===----------------------------------------------------------------------===//
184 //===----------------------------------------------------------------------===//
188 //===----------------------------------------------------------------------===//
190 //===----------------------------------------------------------------------===//
194 //===----------------------------------------------------------------------===//
196 //===----------------------------------------------------------------------===//
202 //===----------------------------------------------------------------------===//
203 // Virtual Supervisor Registers
204 //===----------------------------------------------------------------------===//
219 //===----------------------------------------------------------------------===//
221 //===----------------------------------------------------------------------===//
229 //===----------------------------------------------------------------------===//
231 //===----------------------------------------------------------------------===//
242 //===----------------------------------------------------------------------===//
244 //===----------------------------------------------------------------------===//
254 //===----------------------------------------------------------------------===//
256 //===----------------------------------------------------------------------===//
265 //===----------------------------------------------------------------------===//
267 //===----------------------------------------------------------------------===//
269 // pmpcfg0-pmpcfg15 at 0x3A0-0x3AF. Odd-numbered registers are RV32-only.
275 // pmpaddr0-pmpaddr63 at 0x3B0-0x3EF.
279 //===----------------------------------------------------------------------===//
281 //===----------------------------------------------------------------------===//
285 // mhpmcounter3-mhpmcounter31 at 0xB03-0xB1F.
293 // mhpmcounter3h-mhpmcounter31h at 0xB83-0xB9F.
298 //===----------------------------------------------------------------------===//
300 //===----------------------------------------------------------------------===//
304 // mhpmevent3-mhpmevent31 at 0x323-0x33F.
308 // mhpmevent3h-mhpmevent31h at 0x723-0x73F
314 //===----------------------------------------------------------------------===//
315 // Supervisor Counter Setup
316 //===----------------------------------------------------------------------===//
319 //===----------------------------------------------------------------------===//
321 //===----------------------------------------------------------------------===//
328 //===----------------------------------------------------------------------===//
330 //===----------------------------------------------------------------------===//
335 // drafts of the RISC-V debug spec
340 //===----------------------------------------------------------------------===//
342 //===----------------------------------------------------------------------===//
351 //===----------------------------------------------------------------------===//
353 //===----------------------------------------------------------------------===//
356 //===----------------------------------------------------------------------===//
358 //===----------------------------------------------------------------------===//
360 // sstateen0-sstateen3 at 0x10C-0x10F, mstateen0-mstateen3 at 0x30C-0x30F,
361 // mstateen0h-mstateen3h at 0x31C-0x31F, hstateen0-hstateen3 at 0x60C-0x60F,
362 // and hstateen0h-hstateen3h at 0x61C-0x61F.
373 //===-----------------------------------------------
375 //===-----------------------------------------------
379 //===-----------------------------------------------
381 //===-----------------------------------------------
383 // Machine-level CSRs
404 // Supervisor-level CSRs
445 //===-----------------------------------------------
447 //===-----------------------------------------------
451 //===-----------------------------------------------
452 // Resumable Non-Maskable Interrupts(Smrnmi) CSRs
453 //===-----------------------------------------------