Home
last modified time | relevance | path

Searched full:src3 (Results 1 – 25 of 69) sorted by relevance

123

/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonDepMapAsm2Intrin.td290 def: Pat<(int_hexagon_A2_vraddub_acc DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3),
291 (A2_vraddub_acc DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>;
294 def: Pat<(int_hexagon_A2_vrsadub_acc DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3),
295 (A2_vrsadub_acc DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>;
408 def: Pat<(int_hexagon_A4_vrmaxh DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),
409 (A4_vrmaxh DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;
410 def: Pat<(int_hexagon_A4_vrmaxuh DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),
411 (A4_vrmaxuh DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;
412 def: Pat<(int_hexagon_A4_vrmaxuw DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),
413 (A4_vrmaxuw DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;
[all …]
H A DHexagonMapAsm2IntrinV62.gen.td17 def: Pat<(IntID HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3),
18 (MI HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>;
20 IntRegsLow8:$src3),
21 (MI HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>;
39 def: Pat<(IntID HvxWR:$src1, HvxVR:$src2, HvxVR:$src3),
40 (MI HvxWR:$src1, HvxVR:$src2, HvxVR:$src3)>;
42 HvxVR:$src3),
43 (MI HvxWR:$src1, HvxVR:$src2, HvxVR:$src3)>;
54 def: Pat<(IntID HvxWR:$src1, HvxWR:$src2, IntRegs:$src3),
55 (MI HvxWR:$src1, HvxWR:$src2, IntRegs:$src3)>;
[all …]
H A DHexagonIntrinsicsV60.td171 def: Pat<(IntID HvxWR:$src1, HvxWR:$src2, IntRegs:$src3),
172 (MI HvxWR:$src1, HvxWR:$src2, IntRegs:$src3)>;
175 IntRegs:$src3),
176 (MI HvxWR:$src1, HvxWR:$src2, IntRegs:$src3)>;
180 def: Pat<(IntID HvxVR:$src1, HvxVR:$src2, IntRegs:$src3),
181 (MI HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>;
184 IntRegs:$src3),
185 (MI HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>;
189 def: Pat<(IntID HvxWR:$src1, HvxVR:$src2, IntRegs:$src3),
190 (MI HvxWR:$src1, HvxVR:$src2, IntRegs:$src3)>;
[all …]
H A DHexagonIntrinsics.td145 : Pat <(IntID I32:$src1, I32:$src2, u4_0ImmPred_timm:$src3, u5_0ImmPred_timm:$src4),
146 (OutputInst I32:$src1, I32:$src2, u4_0ImmPred:$src3,
207 def : Pat<(IntID HvxQR:$src1, IntRegs:$src2, HvxVR:$src3),
208 (MI HvxQR:$src1, IntRegs:$src2, 0, HvxVR:$src3)>,
212 HvxVR:$src3),
213 (MI HvxQR:$src1, IntRegs:$src2, 0, HvxVR:$src3)>,
310 def: Pat<(IntID HvxVR:$src1, HvxVR:$src2, u3_0ImmPred:$src3),
311 (MI HvxVR:$src1, HvxVR:$src2, u3_0ImmPred:$src3)>,
315 u3_0ImmPred:$src3),
317 u3_0ImmPred:$src3)>,
[all …]
H A DHexagonIntrinsicsV5.td178 u2_0ImmPred:$src3),
179 (S4_vrcrotate DoubleRegs:$src1, IntRegs:$src2, u2_0ImmPred:$src3)>;
184 IntRegs:$src3, u2_0ImmPred:$src4),
186 IntRegs:$src3, u2_0ImmPred:$src4)>;
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InstrFMA.td40 (ins RC:$src1, RC:$src2, RC:$src3),
42 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
43 [(set RC:$dst, (VT (Op RC:$src2, RC:$src1, RC:$src3)))]>,
48 (ins RC:$src1, RC:$src2, x86memop:$src3),
50 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
52 (MemFrag addr:$src3))))]>,
61 (ins RC:$src1, RC:$src2, RC:$src3),
63 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
68 (ins RC:$src1, RC:$src2, x86memop:$src3),
70 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
[all …]
H A DX86InstrAMX.td67 opaquemem:$src3), []>;
71 opaquemem:$src3), []>;
74 GR16:$src2, opaquemem:$src3,
102 (ins TILE:$src1, TILE:$src2, TILE:$src3),
103 "tdpbssd\t{$src3, $src2, $dst|$dst, $src2, $src3}", []>,
106 (ins TILE:$src1, TILE:$src2, TILE:$src3),
107 "tdpbsud\t{$src3, $src2, $dst|$dst, $src2, $src3}", []>,
110 (ins TILE:$src1, TILE:$src2, TILE:$src3),
111 "tdpbusd\t{$src3, $src2, $dst|$dst, $src2, $src3}", []>,
114 (ins TILE:$src1, TILE:$src2, TILE:$src3),
[all …]
H A DX86InstrXOP.td172 (ins VR128:$src1, VR128:$src2, VR128:$src3),
174 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
176 (Int VR128:$src1, VR128:$src2, VR128:$src3))]>, XOP, VVVV,
179 (ins VR128:$src1, i128mem:$src2, VR128:$src3),
181 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
184 VR128:$src3))]>, XOP, VVVV, Sched<[sched.Folded, sched.ReadAfterFold]>;
218 (v8i16 VR128:$src3))),
219 (VPMACSWWrr VR128:$src1, VR128:$src2, VR128:$src3)>;
[all...]
H A DX86InstrSSE.td2076 (ins RC:$src1, x86memop:$src2, u8imm:$src3), asm,
2078 (i8 timm:$src3))))], d>,
2082 (ins RC:$src1, RC:$src2, u8imm:$src3), asm,
2084 (i8 timm:$src3))))], d>,
2090 "shufps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2094 "shufps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2098 "shufpd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2102 "shufpd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2108 "shufps\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2111 "shufpd\t{$src3, $src2, $dst|$dst, $src2, $src3}",
[all …]
H A DX86InstrAVX512.td372 (ins To.RC:$src1, From.RC:$src2, u8imm:$src3),
374 "$src3, $src2, $src1", "$src1, $src2, $src3",
375 (vinsert_insert:$src3 (To.VT To.RC:$src1),
378 (vinsert_for_mask:$src3 (To.VT To.RC:$src1),
384 (ins To.RC:$src1, From.MemOp:$src2, u8imm:$src3),
386 "$src3, $src2, $src1", "$src1, $src2, $src3",
387 (vinsert_insert:$src3 (To.VT To.RC:$src1),
390 (vinsert_for_mask:$src3 (To.VT To.RC:$src1),
653 (ins VR128X:$src1, VR128X:$src2, u8imm:$src3),
654 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
[all …]
H A DX86InstrShiftRotate.td348 (ins t.RegClass:$src1, t.RegClass:$src2, u8imm:$src3), m, !if(!eq(ndd, 0), triop_args, triop_ndd_args),
354 [(set t.RegClass:$dst, (node t.RegClass:$src1, t.RegClass:$src2, (i8 imm:$src3)))],
355 [(set t.RegClass:$dst, (node t.RegClass:$src2, t.RegClass:$src1, (i8 imm:$src3)))]);
368 : ITy<o, MRMDestMem, t, (outs), (ins t.MemOperand:$src1, t.RegClass:$src2, u8imm:$src3),
375 [(store (node (t.LoadNode addr:$src1), t.RegClass:$src2, (i8 imm:$src3)), addr:$src1)],
376 [(store (node t.RegClass:$src2, (t.LoadNode addr:$src1), (i8 imm:$src3)), addr:$src1)]);
390 : ITy<o, MRMDestMem, t, (outs t.RegClass:$dst), (ins t.MemOperand:$src1, t.RegClass:$src2, u8imm:$src3),
396 [(set t.RegClass:$dst, (node (t.LoadNode addr:$src1), t.RegClass:$src2, (i8 imm:$src3)))],
397 [(set t.RegClass:$dst, (node t.RegClass:$src2, (t.LoadNode addr:$src1), (i8 imm:$src3)))]);
H A DX86InstrFragmentsSIMD.td201 def X86any_cmpp : PatFrags<(ops node:$src1, node:$src2, node:$src3),
202 [(X86strict_cmpp node:$src1, node:$src2, node:$src3),
203 (X86cmpp node:$src1, node:$src2, node:$src3)]>;
220 def X86any_cmpm : PatFrags<(ops node:$src1, node:$src2, node:$src3),
221 [(X86strict_cmpm node:$src1, node:$src2, node:$src3),
222 (X86cmpm node:$src1, node:$src2, node:$src3)]>;
542 def X86any_Fnmadd : PatFrags<(ops node:$src1, node:$src2, node:$src3),
543 [(X86strict_Fnmadd node:$src1, node:$src2, node:$src3),
544 (X86Fnmadd node:$src1, node:$src2, node:$src3)]>;
547 def X86any_Fmsub : PatFrags<(ops node:$src1, node:$src2, node:$src3),
[all …]
H A DX86InstrMMX.td111 (ins VR64:$src1, VR64:$src2, u8imm:$src3),
112 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
113 [(set VR64:$dst, (IntId VR64:$src1, VR64:$src2, (i8 timm:$src3)))]>,
116 (ins VR64:$src1, i64mem:$src2, u8imm:$src3),
117 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
119 (i8 timm:$src3)))]>,
522 (ins VR64:$src1, GR32orGR64:$src2, i32u8imm:$src3),
523 "pinsrw\t{$src3,
[all...]
H A DX86InstrAsmAlias.td55 def : InstAlias<"cmp"#Cond#"xadd"#"\t{$src3, $dst, $dstsrc2|$dstsrc2, $dst, $src3}",
56 (CMPCCXADDmr32 GR32:$dst, i32mem:$dstsrc2, GR32:$src3, CC), 0>;
57 def : InstAlias<"cmp"#Cond#"xadd"#"\t{$src3, $dst, $dstsrc2|$dstsrc2, $dst, $src3}",
58 (CMPCCXADDmr64 GR64:$dst, i64mem:$dstsrc2, GR64:$src3, CC), 0>;
60 def : InstAlias<"cmp"#Cond#"xadd"#"\t{$src3, $dst, $dstsrc2|$dstsrc2, $dst, $src3}",
61 (CMPCCXADDmr32_EVEX GR32:$dst, i32mem:$dstsrc2, GR32:$src3, CC), 0>;
62 def : InstAlias<"cmp"#Cond#"xadd"#"\t{$src3, $dst, $dstsrc2|$dstsrc2, $dst, $src3}",
63 (CMPCCXADDmr64_EVEX GR64:$dst, i64mem:$dstsrc2, GR64:$src3, CC), 0>;
H A DX86InstrMisc.td1686 (ins GR32:$dstsrc1, i32mem:$dstsrc2, GR32:$src3, ccode:$cond),
1687 "cmp${cond}xadd\t{$src3, $dst, $dstsrc2|$dstsrc2, $dst, $src3}",
1689 GR32:$dstsrc1, GR32:$src3, timm:$cond))]>,
1693 (ins GR64:$dstsrc1, i64mem:$dstsrc2, GR64:$src3, ccode:$cond),
1694 "cmp${cond}xadd\t{$src3, $dst, $dstsrc2|$dstsrc2, $dst, $src3}",
1696 GR64:$dstsrc1, GR64:$src3, timm:$cond))]>,
1702 (ins GR32:$dstsrc1, i32mem:$dstsrc2, GR32:$src3, ccode:$cond),
1703 "cmp${cond}xadd\t{$src3, $dst, $dstsrc2|$dstsrc2, $dst, $src3}",
1705 GR32:$dstsrc1, GR32:$src3, timm:$cond))]>,
1709 (ins GR64:$dstsrc1, i64mem:$dstsrc2, GR64:$src3, ccode:$cond),
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DEXPInstructions.td16 ExpSrc0:$src0, ExpSrc1:$src1, ExpSrc2:$src2, ExpSrc3:$src3,
41 : EXPCommon<0, ps.done, "exp$tgt $src0, $src1, $src2, $src3"
49 : EXPCommon<ps.row, ps.done, name#"$tgt $src0, $src1, $src2, $src3"
143 (vt ExpSrc2:$src2), (vt ExpSrc3:$src3),
146 ExpSrc2:$src2, ExpSrc3:$src3, timm:$vm, 0, timm:$en)
152 (vt ExpSrc2:$src2), (vt ExpSrc3:$src3),
155 ExpSrc2:$src2, ExpSrc3:$src3, 0, 0, timm:$en)
/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZOperators.td783 def z_muladd : PatFrag<(ops node:$src1, node:$src2, node:$src3),
784 (add (mul node:$src1, node:$src2), node:$src3)>;
813 def any_fms : PatFrag<(ops node:$src1, node:$src2, node:$src3),
814 (any_fma node:$src1, node:$src2, (fneg node:$src3))>;
818 def z_any_fma : PatFrag<(ops node:$src1, node:$src2, node:$src3),
819 (any_fma node:$src2, node:$src3, node:$src1)>;
820 def z_any_fms : PatFrag<(ops node:$src1, node:$src2, node:$src3),
821 (any_fma node:$src2, node:$src3, (fneg node:$src1))>;
824 def any_fnma : PatFrag<(ops node:$src1, node:$src2, node:$src3),
825 (fneg (any_fma node:$src1, node:$src2, node:$src3))>;
[all …]
/freebsd/sys/contrib/openzfs/module/zfs/
H A Dvdev_raidz_math_powerpc_altivec_common.h145 "lvx 18,0,%[SRC3]\n" \
163 [SRC3] "r" ((OFFSET(src, 48))), \
175 "lvx 18,0,%[SRC3]\n" \
184 [SRC3] "r" ((OFFSET(src, 48))) \
294 "lvx " VR3(r) " ,0,%[SRC3]\n" \
304 [SRC3] "r" ((OFFSET(src, 48))), \
315 "lvx " VR3(r) " ,0,%[SRC3]\n" \
320 [SRC3] "r" ((OFFSET(src, 48)))); \
H A Dvdev_raidz_math_aarch64_neon_common.h148 "ld1 { v18.4s },%[SRC3]\n" \
166 [SRC3] "Q" (*(OFFSET(src, 48))), \
178 "ld1 { v18.4s },%[SRC3]\n" \
187 [SRC3] "Q" (*(OFFSET(src, 48))) \
297 "ld1 { " VR3(r) ".4s },%[SRC3]\n" \
307 [SRC3] "Q" (*(OFFSET(src, 48))), \
318 "ld1 { " VR3(r) ".4s },%[SRC3]\n" \
323 [SRC3] "Q" (*(OFFSET(src, 48)))); \
/freebsd/contrib/llvm-project/llvm/lib/Target/XCore/
H A DXCoreInstrInfo.td460 (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3),
461 "crc32 $dst, $src2, $src3",
464 GRRegs:$src3))]>;
503 (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3),
504 "ladd $dst2, $dst1, $src1, $src2, $src3",
508 (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3),
509 "lsub $dst2, $dst1, $src1, $src2, $src3", []>;
512 (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3),
513 "ldivu $dst1, $dst2, $src3, $src1, $src2", []>;
519 (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3, GRRegs:$src4),
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DREADME_P9.txt256 v ← bfp_MULTIPLY_ADD(src1, src3, src2)
261 v ← bfp_MULTIPLY_ADD(src1, src3, bfp_NEGATE(src2))
266 v ← bfp_MULTIPLY_ADD(src1,src3,src2)
271 v ← bfp_MULTIPLY_ADD(src1, src3, bfp_NEGATE(src2))
/freebsd/sys/contrib/device-tree/Bindings/sound/
H A Drenesas,rsnd.txt40 Capture: [MEM] <- [DVC1] <- [SRC3] <- [SSIU1/SSI1] <- [codec]
50 &src3 &ctu03 &ssi3
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/MCTargetDesc/
H A DX86InstComments.cpp283 // dest, src1, src2, src3 in printFMAComments()
284 // dest, src1, mask, src2, src3 in printFMAComments()
285 // Where src3 is either a register or 5 memory address operands. So to find in printFMAComments()
286 // dest and src1 we can index from the front. To find src2 and src3 we can in printFMAComments()
291 // dest, src1, src2, src3 in printFMAComments()
292 // Where src2 OR src3 are either a register or 5 memory address operands. So in printFMAComments()
294 // and then src3 (reg) will be at the end. in printFMAComments()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64InstrGISel.td256 let InOperandList = (ins type0:$src1, type0:$src2, type0:$src3);
262 let InOperandList = (ins type0:$src1, type0:$src2, type0:$src3);
270 let InOperandList = (ins type0:$src1, type0:$src2, type0:$src3);
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMInstrNEON.td1216 (ins addrmode6:$Rn, DPR:$src1, DPR:$src2, DPR:$src3,
1219 "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3", []>, Sched<[WriteVLD2]> {
1254 DPR:$src1, DPR:$src2, DPR:$src3, nohash_imm:$lane),
1257 "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3, $Rn.addr = $wb",
1290 (ins addrmode6:$Rn, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4,
1293 "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3, $src4 = $dst4", []>,
1332 DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4, nohash_imm:$lane),
1335 "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3, $src4 = $dst4, $Rn.addr = $wb",
2023 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3), IIC_VST3,
2024 "vst3", Dt, "\\{$Vd, $src2, $src3\\}, $Rn", "", []>, Sched<[WriteVST3]> {
[all …]

123