Lines Matching full:src3
40 (ins RC:$src1, RC:$src2, RC:$src3),
42 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
43 [(set RC:$dst, (VT (Op RC:$src2, RC:$src1, RC:$src3)))]>,
48 (ins RC:$src1, RC:$src2, x86memop:$src3),
50 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
52 (MemFrag addr:$src3))))]>,
61 (ins RC:$src1, RC:$src2, RC:$src3),
63 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
68 (ins RC:$src1, RC:$src2, x86memop:$src3),
70 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
71 [(set RC:$dst, (VT (Op RC:$src2, (MemFrag addr:$src3),
81 (ins RC:$src1, RC:$src2, RC:$src3),
83 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
90 (ins RC:$src1, RC:$src2, x86memop:$src3),
92 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
93 [(set RC:$dst, (VT (Op (MemFrag addr:$src3), RC:$src1,
182 (ins RC:$src1, RC:$src2, RC:$src3),
184 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
185 [(set RC:$dst, (OpNode RC:$src2, RC:$src1, RC:$src3))]>,
190 (ins RC:$src1, RC:$src2, x86memop:$src3),
192 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
194 (OpNode RC:$src2, RC:$src1, (load addr:$src3)))]>,
203 (ins RC:$src1, RC:$src2, RC:$src3),
205 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
210 (ins RC:$src1, RC:$src2, x86memop:$src3),
212 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
214 (OpNode RC:$src2, (load addr:$src3), RC:$src1))]>,
223 (ins RC:$src1, RC:$src2, RC:$src3),
225 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
232 (ins RC:$src1, RC:$src2, x86memop:$src3),
234 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
236 (OpNode (load addr:$src3), RC:$src1, RC:$src2))]>,
273 (ins RC:$src1, RC:$src2, RC:$src3),
275 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
280 (ins RC:$src1, RC:$src2, memopr:$src3),
282 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
339 RC:$src3))))),
342 (VT (COPY_TO_REGCLASS RC:$src3, VR128)))>;
345 (Op RC:$src2, RC:$src3,
349 (VT (COPY_TO_REGCLASS RC:$src3, VR128)))>;
354 (mem_frag addr:$src3)))))),
357 addr:$src3)>;
361 (mem_frag addr:$src3), RC:$src2))))),
364 addr:$src3)>;
367 (Op RC:$src2, (mem_frag addr:$src3),
371 addr:$src3)>;
395 (ins RC:$src1, RC:$src2, RC:$src3),
397 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
399 (OpVT (OpNode RC:$src1, RC:$src2, RC:$src3)))]>, REX_W, VEX_LIG,
402 (ins RC:$src1, RC:$src2, x86memop:$src3),
404 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
406 (mem_frag addr:$src3)))]>, REX_W, VEX_LIG,
409 (ins RC:$src1, x86memop:$src2, RC:$src3),
411 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
413 (OpNode RC:$src1, (mem_frag addr:$src2), RC:$src3))]>, VEX_LIG,
418 // RC:$src3
423 (ins RC:$src1, RC:$src2, RC:$src3),
425 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"), []>,
434 (ins VR128:$src1, VR128:$src2, VR128:$src3),
436 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
440 (ins VR128:$src1, VR128:$src2, memop:$src3),
442 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
447 (ins VR128:$src1, memop:$src2, VR128:$src3),
449 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
455 // VR128::$src3
458 (ins VR128:$src1, VR128:$src2, VR128:$src3),
460 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
472 (ins VR128:$src1, VR128:$src2, VR128:$src3),
474 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
476 (OpVT128 (OpNode VR128:$src1, VR128:$src2, VR128:$src3)))]>,
479 (ins VR128:$src1, VR128:$src2, f128mem:$src3),
481 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
483 (ld_frag128 addr:$src3)))]>, REX_W,
486 (ins VR128:$src1, f128mem:$src2, VR128:$src3),
488 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
490 (OpNode VR128:$src1, (ld_frag128 addr:$src2), VR128:$src3))]>,
495 // VR128::$src3
499 (ins VR256:$src1, VR256:$src2, VR256:$src3),
501 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
503 (OpVT256 (OpNode VR256:$src1, VR256:$src2, VR256:$src3)))]>,
506 (ins VR256:$src1, VR256:$src2, f256mem:$src3),
508 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
510 (ld_frag256 addr:$src3)))]>, REX_W, VEX_L,
513 (ins VR256:$src1, f256mem:$src2, VR256:$src3),
515 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
517 (ld_frag256 addr:$src2), VR256:$src3))]>, VEX_L,
522 // VR256::$src3
527 (ins VR128:$src1, VR128:$src2, VR128:$src3),
529 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"), []>,
532 (ins VR256:$src1, VR256:$src2, VR256:$src3),
534 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"), []>,
602 (Op RC:$src1, RC:$src2, RC:$src3))))),
606 (VT (COPY_TO_REGCLASS RC:$src3, VR128)))>;
610 (mem_frag addr:$src3)))))),
613 (VT (COPY_TO_REGCLASS RC:$src2, VR128)), addr:$src3)>;
617 RC:$src3))))),
620 (VT (COPY_TO_REGCLASS RC:$src3, VR128)))>;