xref: /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/HexagonMapAsm2IntrinV62.gen.td (revision 0b57cec536236d46e3dba9bd041533462f33dbb7) 
1//===--- HexagonMapAsm2IntrinV62.gen.td -----------------------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9multiclass T_VR_HVX_gen_pat <InstHexagon MI, Intrinsic IntID> {
10  def: Pat<(IntID HvxVR:$src1, IntRegs:$src2),
11           (MI HvxVR:$src1, IntRegs:$src2)>;
12  def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxVR:$src1, IntRegs:$src2),
13           (MI HvxVR:$src1, IntRegs:$src2)>;
14}
15
16multiclass T_VVL_HVX_gen_pat <InstHexagon MI, Intrinsic IntID> {
17  def: Pat<(IntID HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3),
18           (MI HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>;
19  def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxVR:$src1, HvxVR:$src2,
20                                            IntRegsLow8:$src3),
21           (MI HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>;
22}
23
24multiclass T_VV_HVX_gen_pat <InstHexagon MI, Intrinsic IntID> {
25  def: Pat<(IntID HvxVR:$src1, HvxVR:$src2),
26           (MI HvxVR:$src1, HvxVR:$src2)>;
27  def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxVR:$src1, HvxVR:$src2),
28           (MI HvxVR:$src1, HvxVR:$src2)>;
29}
30
31multiclass T_WW_HVX_gen_pat <InstHexagon MI, Intrinsic IntID> {
32  def: Pat<(IntID HvxWR:$src1, HvxWR:$src2),
33           (MI HvxWR:$src1, HvxWR:$src2)>;
34  def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxWR:$src1, HvxWR:$src2),
35           (MI HvxWR:$src1, HvxWR:$src2)>;
36}
37
38multiclass T_WVV_HVX_gen_pat <InstHexagon MI, Intrinsic IntID> {
39  def: Pat<(IntID HvxWR:$src1, HvxVR:$src2, HvxVR:$src3),
40           (MI HvxWR:$src1, HvxVR:$src2, HvxVR:$src3)>;
41  def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxWR:$src1, HvxVR:$src2,
42                                            HvxVR:$src3),
43           (MI HvxWR:$src1, HvxVR:$src2, HvxVR:$src3)>;
44}
45
46multiclass T_WR_HVX_gen_pat <InstHexagon MI, Intrinsic IntID> {
47  def: Pat<(IntID HvxWR:$src1, IntRegs:$src2),
48           (MI HvxWR:$src1, IntRegs:$src2)>;
49  def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxWR:$src1, IntRegs:$src2),
50           (MI HvxWR:$src1, IntRegs:$src2)>;
51}
52
53multiclass T_WWR_HVX_gen_pat <InstHexagon MI, Intrinsic IntID> {
54  def: Pat<(IntID HvxWR:$src1, HvxWR:$src2, IntRegs:$src3),
55           (MI HvxWR:$src1, HvxWR:$src2, IntRegs:$src3)>;
56  def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxWR:$src1, HvxWR:$src2,
57                                            IntRegs:$src3),
58           (MI HvxWR:$src1, HvxWR:$src2, IntRegs:$src3)>;
59}
60
61multiclass T_VVR_HVX_gen_pat <InstHexagon MI, Intrinsic IntID> {
62  def: Pat<(IntID HvxVR:$src1, HvxVR:$src2, IntRegs:$src3),
63           (MI HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>;
64  def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxVR:$src1, HvxVR:$src2,
65                                            IntRegs:$src3),
66           (MI HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>;
67}
68
69multiclass T_ZR_HVX_gen_pat <InstHexagon MI, Intrinsic IntID> {
70  def: Pat<(IntID HvxQR:$src1, IntRegs:$src2),
71           (MI HvxQR:$src1, IntRegs:$src2)>;
72  def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxQR:$src1, IntRegs:$src2),
73           (MI HvxQR:$src1, IntRegs:$src2)>;
74}
75
76multiclass T_VZR_HVX_gen_pat <InstHexagon MI, Intrinsic IntID> {
77  def: Pat<(IntID HvxVR:$src1, HvxQR:$src2, IntRegs:$src3),
78           (MI HvxVR:$src1, HvxQR:$src2, IntRegs:$src3)>;
79  def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxVR:$src1, HvxQR:$src2,
80                                            IntRegs:$src3),
81           (MI HvxVR:$src1, HvxQR:$src2, IntRegs:$src3)>;
82}
83
84multiclass T_ZV_HVX_gen_pat <InstHexagon MI, Intrinsic IntID> {
85  def: Pat<(IntID HvxQR:$src1, HvxVR:$src2),
86           (MI HvxQR:$src1, HvxVR:$src2)>;
87  def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxQR:$src1, HvxVR:$src2),
88           (MI HvxQR:$src1, HvxVR:$src2)>;
89}
90
91multiclass T_R_HVX_gen_pat <InstHexagon MI, Intrinsic IntID> {
92  def: Pat<(IntID IntRegs:$src1),
93           (MI IntRegs:$src1)>;
94  def: Pat<(!cast<Intrinsic>(IntID#"_128B") IntRegs:$src1),
95           (MI IntRegs:$src1)>;
96}
97
98multiclass T_ZZ_HVX_gen_pat <InstHexagon MI, Intrinsic IntID> {
99  def: Pat<(IntID HvxQR:$src1, HvxQR:$src2),
100           (MI HvxQR:$src1, HvxQR:$src2)>;
101  def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxQR:$src1, HvxQR:$src2),
102           (MI HvxQR:$src1, HvxQR:$src2)>;
103}
104
105multiclass T_VVI_HVX_gen_pat <InstHexagon MI, Intrinsic IntID> {
106  def: Pat<(IntID HvxVR:$src1, HvxVR:$src2, imm:$src3),
107           (MI HvxVR:$src1, HvxVR:$src2, imm:$src3)>;
108  def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxVR:$src1, HvxVR:$src2,
109                                            imm:$src3),
110           (MI HvxVR:$src1, HvxVR:$src2, imm:$src3)>;
111}
112
113multiclass T_VVVI_HVX_gen_pat <InstHexagon MI, Intrinsic IntID> {
114  def: Pat<(IntID HvxVR:$src1, HvxVR:$src2, HvxVR:$src3, imm:$src4),
115           (MI HvxVR:$src1, HvxVR:$src2, HvxVR:$src3, imm:$src4)>;
116  def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxVR:$src1, HvxVR:$src2,
117                                            HvxVR:$src3, imm:$src4),
118           (MI HvxVR:$src1, HvxVR:$src2, HvxVR:$src3, imm:$src4)>;
119}
120
121multiclass T_WVVI_HVX_gen_pat <InstHexagon MI, Intrinsic IntID> {
122  def: Pat<(IntID HvxWR:$src1, HvxVR:$src2, HvxVR:$src3, imm:$src4),
123           (MI HvxWR:$src1, HvxVR:$src2, HvxVR:$src3, imm:$src4)>;
124  def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxWR:$src1, HvxVR:$src2,
125                                            HvxVR:$src3, imm:$src4),
126           (MI HvxWR:$src1, HvxVR:$src2, HvxVR:$src3, imm:$src4)>;
127}
128
129def : T_R_pat <S6_vsplatrbp, int_hexagon_S6_vsplatrbp>;
130def : T_PP_pat <M6_vabsdiffb, int_hexagon_M6_vabsdiffb>;
131def : T_PP_pat <M6_vabsdiffub, int_hexagon_M6_vabsdiffub>;
132def : T_PP_pat <S6_vtrunehb_ppp, int_hexagon_S6_vtrunehb_ppp>;
133def : T_PP_pat <S6_vtrunohb_ppp, int_hexagon_S6_vtrunohb_ppp>;
134
135defm : T_VR_HVX_gen_pat <V6_vlsrb, int_hexagon_V6_vlsrb>;
136defm : T_VR_HVX_gen_pat <V6_vmpyiwub, int_hexagon_V6_vmpyiwub>;
137defm : T_VVL_HVX_gen_pat <V6_vasrwuhrndsat, int_hexagon_V6_vasrwuhrndsat>;
138defm : T_VVL_HVX_gen_pat <V6_vasruwuhrndsat, int_hexagon_V6_vasruwuhrndsat>;
139defm : T_VVL_HVX_gen_pat <V6_vasrhbsat, int_hexagon_V6_vasrhbsat>;
140defm : T_VVL_HVX_gen_pat <V6_vlutvvb_nm, int_hexagon_V6_vlutvvb_nm>;
141defm : T_VVL_HVX_gen_pat <V6_vlutvwh_nm, int_hexagon_V6_vlutvwh_nm>;
142defm : T_VV_HVX_gen_pat <V6_vrounduwuh, int_hexagon_V6_vrounduwuh>;
143defm : T_VV_HVX_gen_pat <V6_vrounduhub, int_hexagon_V6_vrounduhub>;
144defm : T_VV_HVX_gen_pat <V6_vadduwsat, int_hexagon_V6_vadduwsat>;
145defm : T_VV_HVX_gen_pat <V6_vsubuwsat, int_hexagon_V6_vsubuwsat>;
146defm : T_VV_HVX_gen_pat <V6_vaddbsat, int_hexagon_V6_vaddbsat>;
147defm : T_VV_HVX_gen_pat <V6_vsubbsat, int_hexagon_V6_vsubbsat>;
148defm : T_VV_HVX_gen_pat <V6_vaddububb_sat, int_hexagon_V6_vaddububb_sat>;
149defm : T_VV_HVX_gen_pat <V6_vsubububb_sat, int_hexagon_V6_vsubububb_sat>;
150defm : T_VV_HVX_gen_pat <V6_vmpyewuh_64, int_hexagon_V6_vmpyewuh_64>;
151defm : T_VV_HVX_gen_pat <V6_vmaxb, int_hexagon_V6_vmaxb>;
152defm : T_VV_HVX_gen_pat <V6_vminb, int_hexagon_V6_vminb>;
153defm : T_VV_HVX_gen_pat <V6_vsatuwuh, int_hexagon_V6_vsatuwuh>;
154defm : T_VV_HVX_gen_pat <V6_vaddclbw, int_hexagon_V6_vaddclbw>;
155defm : T_VV_HVX_gen_pat <V6_vaddclbh, int_hexagon_V6_vaddclbh>;
156defm : T_WW_HVX_gen_pat <V6_vadduwsat_dv, int_hexagon_V6_vadduwsat_dv>;
157defm : T_WW_HVX_gen_pat <V6_vsubuwsat_dv, int_hexagon_V6_vsubuwsat_dv>;
158defm : T_WW_HVX_gen_pat <V6_vaddbsat_dv, int_hexagon_V6_vaddbsat_dv>;
159defm : T_WW_HVX_gen_pat <V6_vsubbsat_dv, int_hexagon_V6_vsubbsat_dv>;
160defm : T_WVV_HVX_gen_pat <V6_vaddhw_acc, int_hexagon_V6_vaddhw_acc>;
161defm : T_WVV_HVX_gen_pat <V6_vadduhw_acc, int_hexagon_V6_vadduhw_acc>;
162defm : T_WVV_HVX_gen_pat <V6_vaddubh_acc, int_hexagon_V6_vaddubh_acc>;
163defm : T_WVV_HVX_gen_pat <V6_vmpyowh_64_acc, int_hexagon_V6_vmpyowh_64_acc>;
164defm : T_WR_HVX_gen_pat <V6_vmpauhb, int_hexagon_V6_vmpauhb>;
165defm : T_WWR_HVX_gen_pat <V6_vmpauhb_acc, int_hexagon_V6_vmpauhb_acc>;
166defm : T_VVR_HVX_gen_pat <V6_vmpyiwub_acc, int_hexagon_V6_vmpyiwub_acc>;
167defm : T_ZR_HVX_gen_pat <V6_vandnqrt, int_hexagon_V6_vandnqrt>;
168defm : T_VZR_HVX_gen_pat <V6_vandnqrt_acc, int_hexagon_V6_vandnqrt_acc>;
169defm : T_ZV_HVX_gen_pat <V6_vandvqv, int_hexagon_V6_vandvqv>;
170defm : T_ZV_HVX_gen_pat <V6_vandvnqv, int_hexagon_V6_vandvnqv>;
171defm : T_R_HVX_gen_pat <V6_pred_scalar2v2, int_hexagon_V6_pred_scalar2v2>;
172defm : T_R_HVX_gen_pat <V6_lvsplath, int_hexagon_V6_lvsplath>;
173defm : T_R_HVX_gen_pat <V6_lvsplatb, int_hexagon_V6_lvsplatb>;
174defm : T_ZZ_HVX_gen_pat <V6_shuffeqw, int_hexagon_V6_shuffeqw>;
175defm : T_ZZ_HVX_gen_pat <V6_shuffeqh, int_hexagon_V6_shuffeqh>;
176defm : T_VVI_HVX_gen_pat <V6_vlutvvbi, int_hexagon_V6_vlutvvbi>;
177defm : T_VVI_HVX_gen_pat <V6_vlutvwhi, int_hexagon_V6_vlutvwhi>;
178defm : T_VVVI_HVX_gen_pat <V6_vlutvvb_oracci, int_hexagon_V6_vlutvvb_oracci>;
179defm : T_WVVI_HVX_gen_pat <V6_vlutvwh_oracci, int_hexagon_V6_vlutvwh_oracci>;
180