Lines Matching full:src3
172 (ins VR128:$src1, VR128:$src2, VR128:$src3),
174 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
176 (Int VR128:$src1, VR128:$src2, VR128:$src3))]>, XOP, VVVV,
179 (ins VR128:$src1, i128mem:$src2, VR128:$src3),
181 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
184 VR128:$src3))]>, XOP, VVVV, Sched<[sched.Folded, sched.ReadAfterFold]>;
218 (v8i16 VR128:$src3))),
219 (VPMACSWWrr VR128:$src1, VR128:$src2, VR128:$src3)>;
221 (v4i32 VR128:$src3))),
222 (VPMACSDDrr VR128:$src1, VR128:$src2, VR128:$src3)>;
225 (v2i64 VR128:$src3))),
226 (VPMACSDQHrr VR128:$src1, VR128:$src2, VR128:$src3)>;
228 (v2i64 VR128:$src3))),
229 (VPMACSDQLrr VR128:$src1, VR128:$src2, VR128:$src3)>;
231 (v4i32 VR128:$src3))),
232 (VPMADCSWDrr VR128:$src1, VR128:$src2, VR128:$src3)>;
285 (ins VR128:$src1, VR128:$src2, VR128:$src3),
287 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
290 (vt128 VR128:$src3))))]>,
293 (ins VR128:$src1, VR128:$src2, i128mem:$src3),
295 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
298 (vt128 (load addr:$src3)))))]>,
301 (ins VR128:$src1, i128mem:$src2, VR128:$src3),
303 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
306 (vt128 VR128:$src3))))]>,
311 // VR128:$src3
316 (ins VR128:$src1, VR128:$src2, VR128:$src3),
318 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
332 (ins RC:$src1, RC:$src2, RC:$src3),
334 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
335 [(set RC:$dst, (VT (or (and RC:$src3, RC:$src1),
336 (X86andnp RC:$src3, RC:$src2))))]>, XOP, VVVV,
341 (ins RC:$src1, RC:$src2, x86memop:$src3),
343 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
347 (ins RC:$src1, x86memop:$src2, RC:$src3),
349 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
350 [(set RC:$dst, (VT (or (and RC:$src3, RC:$src1),
351 (X86andnp RC:$src3, (load addr:$src2)))))]>,
356 // RC::$src3
361 (ins RC:$src1, RC:$src2, RC:$src3),
363 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
375 def : Pat<(v16i8 (or (and VR128:$src3, VR128:$src1),
376 (X86andnp VR128:$src3, VR128:$src2))),
377 (VPCMOVrrr VR128:$src1, VR128:$src2, VR128:$src3)>;
378 def : Pat<(v8i16 (or (and VR128:$src3, VR128:$src1),
379 (X86andnp VR128:$src3, VR128:$src2))),
380 (VPCMOVrrr VR128:$src1, VR128:$src2, VR128:$src3)>;
381 def : Pat<(v4i32 (or (and VR128:$src3, VR128:$src1),
382 (X86andnp VR128:$src3, VR128:$src2))),
383 (VPCMOVrrr VR128:$src1, VR128:$src2, VR128:$src3)>;
385 def : Pat<(or (and VR128:$src3, VR128:$src1),
386 (X86andnp VR128:$src3, (loadv16i8 addr:$src2))),
387 (VPCMOVrmr VR128:$src1, addr:$src2, VR128:$src3)>;
388 def : Pat<(or (and VR128:$src3, VR128:$src1),
389 (X86andnp VR128:$src3, (loadv8i16 addr:$src2))),
390 (VPCMOVrmr VR128:$src1, addr:$src2, VR128:$src3)>;
391 def : Pat<(or (and VR128:$src3, VR128:$src1),
392 (X86andnp VR128:$src3, (loadv4i32 addr:$src2))),
393 (VPCMOVrmr VR128:$src1, addr:$src2, VR128:$src3)>;
395 def : Pat<(v32i8 (or (and VR256:$src3, VR256:$src1),
396 (X86andnp VR256:$src3, VR256:$src2))),
397 (VPCMOVYrrr VR256:$src1, VR256:$src2, VR256:$src3)>;
398 def : Pat<(v16i16 (or (and VR256:$src3, VR256:$src1),
399 (X86andnp VR256:$src3, VR256:$src2))),
400 (VPCMOVYrrr VR256:$src1, VR256:$src2, VR256:$src3)>;
401 def : Pat<(v8i32 (or (and VR256:$src3, VR256:$src1),
402 (X86andnp VR256:$src3, VR256:$src2))),
403 (VPCMOVYrrr VR256:$src1, VR256:$src2, VR256:$src3)>;
405 def : Pat<(or (and VR256:$src3, VR256:$src1),
406 (X86andnp VR256:$src3, (loadv32i8 addr:$src2))),
407 (VPCMOVYrmr VR256:$src1, addr:$src2, VR256:$src3)>;
408 def : Pat<(or (and VR256:$src3, VR256:$src1),
409 (X86andnp VR256:$src3, (loadv16i16 addr:$src2))),
410 (VPCMOVYrmr VR256:$src1, addr:$src2, VR256:$src3)>;
411 def : Pat<(or (and VR256:$src3, VR256:$src1),
412 (X86andnp VR256:$src3, (loadv8i32 addr:$src2))),
413 (VPCMOVYrmr VR256:$src1, addr:$src2, VR256:$src3)>;
421 (ins RC:$src1, RC:$src2, RC:$src3, u4imm:$src4),
423 "\t{$src4, $src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3, $src4}"),
425 (VT (X86vpermil2 RC:$src1, RC:$src2, RC:$src3, (i8 timm:$src4))))]>,
428 (ins RC:$src1, RC:$src2, intmemop:$src3, u4imm:$src4),
430 "\t{$src4, $src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3, $src4}"),
432 (VT (X86vpermil2 RC:$src1, RC:$src2, (IntLdFrag addr:$src3),
436 (ins RC:$src1, fpmemop:$src2, RC:$src3, u4imm:$src4),
438 "\t{$src4, $src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3, $src4}"),
441 RC:$src3, (i8 timm:$src4))))]>,
445 // RC:$src3
450 (ins RC:$src1, RC:$src2, RC:$src3, u4imm:$src4),
452 "\t{$src4, $src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3, $src4}"),