Lines Matching full:src3
171 def: Pat<(IntID HvxWR:$src1, HvxWR:$src2, IntRegs:$src3),
172 (MI HvxWR:$src1, HvxWR:$src2, IntRegs:$src3)>;
175 IntRegs:$src3),
176 (MI HvxWR:$src1, HvxWR:$src2, IntRegs:$src3)>;
180 def: Pat<(IntID HvxVR:$src1, HvxVR:$src2, IntRegs:$src3),
181 (MI HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>;
184 IntRegs:$src3),
185 (MI HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>;
189 def: Pat<(IntID HvxWR:$src1, HvxVR:$src2, IntRegs:$src3),
190 (MI HvxWR:$src1, HvxVR:$src2, IntRegs:$src3)>;
193 IntRegs:$src3),
194 (MI HvxWR:$src1, HvxVR:$src2, IntRegs:$src3)>;
198 def: Pat<(IntID HvxVR:$src1, HvxWR:$src2, IntRegs:$src3),
199 (MI HvxVR:$src1, HvxWR:$src2, IntRegs:$src3)>;
202 IntRegs:$src3),
203 (MI HvxVR:$src1, HvxWR:$src2, IntRegs:$src3)>;
207 def: Pat<(IntID HvxVR:$src1, HvxVR:$src2, HvxVR:$src3),
208 (MI HvxVR:$src1, HvxVR:$src2, HvxVR:$src3)>;
211 HvxVR:$src3),
212 (MI HvxVR:$src1, HvxVR:$src2, HvxVR:$src3)>;
216 def: Pat<(IntID HvxWR:$src1, HvxVR:$src2, HvxVR:$src3),
217 (MI HvxWR:$src1, HvxVR:$src2, HvxVR:$src3)>;
220 HvxVR:$src3),
221 (MI HvxWR:$src1, HvxVR:$src2, HvxVR:$src3)>;
225 def: Pat<(IntID HvxQR:$src1, HvxVR:$src2, HvxVR:$src3),
226 (MI HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>;
229 HvxVR:$src3),
230 (MI HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>;
234 def: Pat<(IntID HvxVR:$src1, HvxQR:$src2, IntRegs:$src3),
235 (MI HvxVR:$src1, HvxQR:$src2, IntRegs:$src3)>;
238 IntRegs:$src3),
239 (MI HvxVR:$src1, HvxQR:$src2, IntRegs:$src3)>;
244 def: Pat<(IntID HvxQR:$src1, HvxVR:$src2, IntRegs:$src3),
245 (MI HvxQR:$src1, HvxVR:$src2, IntRegs:$src3)>;
248 IntRegs:$src3),
249 (MI HvxQR:$src1, HvxVR:$src2, IntRegs:$src3)>;
253 def: Pat<(IntID HvxVR:$src1, HvxVR:$src2, imm:$src3),
254 (MI HvxVR:$src1, HvxVR:$src2, imm:$src3)>;
257 HvxVR:$src2, imm:$src3),
258 (MI HvxVR:$src1, HvxVR:$src2, imm:$src3)>;
262 def: Pat<(IntID HvxWR:$src1, IntRegs:$src2, imm:$src3),
263 (MI HvxWR:$src1, IntRegs:$src2, imm:$src3)>;
266 IntRegs:$src2, imm:$src3),
267 (MI HvxWR:$src1, IntRegs:$src2, imm:$src3)>;
271 def: Pat<(IntID HvxWR:$src1, HvxWR:$src2, IntRegs:$src3, imm:$src4),
272 (MI HvxWR:$src1, HvxWR:$src2, IntRegs:$src3, imm:$src4)>;
275 IntRegs:$src3, imm:$src4),
276 (MI HvxWR:$src1, HvxWR:$src2, IntRegs:$src3, imm:$src4)>;
280 def: Pat<(IntID HvxVR:$src1, HvxVR:$src2, HvxVR:$src3, IntRegs:$src4),
281 (MI HvxVR:$src1, HvxVR:$src2, HvxVR:$src3, IntRegs:$src4)>;
284 HvxVR:$src3, IntRegs:$src4),
285 (MI HvxVR:$src1, HvxVR:$src2, HvxVR:$src3, IntRegs:$src4)>;
289 def: Pat<(IntID HvxWR:$src1, HvxVR:$src2, HvxVR:$src3, IntRegs:$src4),
290 (MI HvxWR:$src1, HvxVR:$src2, HvxVR:$src3, IntRegs:$src4)>;
293 HvxVR:$src3, IntRegs:$src4),
294 (MI HvxWR:$src1, HvxVR:$src2, HvxVR:$src3, IntRegs:$src4)>;