Home
last modified time | relevance | path

Searched full:polarfire (Results 1 – 20 of 20) sorted by relevance

/linux/drivers/firmware/microchip/
H A DKconfig4 tristate "Microchip PolarFire SoC AUTO UPDATE"
9 Support for reprogramming PolarFire SoC from within Linux, using the
H A Dmpfs-auto-update.c3 * Microchip Polarfire SoC "Auto Update" FPGA reprogramming.
5 * Documentation of this functionality is available in the "PolarFire® FPGA and
6 * PolarFire SoC FPGA Programming" User Guide.
469 MODULE_DESCRIPTION("PolarFire SoC Auto Update FPGA reprogramming");
/linux/Documentation/devicetree/bindings/fpga/
H A Dmicrochip,mpf-spi-fpga-mgr.yaml7 title: Microchip Polarfire FPGA manager.
13 Device Tree Bindings for Microchip Polarfire FPGA Manager using slave SPI to
/linux/Documentation/devicetree/bindings/rtc/
H A Dmicrochip,mpfs-rtc.yaml8 title: Microchip PolarFire Soc (MPFS) RTC
42 on the PolarFire SoC shares it's reference with MTIMER so this will
/linux/drivers/char/hw_random/
H A Dmpfs-rng.c3 * Microchip PolarFire SoC (MPFS) hardware random driver
101 MODULE_DESCRIPTION("PolarFire SoC (MPFS) hardware random driver");
/linux/Documentation/devicetree/bindings/pci/
H A Dmicrochip,pcie-host.yaml18 const: microchip,pcie-host-1.0 # PolarFire
29 fabric and the core complex on PolarFire SoC. The FICs require two clocks,
/linux/drivers/usb/musb/
H A DKconfig116 tristate "Microchip PolarFire SoC platforms"
121 Say Y here to enable support for USB on Microchip's PolarFire SoC.
H A Dmpfs.c3 * PolarFire SoC (MPFS) MUSB Glue Layer
101 * We poll because PolarFire SoC won't expose several OTG-critical in otg_timer()
382 MODULE_DESCRIPTION("PolarFire SoC MUSB Glue Layer");
/linux/drivers/fpga/
H A Dmicrochip-spi.c3 * Microchip Polarfire FPGA programming over slave SPI interface.
379 mgr = devm_fpga_mgr_register(dev, "Microchip Polarfire SPI FPGA Manager", in mpf_probe()
410 MODULE_DESCRIPTION("Microchip Polarfire SPI FPGA Manager");
/linux/drivers/reset/
H A Dreset-mpfs.c3 * PolarFire SoC (MPFS) Peripheral Clock Reset Controller
205 MODULE_DESCRIPTION("Microchip PolarFire SoC Reset Driver");
/linux/drivers/soc/microchip/
H A Dmpfs-control-scb.c40 MODULE_DESCRIPTION("PolarFire SoC control scb driver");
H A Dmpfs-mss-top-sysreg.c46 MODULE_DESCRIPTION("PolarFire SoC mss top sysreg driver");
H A Dmpfs-sys-controller.c3 * Microchip PolarFire SoC (MPFS) system controller driver
/linux/include/soc/microchip/
H A Dmpfs.h4 * Microchip PolarFire SoC (MPFS)
/linux/Documentation/devicetree/bindings/pinctrl/
H A Dmicrochip,mpfs-pinctrl-iomux0.yaml7 title: Microchip PolarFire SoC iomux0
/linux/drivers/clk/microchip/
H A Dclk-mpfs.c3 * PolarFire SoC MSS/core complex clock control
133 * The only two supported reference clock frequencies for the PolarFire SoC are
583 MODULE_DESCRIPTION("Microchip PolarFire SoC Clock Driver");
/linux/drivers/rtc/
H A Drtc-mpfs.c294 MODULE_DESCRIPTION("Real time clock for Microchip Polarfire SoC");
H A DKconfig2125 tristate "Microchip PolarFire SoC built-in RTC"
2129 built-in RTC on Polarfire SoC.
/linux/arch/riscv/boot/dts/microchip/
H A Dmpfs.dtsi10 model = "Microchip PolarFire SoC";
/linux/
H A DMAINTAINERS17541 MICROCHIP POLARFIRE FPGA DRIVERS