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/linux/drivers/soc/microchip/
H A DKconfig2 tristate "Microchip PolarFire SoC (MPFS) system controller support"
6 This driver adds support for the PolarFire SoC (MPFS) system controller.
14 bool "PolarFire SoC (MPFS) syscon drivers"
19 These drivers add support for the syscons on PolarFire SoC (MPFS).
23 If unsure, and on a PolarFire SoC, say y.
H A Dmpfs-control-scb.c38 MODULE_DESCRIPTION("PolarFire SoC control scb driver");
H A Dmpfs-mss-top-sysreg.c44 MODULE_DESCRIPTION("PolarFire SoC mss top sysreg driver");
/linux/Documentation/devicetree/bindings/clock/
H A Dmicrochip,mpfs-clkcfg.yaml7 title: Microchip PolarFire Clock Control Module
13 Microchip PolarFire clock control (CLKCFG) is an integrated clock controller,
52 PolarFire clock IDs.
59 The AHB/AXI peripherals on the PolarFire SoC have reset support, so from
63 PolarFire clock IDs.
H A Dmicrochip,mpfs-ccc.yaml7 title: Microchip PolarFire SoC Fabric Clock Conditioning Circuitry
13 Microchip PolarFire SoC has 4 Clock Conditioning Circuitry blocks. Each of
15 the FPGA. For more information see "PolarFire SoC FPGA Clocking Resources" at:
58 PolarFire clock IDs.
/linux/Documentation/devicetree/bindings/soc/microchip/
H A Dmicrochip,mpfs-mss-top-sysreg.yaml7 title: Microchip PolarFire SoC Microprocessor Subsystem (MSS) sysreg register region
13 An wide assortment of registers that control elements of the MSS on PolarFire
34 The AHB/AXI peripherals on the PolarFire SoC have reset support, so
38 of PolarFire clock/reset IDs.
H A Dmicrochip,mpfs-sys-controller.yaml7 title: Microchip PolarFire SoC (MPFS) MSS (microprocessor subsystem) system controller
13 PolarFire SoC devices include a microcontroller acting as the system controller,
/linux/drivers/clk/microchip/
H A DKconfig7 bool "Clk driver for PolarFire SoC"
14 Supports Clock Configuration for PolarFire SoC
H A Dclk-mpfs.c3 * PolarFire SoC MSS/core complex clock control
133 * The only two supported reference clock frequencies for the PolarFire SoC are
583 MODULE_DESCRIPTION("Microchip PolarFire SoC Clock Driver");
/linux/drivers/firmware/microchip/
H A DKconfig4 tristate "Microchip PolarFire SoC AUTO UPDATE"
9 Support for reprogramming PolarFire SoC from within Linux, using the
H A Dmpfs-auto-update.c3 * Microchip Polarfire SoC "Auto Update" FPGA reprogramming.
5 * Documentation of this functionality is available in the "PolarFire® FPGA and
6 * PolarFire SoC FPGA Programming" User Guide.
467 MODULE_DESCRIPTION("PolarFire SoC Auto Update FPGA reprogramming");
/linux/Documentation/devicetree/bindings/fpga/
H A Dmicrochip,mpf-spi-fpga-mgr.yaml7 title: Microchip Polarfire FPGA manager.
13 Device Tree Bindings for Microchip Polarfire FPGA Manager using slave SPI to
/linux/Documentation/devicetree/bindings/rtc/
H A Dmicrochip,mpfs-rtc.yaml8 title: Microchip PolarFire Soc (MPFS) RTC
42 on the PolarFire SoC shares it's reference with MTIMER so this will
/linux/drivers/char/hw_random/
H A Dmpfs-rng.c3 * Microchip PolarFire SoC (MPFS) hardware random driver
101 MODULE_DESCRIPTION("PolarFire SoC (MPFS) hardware random driver");
/linux/Documentation/devicetree/bindings/pci/
H A Dmicrochip,pcie-host.yaml18 const: microchip,pcie-host-1.0 # PolarFire
29 fabric and the core complex on PolarFire SoC. The FICs require two clocks,
/linux/drivers/usb/musb/
H A DKconfig116 tristate "Microchip PolarFire SoC platforms"
121 Say Y here to enable support for USB on Microchip's PolarFire SoC.
H A Dmpfs.c3 * PolarFire SoC (MPFS) MUSB Glue Layer
101 * We poll because PolarFire SoC won't expose several OTG-critical in otg_timer()
382 MODULE_DESCRIPTION("PolarFire SoC MUSB Glue Layer");
/linux/drivers/reset/
H A Dreset-mpfs.c3 * PolarFire SoC (MPFS) Peripheral Clock Reset Controller
205 MODULE_DESCRIPTION("Microchip PolarFire SoC Reset Driver");
H A DKconfig212 bool "Microchip PolarFire SoC (MPFS) Reset Driver"
218 This driver supports peripheral reset for the Microchip PolarFire SoC
/linux/drivers/fpga/
H A Dmicrochip-spi.c3 * Microchip Polarfire FPGA programming over slave SPI interface.
379 mgr = devm_fpga_mgr_register(dev, "Microchip Polarfire SPI FPGA Manager", in mpf_probe()
410 MODULE_DESCRIPTION("Microchip Polarfire SPI FPGA Manager");
/linux/include/soc/microchip/
H A Dmpfs.h4 * Microchip PolarFire SoC (MPFS)
/linux/Documentation/devicetree/bindings/mailbox/
H A Dmicrochip,mpfs-mailbox.yaml7 title: Microchip PolarFire SoC (MPFS) MSS (microprocessor subsystem) mailbox controller
/linux/Documentation/devicetree/bindings/pinctrl/
H A Dmicrochip,mpfs-pinctrl-iomux0.yaml7 title: Microchip PolarFire SoC iomux0
/linux/arch/riscv/boot/dts/microchip/
H A Dmpfs-sev-kit.dts12 model = "Microchip PolarFire-SoC SEV Kit";
/linux/drivers/pinctrl/
H A DKconfig511 bool "Polarfire SoC pinctrl driver"
517 This selects the pinctrl driver for Microchip Polarfire SoC.

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