1*3ffb5ad2SConor Dooley# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*3ffb5ad2SConor Dooley%YAML 1.2 3*3ffb5ad2SConor Dooley--- 4*3ffb5ad2SConor Dooley$id: http://devicetree.org/schemas/clock/microchip,mpfs-ccc.yaml# 5*3ffb5ad2SConor Dooley$schema: http://devicetree.org/meta-schemas/core.yaml# 6*3ffb5ad2SConor Dooley 7*3ffb5ad2SConor Dooleytitle: Microchip PolarFire SoC Fabric Clock Conditioning Circuitry 8*3ffb5ad2SConor Dooley 9*3ffb5ad2SConor Dooleymaintainers: 10*3ffb5ad2SConor Dooley - Conor Dooley <conor.dooley@microchip.com> 11*3ffb5ad2SConor Dooley 12*3ffb5ad2SConor Dooleydescription: | 13*3ffb5ad2SConor Dooley Microchip PolarFire SoC has 4 Clock Conditioning Circuitry blocks. Each of 14*3ffb5ad2SConor Dooley these blocks contains two PLLs and 2 DLLs & are located in the four corners of 15*3ffb5ad2SConor Dooley the FPGA. For more information see "PolarFire SoC FPGA Clocking Resources" at: 16*3ffb5ad2SConor Dooley https://onlinedocs.microchip.com/pr/GUID-8F0CC4C0-0317-4262-89CA-CE7773ED1931-en-US-1/index.html 17*3ffb5ad2SConor Dooley 18*3ffb5ad2SConor Dooleyproperties: 19*3ffb5ad2SConor Dooley compatible: 20*3ffb5ad2SConor Dooley const: microchip,mpfs-ccc 21*3ffb5ad2SConor Dooley 22*3ffb5ad2SConor Dooley reg: 23*3ffb5ad2SConor Dooley items: 24*3ffb5ad2SConor Dooley - description: PLL0's control registers 25*3ffb5ad2SConor Dooley - description: PLL1's control registers 26*3ffb5ad2SConor Dooley - description: DLL0's control registers 27*3ffb5ad2SConor Dooley - description: DLL1's control registers 28*3ffb5ad2SConor Dooley 29*3ffb5ad2SConor Dooley clocks: 30*3ffb5ad2SConor Dooley description: 31*3ffb5ad2SConor Dooley The CCC PLL's have two input clocks. It is required that even if the input 32*3ffb5ad2SConor Dooley clocks are identical that both are provided. 33*3ffb5ad2SConor Dooley minItems: 2 34*3ffb5ad2SConor Dooley items: 35*3ffb5ad2SConor Dooley - description: PLL0's refclk0 36*3ffb5ad2SConor Dooley - description: PLL0's refclk1 37*3ffb5ad2SConor Dooley - description: PLL1's refclk0 38*3ffb5ad2SConor Dooley - description: PLL1's refclk1 39*3ffb5ad2SConor Dooley - description: DLL0's refclk 40*3ffb5ad2SConor Dooley - description: DLL1's refclk 41*3ffb5ad2SConor Dooley 42*3ffb5ad2SConor Dooley clock-names: 43*3ffb5ad2SConor Dooley minItems: 2 44*3ffb5ad2SConor Dooley items: 45*3ffb5ad2SConor Dooley - const: pll0_ref0 46*3ffb5ad2SConor Dooley - const: pll0_ref1 47*3ffb5ad2SConor Dooley - const: pll1_ref0 48*3ffb5ad2SConor Dooley - const: pll1_ref1 49*3ffb5ad2SConor Dooley - const: dll0_ref 50*3ffb5ad2SConor Dooley - const: dll1_ref 51*3ffb5ad2SConor Dooley 52*3ffb5ad2SConor Dooley '#clock-cells': 53*3ffb5ad2SConor Dooley const: 1 54*3ffb5ad2SConor Dooley description: | 55*3ffb5ad2SConor Dooley The clock consumer should specify the desired clock by having the clock 56*3ffb5ad2SConor Dooley ID in its "clocks" phandle cell. 57*3ffb5ad2SConor Dooley See include/dt-bindings/clock/microchip,mpfs-clock.h for the full list of 58*3ffb5ad2SConor Dooley PolarFire clock IDs. 59*3ffb5ad2SConor Dooley 60*3ffb5ad2SConor Dooleyrequired: 61*3ffb5ad2SConor Dooley - compatible 62*3ffb5ad2SConor Dooley - reg 63*3ffb5ad2SConor Dooley - clocks 64*3ffb5ad2SConor Dooley - clock-names 65*3ffb5ad2SConor Dooley - '#clock-cells' 66*3ffb5ad2SConor Dooley 67*3ffb5ad2SConor DooleyadditionalProperties: false 68*3ffb5ad2SConor Dooley 69*3ffb5ad2SConor Dooleyexamples: 70*3ffb5ad2SConor Dooley - | 71*3ffb5ad2SConor Dooley clock-controller@38100000 { 72*3ffb5ad2SConor Dooley compatible = "microchip,mpfs-ccc"; 73*3ffb5ad2SConor Dooley reg = <0x38010000 0x1000>, <0x38020000 0x1000>, 74*3ffb5ad2SConor Dooley <0x39010000 0x1000>, <0x39020000 0x1000>; 75*3ffb5ad2SConor Dooley #clock-cells = <1>; 76*3ffb5ad2SConor Dooley clocks = <&refclk_ccc>, <&refclk_ccc>, <&refclk_ccc>, <&refclk_ccc>, 77*3ffb5ad2SConor Dooley <&refclk_ccc>, <&refclk_ccc>; 78*3ffb5ad2SConor Dooley clock-names = "pll0_ref0", "pll0_ref1", "pll1_ref0", "pll1_ref1", 79*3ffb5ad2SConor Dooley "dll0_ref", "dll1_ref"; 80*3ffb5ad2SConor Dooley }; 81