1635e5e73SDaire McNamara // SPDX-License-Identifier: GPL-2.0-only
2635e5e73SDaire McNamara /*
3d325268bSConor Dooley * PolarFire SoC MSS/core complex clock control
4d325268bSConor Dooley *
5d325268bSConor Dooley * Copyright (C) 2020-2022 Microchip Technology Inc. All rights reserved.
6635e5e73SDaire McNamara */
7635e5e73SDaire McNamara #include <linux/clk-provider.h>
8635e5e73SDaire McNamara #include <linux/io.h>
9635e5e73SDaire McNamara #include <linux/module.h>
10635e5e73SDaire McNamara #include <linux/platform_device.h>
11635e5e73SDaire McNamara #include <dt-bindings/clock/microchip,mpfs-clock.h>
12b56bae2dSConor Dooley #include <soc/microchip/mpfs.h>
13635e5e73SDaire McNamara
14635e5e73SDaire McNamara /* address offset of control registers */
15445c2da8SConor Dooley #define REG_MSSPLL_REF_CR 0x08u
1666736997SConor Dooley #define REG_MSSPLL_POSTDIV01_CR 0x10u
1766736997SConor Dooley #define REG_MSSPLL_POSTDIV23_CR 0x14u
18445c2da8SConor Dooley #define REG_MSSPLL_SSCG_2_CR 0x2Cu
19635e5e73SDaire McNamara #define REG_CLOCK_CONFIG_CR 0x08u
201c6a7ea3SConor Dooley #define REG_RTC_CLOCK_CR 0x0Cu
21635e5e73SDaire McNamara #define REG_SUBBLK_CLOCK_CR 0x84u
22635e5e73SDaire McNamara #define REG_SUBBLK_RESET_CR 0x88u
23635e5e73SDaire McNamara
24445c2da8SConor Dooley #define MSSPLL_FBDIV_SHIFT 0x00u
25445c2da8SConor Dooley #define MSSPLL_FBDIV_WIDTH 0x0Cu
26445c2da8SConor Dooley #define MSSPLL_REFDIV_SHIFT 0x08u
27445c2da8SConor Dooley #define MSSPLL_REFDIV_WIDTH 0x06u
2866736997SConor Dooley #define MSSPLL_POSTDIV02_SHIFT 0x08u
29b67dae39SConor Dooley #define MSSPLL_POSTDIV13_SHIFT 0x18u
30445c2da8SConor Dooley #define MSSPLL_POSTDIV_WIDTH 0x07u
31445c2da8SConor Dooley #define MSSPLL_FIXED_DIV 4u
32445c2da8SConor Dooley
331afa9480SConor Dooley /*
341afa9480SConor Dooley * This clock ID is defined here, rather than the binding headers, as it is an
351afa9480SConor Dooley * internal clock only, and therefore has no consumers in other peripheral
361afa9480SConor Dooley * blocks.
371afa9480SConor Dooley */
381afa9480SConor Dooley #define CLK_MSSPLL_INTERNAL 38u
391afa9480SConor Dooley
40635e5e73SDaire McNamara struct mpfs_clock_data {
41b56bae2dSConor Dooley struct device *dev;
42635e5e73SDaire McNamara void __iomem *base;
43445c2da8SConor Dooley void __iomem *msspll_base;
44635e5e73SDaire McNamara struct clk_hw_onecell_data hw_data;
45635e5e73SDaire McNamara };
46635e5e73SDaire McNamara
47445c2da8SConor Dooley struct mpfs_msspll_hw_clock {
48445c2da8SConor Dooley void __iomem *base;
491afa9480SConor Dooley struct clk_hw hw;
501afa9480SConor Dooley struct clk_init_data init;
51445c2da8SConor Dooley unsigned int id;
52445c2da8SConor Dooley u32 reg_offset;
53445c2da8SConor Dooley u32 shift;
54445c2da8SConor Dooley u32 width;
55445c2da8SConor Dooley u32 flags;
56445c2da8SConor Dooley };
57445c2da8SConor Dooley
58445c2da8SConor Dooley #define to_mpfs_msspll_clk(_hw) container_of(_hw, struct mpfs_msspll_hw_clock, hw)
59445c2da8SConor Dooley
601afa9480SConor Dooley struct mpfs_msspll_out_hw_clock {
611afa9480SConor Dooley void __iomem *base;
6272151193SConor Dooley struct clk_divider output;
631afa9480SConor Dooley struct clk_init_data init;
641afa9480SConor Dooley unsigned int id;
6566736997SConor Dooley u32 reg_offset;
661afa9480SConor Dooley };
671afa9480SConor Dooley
681afa9480SConor Dooley #define to_mpfs_msspll_out_clk(_hw) container_of(_hw, struct mpfs_msspll_out_hw_clock, hw)
691afa9480SConor Dooley
70635e5e73SDaire McNamara struct mpfs_cfg_hw_clock {
714da2404bSConor Dooley struct clk_divider cfg;
72635e5e73SDaire McNamara struct clk_init_data init;
7352fe6b52SConor Dooley unsigned int id;
7452fe6b52SConor Dooley u32 reg_offset;
75635e5e73SDaire McNamara };
76635e5e73SDaire McNamara
77635e5e73SDaire McNamara struct mpfs_periph_hw_clock {
78d8155697SConor Dooley struct clk_gate periph;
7952fe6b52SConor Dooley unsigned int id;
80635e5e73SDaire McNamara };
81635e5e73SDaire McNamara
82635e5e73SDaire McNamara /*
83635e5e73SDaire McNamara * mpfs_clk_lock prevents anything else from writing to the
84635e5e73SDaire McNamara * mpfs clk block while a software locked register is being written.
85635e5e73SDaire McNamara */
86635e5e73SDaire McNamara static DEFINE_SPINLOCK(mpfs_clk_lock);
87635e5e73SDaire McNamara
88445c2da8SConor Dooley static const struct clk_parent_data mpfs_ext_ref[] = {
89635e5e73SDaire McNamara { .index = 0 },
90635e5e73SDaire McNamara };
91635e5e73SDaire McNamara
92635e5e73SDaire McNamara static const struct clk_div_table mpfs_div_cpu_axi_table[] = {
93635e5e73SDaire McNamara { 0, 1 }, { 1, 2 }, { 2, 4 }, { 3, 8 },
94635e5e73SDaire McNamara { 0, 0 }
95635e5e73SDaire McNamara };
96635e5e73SDaire McNamara
97635e5e73SDaire McNamara static const struct clk_div_table mpfs_div_ahb_table[] = {
98635e5e73SDaire McNamara { 1, 2 }, { 2, 4}, { 3, 8 },
99635e5e73SDaire McNamara { 0, 0 }
100635e5e73SDaire McNamara };
101635e5e73SDaire McNamara
1021c6a7ea3SConor Dooley /*
1031c6a7ea3SConor Dooley * The only two supported reference clock frequencies for the PolarFire SoC are
1041c6a7ea3SConor Dooley * 100 and 125 MHz, as the rtc reference is required to be 1 MHz.
1051c6a7ea3SConor Dooley * It therefore only needs to have divider table entries corresponding to
1061c6a7ea3SConor Dooley * divide by 100 and 125.
1071c6a7ea3SConor Dooley */
1081c6a7ea3SConor Dooley static const struct clk_div_table mpfs_div_rtcref_table[] = {
1091c6a7ea3SConor Dooley { 100, 100 }, { 125, 125 },
1101c6a7ea3SConor Dooley { 0, 0 }
1111c6a7ea3SConor Dooley };
1121c6a7ea3SConor Dooley
1131afa9480SConor Dooley /*
1141afa9480SConor Dooley * MSS PLL internal clock
1151afa9480SConor Dooley */
1161afa9480SConor Dooley
mpfs_clk_msspll_recalc_rate(struct clk_hw * hw,unsigned long prate)117445c2da8SConor Dooley static unsigned long mpfs_clk_msspll_recalc_rate(struct clk_hw *hw, unsigned long prate)
118445c2da8SConor Dooley {
119445c2da8SConor Dooley struct mpfs_msspll_hw_clock *msspll_hw = to_mpfs_msspll_clk(hw);
120445c2da8SConor Dooley void __iomem *mult_addr = msspll_hw->base + msspll_hw->reg_offset;
121445c2da8SConor Dooley void __iomem *ref_div_addr = msspll_hw->base + REG_MSSPLL_REF_CR;
12214016e4aSConor Dooley u32 mult, ref_div;
12314016e4aSConor Dooley
12414016e4aSConor Dooley mult = readl_relaxed(mult_addr) >> MSSPLL_FBDIV_SHIFT;
12514016e4aSConor Dooley mult &= clk_div_mask(MSSPLL_FBDIV_WIDTH);
12614016e4aSConor Dooley ref_div = readl_relaxed(ref_div_addr) >> MSSPLL_REFDIV_SHIFT;
12714016e4aSConor Dooley ref_div &= clk_div_mask(MSSPLL_REFDIV_WIDTH);
12814016e4aSConor Dooley
1291afa9480SConor Dooley return prate * mult / (ref_div * MSSPLL_FIXED_DIV);
13014016e4aSConor Dooley }
13114016e4aSConor Dooley
132445c2da8SConor Dooley static const struct clk_ops mpfs_clk_msspll_ops = {
133445c2da8SConor Dooley .recalc_rate = mpfs_clk_msspll_recalc_rate,
134445c2da8SConor Dooley };
135445c2da8SConor Dooley
136445c2da8SConor Dooley #define CLK_PLL(_id, _name, _parent, _shift, _width, _flags, _offset) { \
137445c2da8SConor Dooley .id = _id, \
1381afa9480SConor Dooley .flags = _flags, \
139445c2da8SConor Dooley .shift = _shift, \
140445c2da8SConor Dooley .width = _width, \
141445c2da8SConor Dooley .reg_offset = _offset, \
142445c2da8SConor Dooley .hw.init = CLK_HW_INIT_PARENTS_DATA(_name, _parent, &mpfs_clk_msspll_ops, 0), \
143445c2da8SConor Dooley }
144445c2da8SConor Dooley
145445c2da8SConor Dooley static struct mpfs_msspll_hw_clock mpfs_msspll_clks[] = {
1461afa9480SConor Dooley CLK_PLL(CLK_MSSPLL_INTERNAL, "clk_msspll_internal", mpfs_ext_ref, MSSPLL_FBDIV_SHIFT,
147445c2da8SConor Dooley MSSPLL_FBDIV_WIDTH, 0, REG_MSSPLL_SSCG_2_CR),
148445c2da8SConor Dooley };
149445c2da8SConor Dooley
mpfs_clk_register_mssplls(struct device * dev,struct mpfs_msspll_hw_clock * msspll_hws,unsigned int num_clks,struct mpfs_clock_data * data)150445c2da8SConor Dooley static int mpfs_clk_register_mssplls(struct device *dev, struct mpfs_msspll_hw_clock *msspll_hws,
151445c2da8SConor Dooley unsigned int num_clks, struct mpfs_clock_data *data)
152445c2da8SConor Dooley {
153445c2da8SConor Dooley unsigned int i;
154445c2da8SConor Dooley int ret;
155445c2da8SConor Dooley
156445c2da8SConor Dooley for (i = 0; i < num_clks; i++) {
157445c2da8SConor Dooley struct mpfs_msspll_hw_clock *msspll_hw = &msspll_hws[i];
158445c2da8SConor Dooley
159e7df7ba0SConor Dooley msspll_hw->base = data->msspll_base;
160e7df7ba0SConor Dooley ret = devm_clk_hw_register(dev, &msspll_hw->hw);
161445c2da8SConor Dooley if (ret)
162445c2da8SConor Dooley return dev_err_probe(dev, ret, "failed to register msspll id: %d\n",
1631afa9480SConor Dooley CLK_MSSPLL_INTERNAL);
164445c2da8SConor Dooley
165445c2da8SConor Dooley data->hw_data.hws[msspll_hw->id] = &msspll_hw->hw;
166445c2da8SConor Dooley }
167445c2da8SConor Dooley
168445c2da8SConor Dooley return 0;
169445c2da8SConor Dooley }
170445c2da8SConor Dooley
171445c2da8SConor Dooley /*
1721afa9480SConor Dooley * MSS PLL output clocks
1731afa9480SConor Dooley */
1741afa9480SConor Dooley
17566736997SConor Dooley #define CLK_PLL_OUT(_id, _name, _parent, _flags, _shift, _width, _offset) { \
1761afa9480SConor Dooley .id = _id, \
17772151193SConor Dooley .output.shift = _shift, \
17872151193SConor Dooley .output.width = _width, \
17972151193SConor Dooley .output.table = NULL, \
18066736997SConor Dooley .reg_offset = _offset, \
18172151193SConor Dooley .output.flags = _flags, \
18272151193SConor Dooley .output.hw.init = CLK_HW_INIT(_name, _parent, &clk_divider_ops, 0), \
18372151193SConor Dooley .output.lock = &mpfs_clk_lock, \
1841afa9480SConor Dooley }
1851afa9480SConor Dooley
1861afa9480SConor Dooley static struct mpfs_msspll_out_hw_clock mpfs_msspll_out_clks[] = {
18772151193SConor Dooley CLK_PLL_OUT(CLK_MSSPLL0, "clk_msspll", "clk_msspll_internal", CLK_DIVIDER_ONE_BASED,
18866736997SConor Dooley MSSPLL_POSTDIV02_SHIFT, MSSPLL_POSTDIV_WIDTH, REG_MSSPLL_POSTDIV01_CR),
18972151193SConor Dooley CLK_PLL_OUT(CLK_MSSPLL1, "clk_msspll1", "clk_msspll_internal", CLK_DIVIDER_ONE_BASED,
190b67dae39SConor Dooley MSSPLL_POSTDIV13_SHIFT, MSSPLL_POSTDIV_WIDTH, REG_MSSPLL_POSTDIV01_CR),
19172151193SConor Dooley CLK_PLL_OUT(CLK_MSSPLL2, "clk_msspll2", "clk_msspll_internal", CLK_DIVIDER_ONE_BASED,
192b67dae39SConor Dooley MSSPLL_POSTDIV02_SHIFT, MSSPLL_POSTDIV_WIDTH, REG_MSSPLL_POSTDIV23_CR),
19372151193SConor Dooley CLK_PLL_OUT(CLK_MSSPLL3, "clk_msspll3", "clk_msspll_internal", CLK_DIVIDER_ONE_BASED,
194b67dae39SConor Dooley MSSPLL_POSTDIV13_SHIFT, MSSPLL_POSTDIV_WIDTH, REG_MSSPLL_POSTDIV23_CR),
1951afa9480SConor Dooley };
1961afa9480SConor Dooley
mpfs_clk_register_msspll_outs(struct device * dev,struct mpfs_msspll_out_hw_clock * msspll_out_hws,unsigned int num_clks,struct mpfs_clock_data * data)1971afa9480SConor Dooley static int mpfs_clk_register_msspll_outs(struct device *dev,
1981afa9480SConor Dooley struct mpfs_msspll_out_hw_clock *msspll_out_hws,
1991afa9480SConor Dooley unsigned int num_clks, struct mpfs_clock_data *data)
2001afa9480SConor Dooley {
2011afa9480SConor Dooley unsigned int i;
2021afa9480SConor Dooley int ret;
2031afa9480SConor Dooley
2041afa9480SConor Dooley for (i = 0; i < num_clks; i++) {
2051afa9480SConor Dooley struct mpfs_msspll_out_hw_clock *msspll_out_hw = &msspll_out_hws[i];
2061afa9480SConor Dooley
20772151193SConor Dooley msspll_out_hw->output.reg = data->msspll_base + msspll_out_hw->reg_offset;
20872151193SConor Dooley ret = devm_clk_hw_register(dev, &msspll_out_hw->output.hw);
2091afa9480SConor Dooley if (ret)
2101afa9480SConor Dooley return dev_err_probe(dev, ret, "failed to register msspll out id: %d\n",
2111afa9480SConor Dooley msspll_out_hw->id);
2121afa9480SConor Dooley
21372151193SConor Dooley data->hw_data.hws[msspll_out_hw->id] = &msspll_out_hw->output.hw;
2141afa9480SConor Dooley }
2151afa9480SConor Dooley
2161afa9480SConor Dooley return 0;
2171afa9480SConor Dooley }
2181afa9480SConor Dooley
2191afa9480SConor Dooley /*
220445c2da8SConor Dooley * "CFG" clocks
221445c2da8SConor Dooley */
222445c2da8SConor Dooley
223445c2da8SConor Dooley #define CLK_CFG(_id, _name, _parent, _shift, _width, _table, _flags, _offset) { \
22452fe6b52SConor Dooley .id = _id, \
225635e5e73SDaire McNamara .cfg.shift = _shift, \
226635e5e73SDaire McNamara .cfg.width = _width, \
227635e5e73SDaire McNamara .cfg.table = _table, \
22852fe6b52SConor Dooley .reg_offset = _offset, \
229445c2da8SConor Dooley .cfg.flags = _flags, \
2304da2404bSConor Dooley .cfg.hw.init = CLK_HW_INIT(_name, _parent, &clk_divider_ops, 0), \
2314da2404bSConor Dooley .cfg.lock = &mpfs_clk_lock, \
232635e5e73SDaire McNamara }
233635e5e73SDaire McNamara
2345da39ac5SConor Dooley #define CLK_CPU_OFFSET 0u
2355da39ac5SConor Dooley #define CLK_AXI_OFFSET 1u
2365da39ac5SConor Dooley #define CLK_AHB_OFFSET 2u
2375da39ac5SConor Dooley #define CLK_RTCREF_OFFSET 3u
2385da39ac5SConor Dooley
239635e5e73SDaire McNamara static struct mpfs_cfg_hw_clock mpfs_cfg_clks[] = {
240445c2da8SConor Dooley CLK_CFG(CLK_CPU, "clk_cpu", "clk_msspll", 0, 2, mpfs_div_cpu_axi_table, 0,
241445c2da8SConor Dooley REG_CLOCK_CONFIG_CR),
242445c2da8SConor Dooley CLK_CFG(CLK_AXI, "clk_axi", "clk_msspll", 2, 2, mpfs_div_cpu_axi_table, 0,
243445c2da8SConor Dooley REG_CLOCK_CONFIG_CR),
244445c2da8SConor Dooley CLK_CFG(CLK_AHB, "clk_ahb", "clk_msspll", 4, 2, mpfs_div_ahb_table, 0,
245445c2da8SConor Dooley REG_CLOCK_CONFIG_CR),
2461c6a7ea3SConor Dooley {
24752fe6b52SConor Dooley .id = CLK_RTCREF,
2481c6a7ea3SConor Dooley .cfg.shift = 0,
2491c6a7ea3SConor Dooley .cfg.width = 12,
2501c6a7ea3SConor Dooley .cfg.table = mpfs_div_rtcref_table,
25152fe6b52SConor Dooley .reg_offset = REG_RTC_CLOCK_CR,
2521c6a7ea3SConor Dooley .cfg.flags = CLK_DIVIDER_ONE_BASED,
2534da2404bSConor Dooley .cfg.hw.init =
2544da2404bSConor Dooley CLK_HW_INIT_PARENTS_DATA("clk_rtcref", mpfs_ext_ref, &clk_divider_ops, 0),
2551c6a7ea3SConor Dooley }
256635e5e73SDaire McNamara };
257635e5e73SDaire McNamara
mpfs_clk_register_cfgs(struct device * dev,struct mpfs_cfg_hw_clock * cfg_hws,unsigned int num_clks,struct mpfs_clock_data * data)258635e5e73SDaire McNamara static int mpfs_clk_register_cfgs(struct device *dev, struct mpfs_cfg_hw_clock *cfg_hws,
259635e5e73SDaire McNamara unsigned int num_clks, struct mpfs_clock_data *data)
260635e5e73SDaire McNamara {
261635e5e73SDaire McNamara unsigned int i, id;
262635e5e73SDaire McNamara int ret;
263635e5e73SDaire McNamara
264635e5e73SDaire McNamara for (i = 0; i < num_clks; i++) {
265635e5e73SDaire McNamara struct mpfs_cfg_hw_clock *cfg_hw = &cfg_hws[i];
266635e5e73SDaire McNamara
267e7df7ba0SConor Dooley cfg_hw->cfg.reg = data->base + cfg_hw->reg_offset;
2684da2404bSConor Dooley ret = devm_clk_hw_register(dev, &cfg_hw->cfg.hw);
269635e5e73SDaire McNamara if (ret)
270635e5e73SDaire McNamara return dev_err_probe(dev, ret, "failed to register clock id: %d\n",
27152fe6b52SConor Dooley cfg_hw->id);
272635e5e73SDaire McNamara
27352fe6b52SConor Dooley id = cfg_hw->id;
2744da2404bSConor Dooley data->hw_data.hws[id] = &cfg_hw->cfg.hw;
275635e5e73SDaire McNamara }
276635e5e73SDaire McNamara
277635e5e73SDaire McNamara return 0;
278635e5e73SDaire McNamara }
279635e5e73SDaire McNamara
280445c2da8SConor Dooley /*
281445c2da8SConor Dooley * peripheral clocks - devices connected to axi or ahb buses.
282445c2da8SConor Dooley */
283445c2da8SConor Dooley
284635e5e73SDaire McNamara #define CLK_PERIPH(_id, _name, _parent, _shift, _flags) { \
28552fe6b52SConor Dooley .id = _id, \
286d8155697SConor Dooley .periph.bit_idx = _shift, \
287d8155697SConor Dooley .periph.hw.init = CLK_HW_INIT_HW(_name, _parent, &clk_gate_ops, \
288635e5e73SDaire McNamara _flags), \
289d8155697SConor Dooley .periph.lock = &mpfs_clk_lock, \
290635e5e73SDaire McNamara }
291635e5e73SDaire McNamara
2924da2404bSConor Dooley #define PARENT_CLK(PARENT) (&mpfs_cfg_clks[CLK_##PARENT##_OFFSET].cfg.hw)
293635e5e73SDaire McNamara
294635e5e73SDaire McNamara /*
295635e5e73SDaire McNamara * Critical clocks:
296635e5e73SDaire McNamara * - CLK_ENVM: reserved by hart software services (hss) superloop monitor/m mode interrupt
297635e5e73SDaire McNamara * trap handler
298635e5e73SDaire McNamara * - CLK_MMUART0: reserved by the hss
299635e5e73SDaire McNamara * - CLK_DDRC: provides clock to the ddr subsystem
30005d27090SConor Dooley * - CLK_RTC: the onboard RTC's AHB bus clock must be kept running as the rtc will stop
30105d27090SConor Dooley * if the AHB interface clock is disabled
302a2438f82SConor Dooley * - CLK_FICx: these provide the processor side clocks to the "FIC" (Fabric InterConnect)
303a2438f82SConor Dooley * clock domain crossers which provide the interface to the FPGA fabric. Disabling them
304a2438f82SConor Dooley * causes the FPGA fabric to go into reset.
305a2438f82SConor Dooley * - CLK_ATHENA: The athena clock is FIC4, which is reserved for the Athena TeraFire.
306635e5e73SDaire McNamara */
307635e5e73SDaire McNamara
308635e5e73SDaire McNamara static struct mpfs_periph_hw_clock mpfs_periph_clks[] = {
309635e5e73SDaire McNamara CLK_PERIPH(CLK_ENVM, "clk_periph_envm", PARENT_CLK(AHB), 0, CLK_IS_CRITICAL),
310635e5e73SDaire McNamara CLK_PERIPH(CLK_MAC0, "clk_periph_mac0", PARENT_CLK(AHB), 1, 0),
311635e5e73SDaire McNamara CLK_PERIPH(CLK_MAC1, "clk_periph_mac1", PARENT_CLK(AHB), 2, 0),
312635e5e73SDaire McNamara CLK_PERIPH(CLK_MMC, "clk_periph_mmc", PARENT_CLK(AHB), 3, 0),
3131c6a7ea3SConor Dooley CLK_PERIPH(CLK_TIMER, "clk_periph_timer", PARENT_CLK(RTCREF), 4, 0),
314635e5e73SDaire McNamara CLK_PERIPH(CLK_MMUART0, "clk_periph_mmuart0", PARENT_CLK(AHB), 5, CLK_IS_CRITICAL),
315635e5e73SDaire McNamara CLK_PERIPH(CLK_MMUART1, "clk_periph_mmuart1", PARENT_CLK(AHB), 6, 0),
316635e5e73SDaire McNamara CLK_PERIPH(CLK_MMUART2, "clk_periph_mmuart2", PARENT_CLK(AHB), 7, 0),
317635e5e73SDaire McNamara CLK_PERIPH(CLK_MMUART3, "clk_periph_mmuart3", PARENT_CLK(AHB), 8, 0),
318635e5e73SDaire McNamara CLK_PERIPH(CLK_MMUART4, "clk_periph_mmuart4", PARENT_CLK(AHB), 9, 0),
319635e5e73SDaire McNamara CLK_PERIPH(CLK_SPI0, "clk_periph_spi0", PARENT_CLK(AHB), 10, 0),
320635e5e73SDaire McNamara CLK_PERIPH(CLK_SPI1, "clk_periph_spi1", PARENT_CLK(AHB), 11, 0),
321635e5e73SDaire McNamara CLK_PERIPH(CLK_I2C0, "clk_periph_i2c0", PARENT_CLK(AHB), 12, 0),
322635e5e73SDaire McNamara CLK_PERIPH(CLK_I2C1, "clk_periph_i2c1", PARENT_CLK(AHB), 13, 0),
323635e5e73SDaire McNamara CLK_PERIPH(CLK_CAN0, "clk_periph_can0", PARENT_CLK(AHB), 14, 0),
324635e5e73SDaire McNamara CLK_PERIPH(CLK_CAN1, "clk_periph_can1", PARENT_CLK(AHB), 15, 0),
325635e5e73SDaire McNamara CLK_PERIPH(CLK_USB, "clk_periph_usb", PARENT_CLK(AHB), 16, 0),
32605d27090SConor Dooley CLK_PERIPH(CLK_RTC, "clk_periph_rtc", PARENT_CLK(AHB), 18, CLK_IS_CRITICAL),
327635e5e73SDaire McNamara CLK_PERIPH(CLK_QSPI, "clk_periph_qspi", PARENT_CLK(AHB), 19, 0),
328635e5e73SDaire McNamara CLK_PERIPH(CLK_GPIO0, "clk_periph_gpio0", PARENT_CLK(AHB), 20, 0),
329635e5e73SDaire McNamara CLK_PERIPH(CLK_GPIO1, "clk_periph_gpio1", PARENT_CLK(AHB), 21, 0),
330635e5e73SDaire McNamara CLK_PERIPH(CLK_GPIO2, "clk_periph_gpio2", PARENT_CLK(AHB), 22, 0),
331635e5e73SDaire McNamara CLK_PERIPH(CLK_DDRC, "clk_periph_ddrc", PARENT_CLK(AHB), 23, CLK_IS_CRITICAL),
3328f9fb2abSConor Dooley CLK_PERIPH(CLK_FIC0, "clk_periph_fic0", PARENT_CLK(AXI), 24, CLK_IS_CRITICAL),
3338f9fb2abSConor Dooley CLK_PERIPH(CLK_FIC1, "clk_periph_fic1", PARENT_CLK(AXI), 25, CLK_IS_CRITICAL),
3348f9fb2abSConor Dooley CLK_PERIPH(CLK_FIC2, "clk_periph_fic2", PARENT_CLK(AXI), 26, CLK_IS_CRITICAL),
3358f9fb2abSConor Dooley CLK_PERIPH(CLK_FIC3, "clk_periph_fic3", PARENT_CLK(AXI), 27, CLK_IS_CRITICAL),
336a2438f82SConor Dooley CLK_PERIPH(CLK_ATHENA, "clk_periph_athena", PARENT_CLK(AXI), 28, CLK_IS_CRITICAL),
337635e5e73SDaire McNamara CLK_PERIPH(CLK_CFM, "clk_periph_cfm", PARENT_CLK(AHB), 29, 0),
338635e5e73SDaire McNamara };
339635e5e73SDaire McNamara
mpfs_clk_register_periphs(struct device * dev,struct mpfs_periph_hw_clock * periph_hws,int num_clks,struct mpfs_clock_data * data)340635e5e73SDaire McNamara static int mpfs_clk_register_periphs(struct device *dev, struct mpfs_periph_hw_clock *periph_hws,
341635e5e73SDaire McNamara int num_clks, struct mpfs_clock_data *data)
342635e5e73SDaire McNamara {
343635e5e73SDaire McNamara unsigned int i, id;
344635e5e73SDaire McNamara int ret;
345635e5e73SDaire McNamara
346635e5e73SDaire McNamara for (i = 0; i < num_clks; i++) {
347635e5e73SDaire McNamara struct mpfs_periph_hw_clock *periph_hw = &periph_hws[i];
348635e5e73SDaire McNamara
349e7df7ba0SConor Dooley periph_hw->periph.reg = data->base + REG_SUBBLK_CLOCK_CR;
350d8155697SConor Dooley ret = devm_clk_hw_register(dev, &periph_hw->periph.hw);
351635e5e73SDaire McNamara if (ret)
352635e5e73SDaire McNamara return dev_err_probe(dev, ret, "failed to register clock id: %d\n",
35352fe6b52SConor Dooley periph_hw->id);
354635e5e73SDaire McNamara
35552fe6b52SConor Dooley id = periph_hws[i].id;
356d8155697SConor Dooley data->hw_data.hws[id] = &periph_hw->periph.hw;
357635e5e73SDaire McNamara }
358635e5e73SDaire McNamara
359635e5e73SDaire McNamara return 0;
360635e5e73SDaire McNamara }
361635e5e73SDaire McNamara
mpfs_clk_probe(struct platform_device * pdev)362635e5e73SDaire McNamara static int mpfs_clk_probe(struct platform_device *pdev)
363635e5e73SDaire McNamara {
364635e5e73SDaire McNamara struct device *dev = &pdev->dev;
365635e5e73SDaire McNamara struct mpfs_clock_data *clk_data;
366635e5e73SDaire McNamara unsigned int num_clks;
367635e5e73SDaire McNamara int ret;
368635e5e73SDaire McNamara
369445c2da8SConor Dooley /* CLK_RESERVED is not part of clock arrays, so add 1 */
3701afa9480SConor Dooley num_clks = ARRAY_SIZE(mpfs_msspll_clks) + ARRAY_SIZE(mpfs_msspll_out_clks)
3711afa9480SConor Dooley + ARRAY_SIZE(mpfs_cfg_clks) + ARRAY_SIZE(mpfs_periph_clks) + 1;
372635e5e73SDaire McNamara
373635e5e73SDaire McNamara clk_data = devm_kzalloc(dev, struct_size(clk_data, hw_data.hws, num_clks), GFP_KERNEL);
374635e5e73SDaire McNamara if (!clk_data)
375635e5e73SDaire McNamara return -ENOMEM;
376635e5e73SDaire McNamara
377635e5e73SDaire McNamara clk_data->base = devm_platform_ioremap_resource(pdev, 0);
378635e5e73SDaire McNamara if (IS_ERR(clk_data->base))
379635e5e73SDaire McNamara return PTR_ERR(clk_data->base);
380635e5e73SDaire McNamara
381445c2da8SConor Dooley clk_data->msspll_base = devm_platform_ioremap_resource(pdev, 1);
382445c2da8SConor Dooley if (IS_ERR(clk_data->msspll_base))
383445c2da8SConor Dooley return PTR_ERR(clk_data->msspll_base);
384445c2da8SConor Dooley
385635e5e73SDaire McNamara clk_data->hw_data.num = num_clks;
386b56bae2dSConor Dooley clk_data->dev = dev;
387b56bae2dSConor Dooley dev_set_drvdata(dev, clk_data);
388635e5e73SDaire McNamara
389445c2da8SConor Dooley ret = mpfs_clk_register_mssplls(dev, mpfs_msspll_clks, ARRAY_SIZE(mpfs_msspll_clks),
390445c2da8SConor Dooley clk_data);
391445c2da8SConor Dooley if (ret)
392445c2da8SConor Dooley return ret;
393445c2da8SConor Dooley
3941afa9480SConor Dooley ret = mpfs_clk_register_msspll_outs(dev, mpfs_msspll_out_clks,
3951afa9480SConor Dooley ARRAY_SIZE(mpfs_msspll_out_clks),
3961afa9480SConor Dooley clk_data);
3971afa9480SConor Dooley if (ret)
3981afa9480SConor Dooley return ret;
3991afa9480SConor Dooley
400635e5e73SDaire McNamara ret = mpfs_clk_register_cfgs(dev, mpfs_cfg_clks, ARRAY_SIZE(mpfs_cfg_clks), clk_data);
401635e5e73SDaire McNamara if (ret)
402635e5e73SDaire McNamara return ret;
403635e5e73SDaire McNamara
404635e5e73SDaire McNamara ret = mpfs_clk_register_periphs(dev, mpfs_periph_clks, ARRAY_SIZE(mpfs_periph_clks),
405635e5e73SDaire McNamara clk_data);
406635e5e73SDaire McNamara if (ret)
407635e5e73SDaire McNamara return ret;
408635e5e73SDaire McNamara
409635e5e73SDaire McNamara ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, &clk_data->hw_data);
410635e5e73SDaire McNamara if (ret)
411635e5e73SDaire McNamara return ret;
412635e5e73SDaire McNamara
413*098c290aSConor Dooley return mpfs_reset_controller_register(dev, clk_data->base + REG_SUBBLK_RESET_CR);
414635e5e73SDaire McNamara }
415635e5e73SDaire McNamara
416635e5e73SDaire McNamara static const struct of_device_id mpfs_clk_of_match_table[] = {
417635e5e73SDaire McNamara { .compatible = "microchip,mpfs-clkcfg", },
418635e5e73SDaire McNamara {}
419635e5e73SDaire McNamara };
420b56bae2dSConor Dooley MODULE_DEVICE_TABLE(of, mpfs_clk_of_match_table);
421635e5e73SDaire McNamara
422635e5e73SDaire McNamara static struct platform_driver mpfs_clk_driver = {
423635e5e73SDaire McNamara .probe = mpfs_clk_probe,
424635e5e73SDaire McNamara .driver = {
425635e5e73SDaire McNamara .name = "microchip-mpfs-clkcfg",
426635e5e73SDaire McNamara .of_match_table = mpfs_clk_of_match_table,
427635e5e73SDaire McNamara },
428635e5e73SDaire McNamara };
429635e5e73SDaire McNamara
clk_mpfs_init(void)430635e5e73SDaire McNamara static int __init clk_mpfs_init(void)
431635e5e73SDaire McNamara {
432635e5e73SDaire McNamara return platform_driver_register(&mpfs_clk_driver);
433635e5e73SDaire McNamara }
434635e5e73SDaire McNamara core_initcall(clk_mpfs_init);
435635e5e73SDaire McNamara
clk_mpfs_exit(void)436635e5e73SDaire McNamara static void __exit clk_mpfs_exit(void)
437635e5e73SDaire McNamara {
438635e5e73SDaire McNamara platform_driver_unregister(&mpfs_clk_driver);
439635e5e73SDaire McNamara }
440635e5e73SDaire McNamara module_exit(clk_mpfs_exit);
441635e5e73SDaire McNamara
442635e5e73SDaire McNamara MODULE_DESCRIPTION("Microchip PolarFire SoC Clock Driver");
443d325268bSConor Dooley MODULE_AUTHOR("Padmarao Begari <padmarao.begari@microchip.com>");
444d325268bSConor Dooley MODULE_AUTHOR("Daire McNamara <daire.mcnamara@microchip.com>");
445d325268bSConor Dooley MODULE_AUTHOR("Conor Dooley <conor.dooley@microchip.com>");
446*098c290aSConor Dooley MODULE_IMPORT_NS(MCHP_CLK_MPFS);
447