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/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonConstExtenders.cpp1 //===- HexagonConstExtenders.cpp ------------------------------------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
28 #define DEBUG_TYPE "hexagon-cext-opt"
33 "hexagon-cext-threshold", cl::init(3), cl::Hidden,
37 ReplaceLimit("hexagon-cext-limit", cl::init(0), cl::Hidden,
45 static int32_t adjustUp(int32_t V, uint8_t A, uint8_t O) { in adjustUp() argument
47 int32_t U = (V & -A) + O; in adjustUp()
48 return U >= V ? U : U+A; in adjustUp()
51 static int32_t adjustDown(int32_t V, uint8_t A, uint8_t O) { in adjustDown() argument
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H A DHexagonMachineFunctionInfo.h1 //=- HexagonMachineFunctionInfo.h - Hexagon machine function info -*- C++ -*-=//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
24 /// Hexagon target-specific information for each MachineFunction.
26 // SRetReturnReg - Some subtargets require that sret lowering includes
30 Register StackAlignBaseReg = 0; // Aligned-stack base register
54 void setVarArgsFrameIndex(int v) { VarArgsFrameIndex = v; } in setVarArgsFrameIndex() argument
57 void setRegSavedAreaStartFrameIndex(int v) { RegSavedAreaStartFrameIndex = v;} in setRegSavedAreaStartFrameIndex() argument
60 void setFirstNamedArgFrameIndex(int v) { FirstNamedArgFrameIndex = v; } in setFirstNamedArgFrameIndex() argument
63 void setLastNamedArgFrameIndex(int v) { LastNamedArgFrameIndex = v; } in setLastNamedArgFrameIndex() argument
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H A DHexagonIntrinsics.td1 //===-- HexagonIntrinsics.td - Instruction intrinsics ------*- tablegen -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // These intrinsic patterns are not auto-generated.
11 class T_R_pat <InstHexagon MI, Intrinsic IntID>
13 (MI I32:$Rs)>;
15 class T_RR_pat <InstHexagon MI, Intrinsic IntID>
17 (MI I32:$Rs, I32:$Rt)>;
19 class T_RP_pat <InstHexagon MI, Intrinsic IntID>
21 (MI I32:$Rs, I64:$Rt)>;
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H A DHexagonBitSimplify.cpp1 //===- HexagonBitSimplify.cpp ---------------------------------------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
52 static cl::opt<bool> PreserveTiedOps("hexbit-keep-tied", cl::Hidden,
54 static cl::opt<bool> GenExtract("hexbit-extract", cl::Hidden,
56 static cl::opt<bool> GenBitSplit("hexbit-bitsplit", cl::Hidden,
59 static cl::opt<unsigned> MaxExtract("hexbit-max-extract", cl::Hidden,
62 static cl::opt<unsigned> MaxBitSplit("hexbit-max-bitsplit", cl::Hidden,
66 static cl::opt<unsigned> RegisterSetLimit("hexbit-registerset-limit",
162 // A.test(B) <=> A-B != {} in includes()
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H A DHexagonConstPropagation.cpp1 //===- HexagonConstPropagation.cpp ---------
684 visitNonBranch(const MachineInstr & MI) visitNonBranch() argument
740 const MachineInstr &MI = *It; visitBranchesFrom() local
832 const MachineInstr &MI = *I; computeBlockSuccessors() local
1630 int64_t V = A1.getSExtValue(); evaluateSEXTi() local
1773 int64_t V = A1.getZExtValue(); evaluateEXTRACTi() local
1924 evaluate(const MachineInstr & MI,const CellMap & Inputs,CellMap & Outputs) evaluate() argument
1990 int64_t V = MI.getOperand(1).getImm(); evaluate() local
2327 rewrite(MachineInstr & MI,const CellMap & Inputs) rewrite() argument
2509 replaceWithNop(MachineInstr & MI) replaceWithNop() argument
2552 evaluateHexCompare(const MachineInstr & MI,const CellMap & Inputs,CellMap & Outputs) evaluateHexCompare() argument
2627 evaluateHexLogical(const MachineInstr & MI,const CellMap & Inputs,CellMap & Outputs) evaluateHexLogical() argument
2674 evaluateHexCondMove(const MachineInstr & MI,const CellMap & Inputs,CellMap & Outputs) evaluateHexCondMove() argument
2696 int64_t V = ValOp.getImm(); evaluateHexCondMove() local
2717 evaluateHexExt(const MachineInstr & MI,const CellMap & Inputs,CellMap & Outputs) evaluateHexExt() argument
2761 evaluateHexVector1(const MachineInstr & MI,const CellMap & Inputs,CellMap & Outputs) evaluateHexVector1() argument
2790 rewriteHexConstDefs(MachineInstr & MI,const CellMap & Inputs,bool & AllDefs) rewriteHexConstDefs() argument
2901 int64_t V = A.getSExtValue(); rewriteHexConstDefs() local
2959 rewriteHexConstUses(MachineInstr & MI,const CellMap & Inputs) rewriteHexConstUses() argument
3019 int64_t V = A.getSExtValue(); rewriteHexConstUses() local
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H A DRDFDeadCode.cpp1 //===--- RDFDeadCode.cpp --------------------------------------------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // RDF-based generic dead code elimination.
35 T V = Queue.front(); in pop_front() local
37 Set.erase(V); in pop_front()
38 return V; in pop_front()
40 void push_back(T V) { in push_back()
41 if (Set.count(V)) in push_back()
43 Queue.push(V); in push_back()
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H A DHexagonPatterns.td1 //===- HexagonPatterns.td - Selection Patterns for Hexagon -*- tablegen -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
49 // 6. The v4 vector instructions (64-bit) are treated as core instructions,
51 // 7. When adding a pattern for an instruction with a constant-extendable
56 // --(0) Definitions -----------------------------------------------------
115 def ssat: PatFrag<(ops node:$V, node:$Ty), (HexagonSSAT node:$V, node:$Ty)>;
116 def usat: PatFrag<(ops node:$V, node:$Ty), (HexagonUSAT node:$V, node:$Ty)>;
119 // 64-bit value.
128 uint32_t V = N->getZExtValue();
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H A DBitTracker.cpp1 //===- BitTracker.cpp -----------------------------------------------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // SSA-based bit propagation.
16 // cannot be a copy of yet another bit---such chains are not allowed).
31 // The tracker implements the Wegman-Zadeck algorithm, originally developed
32 // for SSA-based constant propagation. Each register is represented as
33 // a sequence of bits, with the convention that bit 0 is the least signi-
38 // The intended usage of the bit tracker is to create a target-specific
53 // The code below is intended to be fully target-independent.
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/freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/MCTargetDesc/
H A DCSKYInstPrinter.cpp1 //===-- CSKYInstPrinter.cpp - Convert CSKY MCInst to asm syntax ---------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
32 #define DEBUG_TYPE "csky-asm-printer"
34 // Include the auto-generated portion of the assembly writer.
39 NoAliases("csky-no-aliases",
44 ArchRegNames("csky-arch-reg-names",
49 // The command-line flags above are used by llvm-mc and llc. They can be used by
50 // `llvm-objdump`, but we override their values here to handle options passed to
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H A DCSKYMCCodeEmitter.cpp1 //===-- CSKYMCCodeEmitter.cpp - CSKY Code Emitter interface -------
30 getOImmOpValue(const MCInst & MI,unsigned Idx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getOImmOpValue() argument
39 getImmOpValueIDLY(const MCInst & MI,unsigned Idx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getImmOpValueIDLY() argument
45 auto V = (MO.getImm() <= 3) ? 4 : MO.getImm(); getImmOpValueIDLY() local
50 getImmOpValueMSBSize(const MCInst & MI,unsigned Idx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getImmOpValueMSBSize() argument
70 expandJBTF(const MCInst & MI,raw_ostream & OS,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const expandJBTF() argument
96 expandNEG(const MCInst & MI,raw_ostream & OS,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const expandNEG() argument
118 expandRSUBI(const MCInst & MI,raw_ostream & OS,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const expandRSUBI() argument
140 encodeInstruction(const MCInst & MI,raw_ostream & OS,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const encodeInstruction() argument
225 auto V = 1 << MI.getOperand(1).getImm(); encodeInstruction() local
245 getMachineOpValue(const MCInst & MI,const MCOperand & MO,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getMachineOpValue() argument
259 getRegSeqImmOpValue(const MCInst & MI,unsigned Idx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getRegSeqImmOpValue() argument
275 getRegisterSeqOpValue(const MCInst & MI,unsigned Op,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getRegisterSeqOpValue() argument
288 getImmJMPIX(const MCInst & MI,unsigned Idx,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getImmJMPIX() argument
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/freebsd/usr.sbin/ppp/
H A Ddeflate.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
53 #define DEFLATE_CHUNK_LEN (1536 - sizeof(struct mbuf))
56 DeflateResetOutput(void *v) in DeflateResetOutput() argument
58 struct deflate_state *state = (struct deflate_state *)v; in DeflateResetOutput()
60 state->seqno = 0; in DeflateResetOutput()
61 state->uncomp_rec = 0; in DeflateResetOutput()
62 deflateReset(&state->cx); in DeflateResetOutput()
69 DeflateOutput(void *v, struct ccp *ccp, struct link *l __unused, in DeflateOutput() argument
72 struct deflate_state *state = (struct deflate_state *)v; in DeflateOutput()
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/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVVectorPeephole.cpp1 //===- RISCVVectorPeephole.cpp - MI Vector Pseudo Peepholes ---------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
12 // Currently it converts vmerge.vvm to vmv.v.v
14 // ->
19 // ->
25 // ->
26 // PseudoVADD_V_V %passthru, %a, %b, -1, sew, policy
28 //===----------------------------------------------------------------------===//
40 #define DEBUG_TYPE "riscv-vector-peephole"
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H A DRISCVInsertReadWriteCSR.cpp1 //===-- RISCVInsertReadWriteCSR.cpp - Insert Read/Write of RISC-V CSR -----===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
8 // This file implements the machine function pass to insert read/write of CSR-s
9 // of the RISC-V instructions.
12 // -Writing and saving frm before an RVV floating-point instruction with a
15 //===----------------------------------------------------------------------===//
23 #define DEBUG_TYPE "riscv-insert-read-write-csr"
24 #define RISCV_INSERT_READ_WRITE_CSR_NAME "RISC-V Insert Read/Write CSR Pass"
27 DisableFRMInsertOpt("riscv-disable-frm-insert-opt", cl::init(false),
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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DScheduleDAGInstrs.cpp1 //===---- ScheduleDAGInstrs.cpp - MachineInstr Rescheduling ---------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
10 /// re-scheduling of MachineInstrs.
12 //===----------------------------------------------------------------------===//
40 #include "llvm/Config/llvm-config.h"
62 #define DEBUG_TYPE "machine-scheduler"
65 EnableAASchedMI("enable-aa-sched-mi", cl::Hidden,
66 cl::desc("Enable use of AA during MI DAG construction"));
68 static cl::opt<bool> UseTBAA("use-tbaa-in-sched-mi", cl::Hidden,
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/freebsd/contrib/llvm-project/llvm/lib/Target/SPIRV/
H A DSPIRVModuleAnalysis.cpp1 //===- SPIRVModuleAnalysis.cpp - analysis of global instrs & regs - C++ -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
31 #define DEBUG_TYPE "spirv-module-analysis"
34 SPVDumpDeps("spv-dump-deps",
35 cl::desc("Dump MIR with SPIR-V dependencies info"),
39 AvoidCapabilities("avoid-spirv-capabilities",
40 cl::desc("SPIR-V capabilities to avoid if there are "
44 "SPIR-V Shader capability")));
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H A DSPIRVAsmPrinter.cpp1 //===-- SPIRVAsmPrinter.cpp - SPIR-V LLVM assembly writer ------*- C++ -*--===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
10 // of machine-dependent LLVM code to the SPIR-V assembly language.
12 //===----------------------------------------------------------------------===//
43 #define DEBUG_TYPE "asm-printer"
58 void printOperand(const MachineInstr *MI, int OpNum, raw_ostream &O);
59 bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
63 void outputInstruction(const MachineInstr *MI);
82 void emitInstruction(const MachineInstr *MI) override;
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H A DSPIRVISelLowering.cpp1 //===- SPIRVISelLowering.cpp - SPIR-V DAG Lowering Impl ---------*- C++ -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
24 #define DEBUG_TYPE "spirv-lower"
69 Info.align = Align(AlignOp->getZExtValue()); in getTgtMemIntrinsic()
72 cast<ConstantInt>(I.getOperand(AlignIdx - 1))->getZExtValue()); in getTgtMemIntrinsic()
75 // MVT::getVT(PtrTy->getElementType()); in getTgtMemIntrinsic()
108 SPIRVType *TypeInst = MRI->getVRegDef(OpReg); in getTypeReg()
109 return TypeInst && TypeInst->getOpcode() == SPIRV::OpFunctionParameter in getTypeReg()
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/freebsd/stand/i386/libi386/
H A Dvbe.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
59 * palette array for 8-bit indexed colors. In this case, cmap does store
108 if (strcasecmp(res->name, cmp) == 0) in vbe_resolution_compare()
110 if (res->alias != NULL && strcasecmp(res->alias, cmp) == 0) in vbe_resolution_compare()
132 *width = res->width; in vbe_get_max_resolution()
133 *height = res->height; in vbe_get_max_resolution()
175 vga_set_atr(int reg, int i, int v) in vga_set_atr() argument
179 outb(reg + VGA_AC_WRITE, v); in vga_set_atr()
205 vga_set_crtc(int reg, int i, int v) in vga_set_crtc() argument
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/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86MCInstLower.cpp1 //===-- X86MCInstLower.cpp - Convert X86 MachineInstr to an MCInst --------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
58 static cl::opt<bool> EnableBranchHint("enable-branch-hint",
62 "branch-hint-probability-threshold",
68 /// X86MCInstLower - This class is used to lower an MachineInstr into an MCInst.
79 MCOperand LowerMachineOperand(const MachineInstr *MI,
81 void Lower(const MachineInstr *MI, MCInst &OutMI) const;
123 CodeEmitter->encodeInstruction(Inst, Code, Fixups, STI); in count()
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/freebsd/contrib/llvm-project/llvm/lib/Target/X86/MCTargetDesc/
H A DX86MCCodeEmitter.cpp1 //===-- X86MCCodeEmitter.cpp - Convert X86 code to machine code -----------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
45 // +-----+ +------+
47 // +-----+ +------+
50 // +-----+ +-------------------+
52 // +-----+ +-------------------+
54 // XOP (3-byte)
55 // +-----+ +--------------+ +-------------------+
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/freebsd/contrib/llvm-project/llvm/include/llvm/ADT/
H A DEquivalenceClasses.h1 //===- llvm/ADT/EquivalenceClasses.h - Generic Equiv. Classes ---*- C++ -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 /// efficient union-find algorithm.
13 //===----------------------------------------------------------------------===//
26 /// EquivalenceClasses - This represents a collection of equivalence classes and
47 /// if (!I->isLeader()) continue; // Ignore non-leader sets.
48 /// for (EquivalenceClasses<int>::member_iterator MI = EC.member_begin(I);
49 /// MI != EC.member_end(); ++MI) // Loop over members in this set.
50 /// cerr << *MI << " "; // Print member.
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/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/
H A DRISCVInstPrinter.h1 //===-- RISCVInstPrinter.h - Convert RISC-V MCInst to asm syntax --*- C++ -*--//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This class prints a RISC-V MCInst to a .s file.
11 //===----------------------------------------------------------------------===//
29 void printInst(const MCInst *MI, uint64_t Address, StringRef Annot,
33 void printOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
35 void printBranchOperand(const MCInst *MI, uint64_t Address, unsigned OpNo,
37 void printCSRSystemRegister(const MCInst *MI, unsigned OpNo,
39 void printFenceArg(const MCInst *MI, unsigned OpNo,
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/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
H A DCombinerHelper.h1 //===-- llvm/CodeGen/GlobalISel/CombinerHelper.h --------------*- C++ -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===--------------------------------------------------------------------===//
15 //===--------------------------------------------------------------------===//
52 MachineInstr *MI; member
132 /// \returns true if the combiner is running pre-legalization.
170 /// If \p MI is COPY, try to combine it.
171 /// Returns true if MI changed.
172 bool tryCombineCopy(MachineInstr &MI);
173 bool matchCombineCopy(MachineInstr &MI);
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/freebsd/contrib/llvm-project/llvm/lib/Target/SPIRV/MCTargetDesc/
H A DSPIRVInstPrinter.h1 //===-- SPIRVInstPrinter.h - Output SPIR-V MCInsts as ASM -------*- C++ -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This class prints a SPIR-V MCInst to a .s file.
11 //===----------------------------------------------------------------------===//
24 void recordOpExtInstImport(const MCInst *MI);
29 void printInst(const MCInst *MI, uint64_t Address, StringRef Annot,
31 void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O,
34 void printStringImm(const MCInst *MI, unsigned OpNo, raw_ostream &O);
36 void printOpDecorate(const MCInst *MI, raw_ostream &O);
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/freebsd/sys/dev/sound/pcm/
H A Dmixer.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2005-2009 Ariff Abdullah <ariff@FreeBSD.org>
5 * Portions Copyright (c) Ryan Beasley <ryan.beasley@gmail.com> - GSoC 2006
117 return snddev->mixer_dev; in mixer_get_devt()
129 return -1; in mixer_lookup()
134 snd_mtxunlock((x)->lock); \
139 snd_mtxlock((x)->lock); \
152 if (mtx_owned(m->lock)) in mixer_set_softpcmvol()
157 if (!(d->flags & SD_F_MPSAFE) || mtx_owned(d->lock) != 0) in mixer_set_softpcmvol()
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