Lines Matching +full:mi +full:- +full:v
1 //===- HexagonConstPropagation.cpp ----------------------------------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
102 // Lattice cell, based on that was described in the W-Z paper on constant
201 // Mapping: vreg -> cell
221 // All non-virtual registers are considered "bottom".
233 return F->second;
262 void visitNonBranch(const MachineInstr &MI);
289 // as well as some helper functions that are target-independent.
298 // - A set of three "evaluate" functions. Each returns "true" if the
300 // (1) Given an instruction MI, and the map with input values "Inputs",
302 // the computation can "fail" is if MI is not an instruction that
307 // If the branch can fall-through, add null (0) to the list of
309 // - A function "rewrite", that given the cell map after propagation,
310 // could rewrite instruction MI in a more beneficial form. Return
313 virtual bool evaluate(const MachineInstr &MI, const CellMap &Inputs,
320 virtual bool rewrite(MachineInstr &MI, const CellMap &Inputs) = 0;
333 L = 0x04, // Less-than property.
334 G = 0x08, // Greater-than property.
432 if (CI->isZero())
435 if (CI->isNegative())
442 uint32_t Props = CF->isNegative() ? (NegOrZero|NonZero)
444 if (CF->isZero())
447 if (CF->isNaN())
449 const APFloat &Val = CF->getValueAPF();
511 C->print(os);
589 // Add a property to the cell. This will force the cell to become a property-
623 dbgs() << " " << printReg(I.first, &TRI) << " -> " << I.second << '\n';
629 unsigned MBN = MB->getNumber();
638 // If the def has a sub-register, set the corresponding cell to "bottom".
653 unsigned PBN = PB->getNumber();
655 LLVM_DEBUG(dbgs() << " edge " << printMBBReference(*PB) << "->"
684 void MachineConstPropagator::visitNonBranch(const MachineInstr &MI) {
685 LLVM_DEBUG(dbgs() << "Visiting MI(" << printMBBReference(*MI.getParent())
686 << "): " << MI);
688 bool Eval = MCE.evaluate(MI, Cells, Outputs);
700 for (const MachineOperand &MO : MI.operands()) {
730 // including the potential fall-through to the layout-successor block.
740 const MachineInstr &MI = *It;
741 InstrExec.insert(&MI);
743 << printMBBReference(B) << "): " << MI);
747 EvalOk = EvalOk && MCE.evaluate(MI, Cells, Targets, FallsThru);
763 if (SB->isEHPad())
787 unsigned TBN = TB->getNumber();
788 LLVM_DEBUG(dbgs() << " pushing edge " << printMBBReference(B) << " -> "
797 for (MachineInstr &MI : MRI->use_nodbg_instructions(Reg)) {
798 // Do not process non-executable instructions. They can become exceutable
799 // later (via a flow-edge in the work queue). In such case, the instruc-
801 if (!InstrExec.count(&MI))
803 if (MI.isPHI())
804 visitPHI(MI);
805 else if (!MI.isBranch())
806 visitNonBranch(MI);
808 visitBranchesFrom(MI);
816 MachineBasicBlock::const_iterator FirstBr = MB->end();
817 for (const MachineInstr &MI : *MB) {
818 if (MI.getOpcode() == TargetOpcode::INLINEASM_BR)
820 if (MI.isDebugInstr())
822 if (MI.isBranch()) {
823 FirstBr = MI.getIterator();
828 MachineBasicBlock::const_iterator End = MB->end();
832 const MachineInstr &MI = *I;
834 if (MI.isDebugInstr())
836 if (!InstrExec.count(&MI))
838 bool Eval = MCE.evaluate(MI, Cells, Targets, DoNext);
844 // If the last branch could fall-through, add block's layout successor.
846 MachineFunction::const_iterator BI = MB->getIterator();
848 if (NextI != MB->getParent()->end())
853 for (const MachineBasicBlock *SB : MB->successors())
854 if (SB->isEHPad())
863 From->removeSuccessor(To);
865 for (MachineInstr &PN : To->phis()) {
867 int N = PN.getNumOperands() - 2;
873 N -= 2;
880 unsigned EntryNum = Entry->getNumber();
891 << printMBBReference(*MF.getBlockNumbered(Edge.first)) << "->"
900 // - visit all PHI nodes,
901 // - visit all non-branch instructions,
902 // - visit block branches.
903 MachineBasicBlock::const_iterator It = SB->begin(), End = SB->end();
906 while (It != End && It->isPHI()) {
914 // non-debug instruction to see if it is executable.
915 while (It != End && It->isDebugInstr())
917 assert(It == End || !It->isPHI());
921 // For now, scan all non-branch instructions. Branches require different
923 while (It != End && !It->isBranch()) {
924 if (!It->isDebugInstr()) {
932 // processing regular (non-branch) instructions, because there can
940 unsigned SBN = SB->getNumber();
941 for (const MachineBasicBlock *SSB : SB->successors())
942 FlowQ.push(CFGEdge(SBN, SSB->getNumber()));
953 unsigned SN = SB->getNumber();
955 dbgs() << " " << printMBBReference(B) << " -> "
966 // Traverse the instructions in a post-order, so that rewriting an
967 // instruction can make changes "downstream" in terms of control-flow
977 // Collect the post-order-traversal block ordering. The subsequent
982 if (!B->empty())
997 for (MachineInstr &MI : llvm::reverse(*B)) {
998 if (InstrExec.count(&MI)) {
999 if (MI.isBranch() && !HaveTargets)
1001 Changed |= MCE.rewrite(MI, Cells);
1004 // The rewriting could rewrite PHI nodes to non-PHI nodes, causing
1007 for (auto I = B->begin(), E = B->end(); I != E; ++I) {
1008 if (I->isPHI())
1013 if (P->isPHI())
1019 B->splice(I, B, P);
1021 --I;
1026 for (MachineBasicBlock *SB : B->successors()) {
1035 // This could legitimately happen in blocks that have non-returning
1036 // calls---we would think that the execution can continue, but the
1040 // Need to do some final post-processing.
1046 for (MachineInstr &MI : llvm::make_early_inc_range(B))
1047 if (MI.isBranch() && !InstrExec.count(&MI))
1048 B.erase(&MI);
1053 // This is the constant propagation algorithm as described by Wegman-Zadeck.
1076 // --------------------------------------------------------------------
1097 Val = CI->getValue();
1327 // or a known non-zero.
1375 // with the non-bottom argument passed as the immediate. This is to
1403 if (A2 == -1)
1442 // with the non-bottom argument passed as the immediate. This is to
1443 // catch cases of ORing with -1.
1472 if (A2 == -1) {
1630 int64_t V = A1.getSExtValue();
1633 V = static_cast<int8_t>(V);
1636 V = static_cast<int16_t>(V);
1639 V = static_cast<int32_t>(V);
1645 V = (V << (64-Bits)) >> (64-Bits);
1648 // V is a 64-bit sign-extended value. Convert it to APInt of desired
1650 Result = APInt(Width, V, true);
1773 int64_t V = A1.getZExtValue();
1774 V <<= (64-Bits-Offset);
1776 V >>= (64-Bits);
1778 V = static_cast<uint64_t>(V) >> (64-Bits);
1779 Result = APInt(BW, V, Signed);
1783 Result = A1.shl(BW-Bits-Offset).ashr(BW-Bits);
1785 Result = A1.shl(BW-Bits-Offset).lshr(BW-Bits);
1828 // ----------------------------------------------------------------------
1829 // Hexagon-specific code.
1844 bool evaluate(const MachineInstr &MI, const CellMap &Inputs,
1851 bool rewrite(MachineInstr &MI, const CellMap &Inputs) override;
1859 void replaceWithNop(MachineInstr &MI);
1863 bool evaluateHexCompare(const MachineInstr &MI, const CellMap &Inputs,
1865 // This is suitable to be called for compare-and-jump instructions.
1868 bool evaluateHexLogical(const MachineInstr &MI, const CellMap &Inputs,
1870 bool evaluateHexCondMove(const MachineInstr &MI, const CellMap &Inputs,
1872 bool evaluateHexExt(const MachineInstr &MI, const CellMap &Inputs,
1874 bool evaluateHexVector1(const MachineInstr &MI, const CellMap &Inputs,
1876 bool evaluateHexVector2(const MachineInstr &MI, const CellMap &Inputs,
1881 bool rewriteHexConstDefs(MachineInstr &MI, const CellMap &Inputs,
1883 bool rewriteHexConstUses(MachineInstr &MI, const CellMap &Inputs);
1914 INITIALIZE_PASS(HexagonConstPropagation, "hexagon-constp",
1924 bool HexagonConstEvaluator::evaluate(const MachineInstr &MI,
1926 if (MI.isCall())
1928 if (MI.getNumOperands() == 0 || !MI.getOperand(0).isReg())
1930 const MachineOperand &MD = MI.getOperand(0);
1934 unsigned Opc = MI.getOpcode();
1940 if (MI.isCopy()) {
1942 RegisterSubReg SrcR(MI.getOperand(1));
1949 if (MI.isRegSequence()) {
1950 unsigned Sub1 = MI.getOperand(2).getImm();
1951 unsigned Sub2 = MI.getOperand(4).getImm();
1952 const TargetRegisterClass &DefRC = *MRI->getRegClass(DefR.Reg);
1961 const MachineOperand &OpLo = LoIs1 ? MI.getOperand(1) : MI.getOperand(3);
1962 const MachineOperand &OpHi = LoIs1 ? MI.getOperand(3) : MI.getOperand(1);
1971 if (MI.isCompare()) {
1972 bool Eval = evaluateHexCompare(MI, Inputs, Outputs);
1984 const MachineOperand &VO = MI.getOperand(1);
1990 int64_t V = MI.getOperand(1).getImm();
1996 const ConstantInt *CI = ConstantInt::get(Ty, V, true);
2024 bool Eval = evaluateHexLogical(MI, Inputs, Outputs);
2033 if (!MI.getOperand(1).isImm() || !MI.getOperand(2).isImm())
2035 uint64_t Hi = MI.getOperand(1).getImm();
2036 uint64_t Lo = MI.getOperand(2).getImm();
2048 int64_t B = MI.getOperand(2).getImm();
2051 RegisterSubReg R(MI.getOperand(1));
2065 bool Eval = evaluateHexCondMove(MI, Inputs, Outputs);
2077 bool Eval = evaluateHexExt(MI, Inputs, Outputs);
2091 RegisterSubReg R1(MI.getOperand(1));
2097 // All of these instructions return a 32-bit value. The evaluate
2123 RegisterSubReg R1(MI.getOperand(1));
2129 // All of these instructions return a 32-bit value. The evaluate
2151 RegisterSubReg R1(MI.getOperand(1));
2153 unsigned Bits = MI.getOperand(2).getImm();
2154 unsigned Offset = MI.getOperand(3).getImm();
2165 Bits = BW-Offset;
2186 bool Eval = evaluateHexVector1(MI, Inputs, Outputs);
2208 const TargetRegisterClass *RC = MRI->getRegClass(R.Reg);
2327 bool HexagonConstEvaluator::rewrite(MachineInstr &MI, const CellMap &Inputs) {
2328 if (MI.isBranch())
2329 return rewriteHexBranch(MI, Inputs);
2331 unsigned Opc = MI.getOpcode();
2344 unsigned NumOp = MI.getNumOperands();
2349 Changed = rewriteHexConstDefs(MI, Inputs, AllDefs);
2351 // a register that is not compile-time constant), then try to rewrite
2354 Changed |= rewriteHexConstUses(MI, Inputs);
2360 const TargetRegisterClass *RC = MRI->getRegClass(Reg);
2509 void HexagonConstEvaluator::replaceWithNop(MachineInstr &MI) {
2510 MI.setDesc(HII.get(Hexagon::A2_nop));
2511 while (MI.getNumOperands() > 0)
2512 MI.removeOperand(0);
2552 bool HexagonConstEvaluator::evaluateHexCompare(const MachineInstr &MI,
2554 unsigned Opc = MI.getOpcode();
2575 const MachineOperand &Src1 = MI.getOperand(1);
2576 const MachineOperand &Src2 = MI.getOperand(2);
2579 unsigned Opc = MI.getOpcode();
2582 // Only create a zero/non-zero cell. At this time there isn't really
2584 RegisterSubReg DefR(MI.getOperand(0));
2627 bool HexagonConstEvaluator::evaluateHexLogical(const MachineInstr &MI,
2629 unsigned Opc = MI.getOpcode();
2630 if (MI.getNumOperands() != 3)
2632 const MachineOperand &Src1 = MI.getOperand(1);
2633 const MachineOperand &Src2 = MI.getOperand(2);
2668 RegisterSubReg DefR(MI.getOperand(0));
2674 bool HexagonConstEvaluator::evaluateHexCondMove(const MachineInstr &MI,
2677 RegisterSubReg CR(MI.getOperand(1));
2691 const MachineOperand &ValOp = MI.getOperand(TakeOp);
2692 RegisterSubReg DefR(MI.getOperand(0));
2696 int64_t V = ValOp.getImm();
2698 APInt A(W, V, true);
2717 bool HexagonConstEvaluator::evaluateHexExt(const MachineInstr &MI,
2720 RegisterSubReg R1(MI.getOperand(1));
2723 unsigned Opc = MI.getOpcode();
2750 RegisterSubReg DefR(MI.getOperand(0));
2761 bool HexagonConstEvaluator::evaluateHexVector1(const MachineInstr &MI,
2764 RegisterSubReg DefR(MI.getOperand(0));
2765 RegisterSubReg R1(MI.getOperand(1));
2770 unsigned Opc = MI.getOpcode();
2790 bool HexagonConstEvaluator::rewriteHexConstDefs(MachineInstr &MI,
2800 for (const MachineOperand &MO : MI.operands()) {
2808 if (!MI.isPHI() && !Inputs.has(R.Reg)) {
2810 << " in MI: " << MI;
2819 if (!MI.isCopy()) {
2820 dbgs() << "CONST: " << MI;
2821 for (const MachineOperand &MO : MI.operands()) {
2832 // Avoid generating TFRIs for register transfers---this will keep the
2834 if (MI.isCopy())
2837 MachineFunction *MF = MI.getParent()->getParent();
2838 auto &HST = MF->getSubtarget<HexagonSubtarget>();
2840 // Collect all virtual register-def operands.
2842 for (const MachineOperand &MO : MI.operands()) {
2853 MachineBasicBlock &B = *MI.getParent();
2854 const DebugLoc &DL = MI.getDebugLoc();
2867 const TargetRegisterClass *RC = MRI->getRegClass(R);
2868 MachineBasicBlock::iterator At = MI.getIterator();
2871 // If this a zero/non-zero cell, we can fold a definition
2884 Register NewR = MRI->createVirtualRegister(PredRC);
2900 int64_t V = A.getSExtValue();
2906 Register NewR = MRI->createVirtualRegister(NewRC);
2912 .addImm(V);
2917 .addImm(V);
2919 int32_t Hi = V >> 32;
2920 int32_t Lo = V & 0xFFFFFFFFLL;
2926 } else if (MF->getFunction().hasOptSize() || !HST.isTinyCore()) {
2930 .addImm(V);
2946 MachineFunction &MF = *MI.getParent()->getParent();
2948 dbgs() << "Rewrite: for " << MI << " created " << *NewInstrs[0];
2958 bool HexagonConstEvaluator::rewriteHexConstUses(MachineInstr &MI,
2961 unsigned Opc = MI.getOpcode();
2962 MachineBasicBlock &B = *MI.getParent();
2963 const DebugLoc &DL = MI.getDebugLoc();
2964 MachineBasicBlock::iterator At = MI.getIterator();
2971 // or DefR -= mpyi(R, #imm).
2973 RegisterSubReg DefR(MI.getOperand(0));
2975 RegisterSubReg R2(MI.getOperand(2));
2976 RegisterSubReg R3(MI.getOperand(3));
2980 // to replace one argument---whichever happens to be a single constant.
2989 MachineOperand &Acc = MI.getOperand(1);
2994 const TargetRegisterClass *RC = MRI->getRegClass(DefR.Reg);
2995 NewR = MRI->createVirtualRegister(RC);
3000 MRI->clearKillFlags(NewR);
3012 const MachineOperand &OpR2 = Swap ? MI.getOperand(3)
3013 : MI.getOperand(2);
3018 int64_t V = A.getSExtValue();
3019 const MCInstrDesc &D = (V >= 0) ? HII.get(Hexagon::M2_macsip)
3021 if (V < 0)
3022 V = -V;
3023 const TargetRegisterClass *RC = MRI->getRegClass(DefR.Reg);
3024 Register NewR = MRI->createVirtualRegister(RC);
3025 const MachineOperand &Src1 = MI.getOperand(1);
3029 .addImm(V);
3037 RegisterSubReg R1(MI.getOperand(1));
3038 RegisterSubReg R2(MI.getOperand(2));
3042 // Check if any of the operands is -1 (i.e. all bits set).
3055 MachineOperand &SO = MI.getOperand(CopyOf);
3057 RegisterSubReg DefR(MI.getOperand(0));
3060 const TargetRegisterClass *RC = MRI->getRegClass(DefR.Reg);
3061 NewR = MRI->createVirtualRegister(RC);
3066 MRI->clearKillFlags(NewR);
3073 RegisterSubReg R1(MI.getOperand(1));
3074 RegisterSubReg R2(MI.getOperand(2));
3087 MachineOperand &SO = MI.getOperand(CopyOf);
3089 RegisterSubReg DefR(MI.getOperand(0));
3092 const TargetRegisterClass *RC = MRI->getRegClass(DefR.Reg);
3093 NewR = MRI->createVirtualRegister(RC);
3098 MRI->clearKillFlags(NewR);
3106 for (MachineOperand &MO : NewMI->operands())
3113 dbgs() << "Rewrite: for " << MI;
3114 if (NewMI != &MI)
3129 llvm::make_early_inc_range(MRI->use_operands(FromReg)))
3153 // MIB.addMBB needs non-const pointer.
3158 // erased as "non-executable". We can't mark any new instructions
3167 // This ensures that all implicit operands (e.g. implicit-def %r31, etc)
3169 for (auto &Op : NI->operands())
3171 NI->eraseFromParent();