Lines Matching +full:mi +full:- +full:v
1 //===- HexagonPatterns.td - Selection Patterns for Hexagon -*- tablegen -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
49 // 6. The v4 vector instructions (64-bit) are treated as core instructions,
51 // 7. When adding a pattern for an instruction with a constant-extendable
56 // --(0) Definitions -----------------------------------------------------
115 def ssat: PatFrag<(ops node:$V, node:$Ty), (HexagonSSAT node:$V, node:$Ty)>;
116 def usat: PatFrag<(ops node:$V, node:$Ty), (HexagonUSAT node:$V, node:$Ty)>;
119 // 64-bit value.
128 uint32_t V = N->getZExtValue();
129 return isPowerOf2_32(V);
133 uint64_t V = N->getZExtValue();
134 return isPowerOf2_64(V);
138 uint32_t NV = ~N->getZExtValue();
143 uint64_t V = N->getZExtValue();
144 return isPowerOf2_64(V) && Log2_64(V) < 32;
148 uint64_t V = N->getZExtValue();
149 return isPowerOf2_64(V) && Log2_64(V) >= 32;
153 uint64_t NV = ~N->getZExtValue();
158 uint64_t NV = ~N->getZExtValue();
163 "uint64_t V = N->getZExtValue();" #
164 "return isUInt<" # Width # ">(V) && V <= " # Arg # ";"
168 "uint64_t V = N->getZExtValue();" #
169 "return isUInt<" # Width # ">(V) && V > " # Arg # ";"
173 int32_t V = N->getSExtValue();
174 return CurDAG->getTargetConstant(V-1, SDLoc(N), MVT::i32);
178 uint32_t V = N->getZExtValue();
179 assert(V >= 1);
180 return CurDAG->getTargetConstant(V-1, SDLoc(N), MVT::i32);
184 uint32_t V = N->getZExtValue();
185 assert(V >= 32);
186 return CurDAG->getTargetConstant(V-32, SDLoc(N), MVT::i32);
190 "int32_t V = " # From # " - N->getSExtValue();" #
191 "return CurDAG->getTargetConstant(V, SDLoc(N), MVT::i32);"
195 uint32_t V = N->getZExtValue();
196 return CurDAG->getTargetConstant(Log2_32(V), SDLoc(N), MVT::i32);
200 uint64_t V = N->getZExtValue();
201 return CurDAG->getTargetConstant(Log2_64(V), SDLoc(N), MVT::i32);
205 uint32_t NV = ~N->getZExtValue();
206 return CurDAG->getTargetConstant(Log2_32(NV), SDLoc(N), MVT::i32);
210 uint64_t NV = ~N->getZExtValue();
211 return CurDAG->getTargetConstant(Log2_64(NV), SDLoc(N), MVT::i32);
215 int8_t NV = -N->getSExtValue();
216 return CurDAG->getTargetConstant(NV, SDLoc(N), MVT::i32);
220 int16_t NV = -N->getSExtValue();
221 return CurDAG->getTargetConstant(NV, SDLoc(N), MVT::i32);
225 int32_t NV = -N->getSExtValue();
226 return CurDAG->getTargetConstant(NV, SDLoc(N), MVT::i32);
230 uint32_t V = N->getZExtValue();
231 assert(isUInt<8>(V) || V >> 8 == 0xFFFFFF);
232 V &= 0xFF;
233 uint32_t S = V << 24 | V << 16 | V << 8 | V;
234 return CurDAG->getTargetConstant(S, SDLoc(N), MVT::i32);
238 uint32_t V = N->getZExtValue();
239 assert(isUInt<16>(V) || V >> 16 == 0xFFFF);
240 V &= 0xFFFF;
241 return CurDAG->getTargetConstant(V << 16 | V, SDLoc(N), MVT::i32);
270 return N->isExactlyValue(APFloat::getZero(APFloat::IEEEsingle(), false));
274 // sign-extension i32->i64. The selected value will be of type i64
310 SDValue Op1 = N->getOperand(1);
322 class OpR_R_pat<InstHexagon MI, PatFrag Op, ValueType ResVT, PatFrag RegPred>
323 : Pat<(ResVT (Op RegPred:$Rs)), (MI RegPred:$Rs)>;
325 class OpR_RI_pat<InstHexagon MI, PatFrag Op, ValueType ResType,
328 (MI RegPred:$Rs, imm:$I)>;
330 class OpR_RR_pat<InstHexagon MI, PatFrag Op, ValueType ResType,
333 (MI RsPred:$Rs, RtPred:$Rt)>;
335 class AccRRI_pat<InstHexagon MI, PatFrag AccOp, PatFrag Op,
338 (MI RegPred:$Rx, RegPred:$Rs, imm:$I)>;
340 class AccRRR_pat<InstHexagon MI, PatFrag AccOp, PatFrag Op,
343 (MI RxPred:$Rx, RsPred:$Rs, RtPred:$Rt)>;
364 // Bitcasts between same-size vector types are no-ops, except for the
387 // --(1) Immediate -------------------------------------------------------
391 return CurDAG->getTargetConstant(int32_t (N->getSExtValue()),
395 return CurDAG->getTargetConstant(int32_t (N->getSExtValue()>>32),
409 return CurDAG->getTargetConstant(N->getSExtValue(), SDLoc(N), MVT::i32);
427 def: Pat<(i64 imm:$v), (CONST64 imm:$v)>,
429 def: Pat<(i64 imm:$v),
430 (Combinew (A2_tfrsi (Imm64Hi $v)), (A2_tfrsi (Imm64Lo $v)))>;
433 APInt I = N->getValueAPF().bitcastToAPInt();
434 return CurDAG->getTargetConstant(I.getZExtValue(), SDLoc(N),
441 def ToI32: OutPatFrag<(ops node:$V), (A2_tfrsi $V)>;
443 // --(2) Type cast -------------------------------------------------------
470 def: Pat<(i32 (bitconvert F32:$v)), (I32:$v)>;
471 def: Pat<(f32 (bitconvert I32:$v)), (F32:$v)>;
472 def: Pat<(i64 (bitconvert F64:$v)), (I64:$v)>;
473 def: Pat<(f64 (bitconvert I64:$v)), (F64:$v)>;
475 // Bit convert 32- and 64-bit types.
489 // --(3) Extend/truncate/saturate ----------------------------------------
514 def: Pat<(i32 (sext I1:$Pu)), (C2_muxii I1:$Pu, -1, 0)>;
515 def: Pat<(i64 (sext I1:$Pu)), (Combinew (C2_muxii PredRegs:$Pu, -1, 0),
516 (C2_muxii PredRegs:$Pu, -1, 0))>;
524 def Vsplatpi: OutPatFrag<(ops node:$V),
525 (Combinew (A2_tfrsi $V), (A2_tfrsi $V))>;
558 // Truncate: from vectors B and C copy all 'E'ven 'H'alf-word elements:
580 // Note: saturation assumes the same signed-ness for the input and the
588 (C2_mux (C2_cmpeqi (HiReg $Rs), (i32 0)), (LoReg $Rs), (i32 -1))>;
596 // --(4) Logical ---------------------------------------------------------
603 def: Pat<(add I1:$Ps, -1), (C2_not I1:$Ps)>;
620 multiclass BoolvOpR_RR_pat<InstHexagon MI, PatFrag VOp> {
621 def: OpR_RR_pat<MI, VOp, v2i1, V2I1>;
622 def: OpR_RR_pat<MI, VOp, v4i1, V4I1>;
623 def: OpR_RR_pat<MI, VOp, v8i1, V8I1>;
626 multiclass BoolvAccRRR_pat<InstHexagon MI, PatFrag AccOp, PatFrag VOp> {
627 def: AccRRR_pat<MI, AccOp, VOp, V2I1, V2I1, V2I1>;
628 def: AccRRR_pat<MI, AccOp, VOp, V4I1, V4I1, V4I1>;
629 def: AccRRR_pat<MI, AccOp, VOp, V8I1, V8I1, V8I1>;
651 // --(5) Compare ---------------------------------------------------------
756 class Outn<InstHexagon MI>
758 (C2_not (MI $Rs, $Rt))>;
802 multiclass Cmpb_pat<InstHexagon MI, PatFrag Op, PatFrag AssertExt,
805 (MI I32:$Rs, imm:$I)>;
807 (MI I32:$Rs, imm:$I)>;
810 multiclass CmpbN_pat<InstHexagon MI, PatFrag Op, PatFrag AssertExt,
813 (C2_not (MI I32:$Rs, imm:$I))>;
815 (C2_not (MI I32:$Rs, imm:$I))>;
818 multiclass CmpbND_pat<InstHexagon MI, PatFrag Op, PatFrag AssertExt,
821 (C2_not (MI I32:$Rs, (UDEC1 imm:$I)))>;
823 (C2_not (MI I32:$Rs, (UDEC1 imm:$I)))>;
846 def: Pat<(i1 (seteq I1:$Ps, (i1 -1))), (I1:$Ps)>;
847 def: Pat<(i1 (setne I1:$Ps, (i1 -1))), (C2_not I1:$Ps)>;
862 // Signed "true" == -1
874 // Floating-point comparisons with checks for ordered/unordered status.
880 class Cmpuf<InstHexagon MI>: T3<C2_or, F2_sfcmpuo, MI>;
881 class Cmpud<InstHexagon MI>: T3<C2_or, F2_dfcmpuo, MI>;
883 class Cmpufn<InstHexagon MI>: T3<C2_orn, F2_sfcmpuo, MI>;
884 class Cmpudn<InstHexagon MI>: T3<C2_orn, F2_dfcmpuo, MI>;
910 // --(6) Select ----------------------------------------------------------
935 // Map from a 64-bit select to an emulated 64-bit mux.
936 // Hexagon does not support 64-bit MUXes; so emulate with combines.
1061 // --(7) Insert/extract --------------------------------------------------
1096 def: Pat<(v4i8 (splat_vector anyint:$V)), (ToI32 (SplatB $V))>;
1097 def: Pat<(v2i16 (splat_vector anyint:$V)), (ToI32 (SplatH $V))>;
1098 def: Pat<(v8i8 (splat_vector anyint:$V)),
1099 (Combinew (ToI32 (SplatB $V)), (ToI32 (SplatB $V)))>;
1100 def: Pat<(v4i16 (splat_vector anyint:$V)),
1101 (Combinew (ToI32 (SplatH $V)), (ToI32 (SplatH $V)))>;
1105 def: Pat<(v2i32 (splat_vector anyimm:$V)), (Combinew (ToI32 $V), (ToI32 $V))>;
1143 // --(8) Shift/permute ---------------------------------------------------
1207 uint64_t V = N->getZExtValue();
1208 return V % 8 == 0 && isUInt<3>(V / 8);
1212 return CurDAG->getTargetConstant(N->getZExtValue() / 8, SDLoc(N), MVT::i32);
1215 // Funnel shift-left.
1228 return CurDAG->getTargetConstant((64 - N->getSExtValue()) / 8,
1255 // Funnel shift-right.
1386 class OpshIRI_pat<InstHexagon MI, PatFrag Op, PatFrag ShOp,
1389 (MI anyimm:$u8, RegPred:$Rs, imm:$U5)>;
1403 // two 32-bit words into a 64-bit word.
1478 // --(9) Arithmetic/bitwise ----------------------------------------------
1483 def: Pat<(not I32:$Rs), (A2_subri -1, I32:$Rs)>;
1592 // In expressions like a0*b0 + a1*b1 + ..., prefer to generate multiply-add,
1593 // over add-add with individual multiplies as inputs.
1626 (C2_vmux (A4_vcmpbgti $Rss, -1), (A2_tfrpi 0), $Rtt)>;
1631 // (Mulhs x, y) = (Mulhu x, y) - (x < 0 ? y : 0) - (y < 0 ? x : 0)
1642 // v2i16 *s v2i16 -> v2i32
1677 int64_t V = N->getSExtValue();
1678 return -255 <= V && V <= 0;
1681 // Change the sign of the immediate for Rd=-mpyi(Rs,#u8)
1798 // Multiply 64-bit unsigned and use upper result.
1801 // Multiply 64-bit signed and use upper result.
1803 // For two signed 64-bit integers A and B, let A' and B' denote A and B
1804 // with the sign bit cleared. Then A = -2^63*s(A) + A', where s(A) is the
1807 // AB = (-2^63 s(A) + A') * (-2^63 s(B) + B')
1808 // = 2^126 s(A)s(B) - 2^63 [s(A)B'+s(B)A'] + A'B'
1809 // = 2^126 s(A)s(B) + 2^63 [s(A)B'+s(B)A'] + A'B' - 2*2^63 [s(A)B'+s(B)A']
1810 // = (unsigned product AB) - 2^64 [s(A)B'+s(B)A']
1812 // Clear the sign bit in a 64-bit register.
1861 // Use M2_vmpy2s_s0 for half-word vector multiply. It multiplies two
1862 // half-words, and saturates the result to a 32-bit value, except the
1881 // --(10) Bit ------------------------------------------------------------
1900 // Define leading/trailing patterns that require zero-extensions to 64 bits.
1927 def: Pat<(and I32:$Rs, IsNPow2_32:$V),
1928 (S2_clrbit_i IntRegs:$Rs, (LogN2_32 $V))>;
1929 def: Pat<(or I32:$Rs, IsPow2_32:$V),
1930 (S2_setbit_i IntRegs:$Rs, (Log2_32 $V))>;
1931 def: Pat<(xor I32:$Rs, IsPow2_32:$V),
1932 (S2_togglebit_i IntRegs:$Rs, (Log2_32 $V))>;
1942 // Clr/set/toggle bit for 64-bit values with immediate bit index.
1944 def: Pat<(and I64:$Rss, IsNPow2_64L:$V),
1946 (S2_clrbit_i (LoReg $Rss), (LogN2_64 $V)))>;
1947 def: Pat<(and I64:$Rss, IsNPow2_64H:$V),
1948 (Combinew (S2_clrbit_i (HiReg $Rss), (UDEC32 (i32 (LogN2_64 $V)))),
1951 def: Pat<(or I64:$Rss, IsPow2_64L:$V),
1953 (S2_setbit_i (LoReg $Rss), (Log2_64 $V)))>;
1954 def: Pat<(or I64:$Rss, IsPow2_64H:$V),
1955 (Combinew (S2_setbit_i (HiReg $Rss), (UDEC32 (i32 (Log2_64 $V)))),
1958 def: Pat<(xor I64:$Rss, IsPow2_64L:$V),
1960 (S2_togglebit_i (LoReg $Rss), (Log2_64 $V)))>;
1961 def: Pat<(xor I64:$Rss, IsPow2_64H:$V),
1962 (Combinew (S2_togglebit_i (HiReg $Rss), (UDEC32 (i32 (Log2_64 $V)))),
1967 let AddedComplexity = 20 in { // Complexity greater than cmp reg-imm.
1992 let AddedComplexity = 20 in { // Complexity greater than compare reg-imm.
1999 let AddedComplexity = 10 in // Complexity greater than compare reg-reg.
2015 let AddedComplexity = 20 in { // Complexity greater than cmp reg-imm.
2048 // Special patterns to address certain cases where the "top-down" matching
2067 // --(11) PIC ------------------------------------------------------------
2075 // AT_GOT address-of-GOT, address-of-global, offset-in-global
2077 // AT_PCREL address-of-global
2091 // --(12) Load -----------------------------------------------------------
2098 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::v2i8;
2101 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::v4i8;
2105 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::v2i8;
2108 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::v4i8;
2112 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::v2i8;
2115 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::v4i8;
2118 // Patterns to select load-indexed: Rs + Off.
2119 // - frameindex [+ imm],
2121 InstHexagon MI> {
2123 (VT (MI AddrFI:$fi, imm:$Off))>;
2125 (VT (MI AddrFI:$fi, imm:$Off))>;
2126 def: Pat<(VT (Load AddrFI:$fi)), (VT (MI AddrFI:$fi, 0))>;
2129 // Patterns to select load-indexed: Rs + Off.
2130 // - base reg [+ imm]
2132 InstHexagon MI> {
2134 (VT (MI IntRegs:$Rs, imm:$Off))>;
2136 (VT (MI IntRegs:$Rs, imm:$Off))>;
2137 def: Pat<(VT (Load I32:$Rs)), (VT (MI IntRegs:$Rs, 0))>;
2140 // Patterns to select load-indexed: Rs + Off. Combines Loadxfi + Loadxgi.
2142 InstHexagon MI> {
2143 defm: Loadxfi_pat<Load, VT, ImmPred, MI>;
2144 defm: Loadxgi_pat<Load, VT, ImmPred, MI>;
2148 // - frameindex [+ imm]
2150 PatLeaf ImmPred, InstHexagon MI> {
2152 (VT (ValueMod (MI AddrFI:$fi, imm:$Off)))>;
2154 (VT (ValueMod (MI AddrFI:$fi, imm:$Off)))>;
2155 def: Pat<(VT (Load AddrFI:$fi)), (VT (ValueMod (MI AddrFI:$fi, 0)))>;
2159 // - base reg [+ imm]
2161 PatLeaf ImmPred, InstHexagon MI> {
2163 (VT (ValueMod (MI IntRegs:$Rs, imm:$Off)))>;
2165 (VT (ValueMod (MI IntRegs:$Rs, imm:$Off)))>;
2166 def: Pat<(VT (Load I32:$Rs)), (VT (ValueMod (MI IntRegs:$Rs, 0)))>;
2172 PatLeaf ImmPred, InstHexagon MI> {
2173 defm: Loadxfim_pat<Load, VT, ValueMod, ImmPred, MI>;
2174 defm: Loadxgim_pat<Load, VT, ValueMod, ImmPred, MI>;
2177 // Pattern to select load reg reg-indexed: Rs + Rt<<u2.
2178 class Loadxr_shl_pat<PatFrag Load, ValueType VT, InstHexagon MI>
2180 (VT (MI IntRegs:$Rs, IntRegs:$Rt, imm:$u2))>;
2182 // Pattern to select load reg reg-indexed: Rs + Rt<<0.
2183 class Loadxr_add_pat<PatFrag Load, ValueType VT, InstHexagon MI>
2185 (VT (MI IntRegs:$Rs, IntRegs:$Rt, 0))>;
2187 // Pattern to select load reg reg-indexed: Rs + Rt<<u2 with value modifier.
2189 InstHexagon MI>
2191 (VT (ValueMod (MI IntRegs:$Rs, IntRegs:$Rt, imm:$u2)))>;
2193 // Pattern to select load reg reg-indexed: Rs + Rt<<0 with value modifier.
2195 InstHexagon MI>
2197 (VT (ValueMod (MI IntRegs:$Rs, IntRegs:$Rt, 0)))>;
2199 // Pattern to select load long-offset reg-indexed: Addr + Rt<<u2.
2201 class Loadxu_pat<PatFrag Load, ValueType VT, PatFrag ImmPred, InstHexagon MI>
2203 (VT (MI IntRegs:$Rt, imm:$u2, ImmPred:$Addr))>;
2206 InstHexagon MI>
2208 (VT (ValueMod (MI IntRegs:$Rt, imm:$u2, ImmPred:$Addr)))>;
2211 class Loada_pat<PatFrag Load, ValueType VT, PatFrag Addr, InstHexagon MI>
2212 : Pat<(VT (Load Addr:$addr)), (MI Addr:$addr)>;
2216 InstHexagon MI>
2217 : Pat<(VT (Load Addr:$addr)), (ValueMod (MI Addr:$addr))>;
2254 // It doesn't matter if it's sign- or zero-extended, so use zero-extension
2432 // GP-relative address
2487 // --(13) Store ----------------------------------------------------------
2490 class Storepi_pat<PatFrag Store, PatFrag Value, PatFrag Offset, InstHexagon MI>
2492 (MI I32:$Rx, imm:$s4, Value:$Rt)>;
2500 // - frameindex,
2501 // - frameindex + offset,
2502 // - base + offset,
2503 // - simple (base address without offset).
2507 class Storexi_fi_pat<PatFrag Store, PatFrag Value, InstHexagon MI>
2508 : Pat<(Store Value:$Rs, AddrFI:$fi), (MI AddrFI:$fi, 0, Value:$Rs)>;
2511 InstHexagon MI> {
2513 (MI AddrFI:$fi, imm:$Off, Value:$Rs)>;
2515 (MI AddrFI:$fi, imm:$Off, Value:$Rs)>;
2519 InstHexagon MI> {
2521 (MI IntRegs:$Rs, imm:$Off, Value:$Rt)>;
2523 (MI IntRegs:$Rs, imm:$Off, Value:$Rt)>;
2526 class Storexi_base_pat<PatFrag Store, PatFrag Value, InstHexagon MI>
2528 (MI IntRegs:$Rs, 0, Value:$Rt)>;
2534 InstHexagon MI>
2536 (MI AddrFI:$fi, 0, (ValueMod Value:$Rs))>;
2539 PatFrag ValueMod, InstHexagon MI> {
2541 (MI AddrFI:$fi, imm:$Off, (ValueMod Value:$Rs))>;
2543 (MI AddrFI:$fi, imm:$Off, (ValueMod Value:$Rs))>;
2547 PatFrag ValueMod, InstHexagon MI> {
2549 (MI IntRegs:$Rs, imm:$Off, (ValueMod Value:$Rt))>;
2551 (MI IntRegs:$Rs, imm:$Off, (ValueMod Value:$Rt))>;
2555 InstHexagon MI>
2557 (MI IntRegs:$Rs, 0, (ValueMod Value:$Rt))>;
2560 InstHexagon MI> {
2561 defm: Storexi_fi_add_pat <Store, Value, ImmPred, MI>;
2562 def: Storexi_fi_pat <Store, Value, MI>;
2563 defm: Storexi_add_pat <Store, Value, ImmPred, MI>;
2567 PatFrag ValueMod, InstHexagon MI> {
2568 defm: Storexim_fi_add_pat <Store, Value, ImmPred, ValueMod, MI>;
2569 def: Storexim_fi_pat <Store, Value, ValueMod, MI>;
2570 defm: Storexim_add_pat <Store, Value, ImmPred, ValueMod, MI>;
2574 class Storexu_shl_pat<PatFrag Store, PatFrag Value, PatFrag ImmPred, InstHexagon MI>
2576 (MI IntRegs:$Ru, imm:$u2, ImmPred:$A, Value:$Rt)>;
2579 class Storexr_shl_pat<PatFrag Store, PatFrag Value, InstHexagon MI>
2581 (MI IntRegs:$Rs, IntRegs:$Rt, imm:$u2, Value:$Ru)>;
2584 class Storexr_add_pat<PatFrag Store, PatFrag Value, InstHexagon MI>
2586 (MI IntRegs:$Rs, IntRegs:$Rt, 0, Value:$Ru)>;
2588 class Storea_pat<PatFrag Store, PatFrag Value, PatFrag Addr, InstHexagon MI>
2589 : Pat<(Store Value:$val, Addr:$addr), (MI Addr:$addr, Value:$val)>;
2592 InstHexagon MI>
2594 (MI Addr:$addr, (ValueMod Value:$val))>;
2597 // -1 can be represented as 255, etc.
2599 int8_t imm = N->getSExtValue();
2600 return CurDAG->getTargetConstant(imm, SDLoc(N), MVT::i32);
2604 // -1 can be represented as 65535, etc.
2606 int16_t imm = N->getSExtValue();
2607 return CurDAG->getTargetConstant(imm, SDLoc(N), MVT::i32);
2611 // -1 can be represented as 4294967295, etc.
2613 // might convert -1 to a large +ve number.
2615 int32_t imm = N->getSExtValue();
2616 return CurDAG->getTargetConstant(imm, SDLoc(N), MVT::i32);
2623 // Even though the offset is not extendable in the store-immediate, we
2641 // store-immediate. The reason is that the constant-extender optimization
2642 // can replace store-immediate with a store-register, but there is nothing
2643 // to generate a store-immediate out of a store-register.
2646 // --+-------+-----+-----+------+-----+-----+--------+--------
2650 // (*) Absolute or GP-relative.
2662 // --+-------+-----+-----+------+-----+-----+--------+--------
2663 // C | 1 | 6 | - | 5 | 9 | - | - | -
2673 int64_t v = (int64_t)N->getSExtValue();
2674 return isShiftedInt<30,2>(v) && !isShiftedInt<29,3>(v);
2677 int32_t Imm = N->getSExtValue();
2678 return CurDAG->getTargetConstant(Imm & -8, SDLoc(N), MVT::i32);
2685 class Storexi_abs_pat<PatFrag Store, PatFrag Value, InstHexagon MI>
2687 (MI (ToI32 $addr), 0, Value:$val)>;
2689 InstHexagon MI>
2691 (MI (ToI32 $addr), 0, (ValueMod Value:$val))>;
2703 // GP-relative address
2800 multiclass IMFA_<PatFrag S, PatFrag V, PatFrag O, PatFrag M, InstHexagon I> {
2801 defm: Storexim_fi_add_pat<S, V, O, M, I>;
2803 multiclass IFA_<PatFrag S, PatFrag V, PatFrag O, InstHexagon I> {
2804 defm: Storexi_fi_add_pat<S, V, O, I>;
2807 // Fi+Imm, store-immediate
2817 // For large-stack stores, generate store-register (prefer explicit Fi
2824 // Fi, store-immediate
2834 // For large-stack stores, generate store-register (prefer explicit Fi
2841 // Fi+Imm, Fi, store-register
2871 multiclass IMRA_<PatFrag S, PatFrag V, PatFrag O, PatFrag M, InstHexagon I> {
2872 defm: Storexim_add_pat<S, V, O, M, I>;
2874 multiclass IRA_<PatFrag S, PatFrag V, PatFrag O, InstHexagon I> {
2875 defm: Storexi_add_pat<S, V, O, I>;
2878 // Reg+Imm, store-immediate
2889 // Reg+Imm, store-register
2937 // Reg, store-immediate
2948 // Reg, store-register
2979 // --(14) Memop ----------------------------------------------------------
2983 int8_t V = N->getSExtValue();
2984 return -32 < V && V <= -1;
2988 int16_t V = N->getSExtValue();
2989 return -32 < V && V <= -1;
2993 int64_t V = N->getSExtValue();
2994 return -31 <= V && V <= -1;
2998 uint8_t NV = ~N->getZExtValue();
3003 uint16_t NV = ~N->getZExtValue();
3008 uint8_t V = N->getZExtValue();
3009 return CurDAG->getTargetConstant(Log2_32(V), SDLoc(N), MVT::i32);
3013 uint16_t V = N->getZExtValue();
3014 return CurDAG->getTargetConstant(Log2_32(V), SDLoc(N), MVT::i32);
3018 uint8_t NV = ~N->getZExtValue();
3019 return CurDAG->getTargetConstant(Log2_32(NV), SDLoc(N), MVT::i32);
3023 uint16_t NV = ~N->getZExtValue();
3024 return CurDAG->getTargetConstant(Log2_32(NV), SDLoc(N), MVT::i32);
3030 InstHexagon MI> {
3033 (MI I32:$Rs, 0, I32:$A)>;
3036 (MI AddrFI:$Rs, 0, I32:$A)>;
3040 SDNode Oper, InstHexagon MI> {
3044 (MI I32:$Rs, imm:$Off, I32:$A)>;
3047 (MI I32:$Rs, imm:$Off, I32:$A)>;
3051 (MI AddrFI:$Rs, imm:$Off, I32:$A)>;
3054 (MI AddrFI:$Rs, imm:$Off, I32:$A)>;
3058 SDNode Oper, InstHexagon MI> {
3060 defm: Memopxr_base_pat <Load, Store, Oper, MI>;
3061 defm: Memopxr_add_pat <Load, Store, ImmPred, Oper, MI>;
3129 PatFrag Arg, SDNodeXForm ArgMod, InstHexagon MI> {
3132 (MI I32:$Rs, 0, (ArgMod Arg:$A))>;
3135 (MI AddrFI:$Rs, 0, (ArgMod Arg:$A))>;
3140 InstHexagon MI> {
3144 (MI I32:$Rs, imm:$Off, (ArgMod Arg:$A))>;
3147 (MI I32:$Rs, imm:$Off, (ArgMod Arg:$A))>;
3151 (MI AddrFI:$Rs, imm:$Off, (ArgMod Arg:$A))>;
3154 (MI AddrFI:$Rs, imm:$Off, (ArgMod Arg:$A))>;
3159 InstHexagon MI> {
3161 defm: Memopxi_base_pat <Load, Store, Oper, Arg, ArgMod, MI>;
3162 defm: Memopxi_add_pat <Load, Store, ImmPred, Oper, Arg, ArgMod, MI>;
3261 // --(15) Call -----------------------------------------------------------
3310 // --(16) Branch ---------------------------------------------------------
3320 def: Pat<(brcond (i1 (setne I1:$Pu, -1)), bb:$dst),
3328 // --(17) Misc -----------------------------------------------------------
3331 // Generate code of the form 'C2_muxii(cmpbgtui(Rdd, C-1),0,1)'
3342 // retval = (c-48) < 10 ? 1 : 0;
3345 // True if the immediate fits in an 7-bit unsigned field and is positive.
3401 // The declared return value of the store-locked intrinsics is i32, but