Lines Matching +full:mi +full:- +full:v
1 //===- SPIRVISelLowering.cpp - SPIR-V DAG Lowering Impl ---------*- C++ -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
24 #define DEBUG_TYPE "spirv-lower"
69 Info.align = Align(AlignOp->getZExtValue()); in getTgtMemIntrinsic()
72 cast<ConstantInt>(I.getOperand(AlignIdx - 1))->getZExtValue()); in getTgtMemIntrinsic()
75 // MVT::getVT(PtrTy->getElementType()); in getTgtMemIntrinsic()
108 SPIRVType *TypeInst = MRI->getVRegDef(OpReg); in getTypeReg()
109 return TypeInst && TypeInst->getOpcode() == SPIRV::OpFunctionParameter in getTypeReg()
110 ? TypeInst->getOperand(1).getReg() in getTypeReg()
118 Register NewReg = MRI->createGenericVirtualRegister(LLT::scalar(32)); in doInsertBitcast()
128 MRI->setRegClass(NewReg, &SPIRV::IDRegClass); in doInsertBitcast()
139 OpType->getOperand(1).getImm()); in createNewPtrType()
148 // Insert a bitcast before the instruction to keep SPIR-V code valid
155 MachineFunction *MF = I.getParent()->getParent(); in validatePtrTypes()
159 if (!ResType || !OpType || OpType->getOpcode() != SPIRV::OpTypePointer) in validatePtrTypes()
162 Register ElemTypeReg = OpType->getOperand(2).getReg(); in validatePtrTypes()
167 bool IsSameMF = MF == ResType->getParent()->getParent(); in validatePtrTypes()
173 // and we insert a bitcast before the instruction to keep SPIR-V code valid in validatePtrTypes()
189 MachineFunction *MF = I.getParent()->getParent(); in validateGroupWaitEventsPtr()
193 if (!OpType || OpType->getOpcode() != SPIRV::OpTypePointer) in validateGroupWaitEventsPtr()
195 SPIRVType *ElemType = GR.getSPIRVTypeForVReg(OpType->getOperand(2).getReg()); in validateGroupWaitEventsPtr()
196 if (!ElemType || ElemType->getOpcode() == SPIRV::OpTypeEvent) in validateGroupWaitEventsPtr()
198 // Insert a bitcast before the instruction to keep SPIR-V code valid. in validateGroupWaitEventsPtr()
199 LLVMContext &Context = MF->getFunction().getContext(); in validateGroupWaitEventsPtr()
210 MachineFunction *MF = I.getParent()->getParent(); in validateGroupAsyncCopyPtr()
214 if (!OpType || OpType->getOpcode() != SPIRV::OpTypePointer) in validateGroupAsyncCopyPtr()
216 SPIRVType *ElemType = GR.getSPIRVTypeForVReg(OpType->getOperand(2).getReg()); in validateGroupAsyncCopyPtr()
217 if (!ElemType || ElemType->getOpcode() != SPIRV::OpTypeStruct || in validateGroupAsyncCopyPtr()
218 ElemType->getNumOperands() != 2) in validateGroupAsyncCopyPtr()
220 // It's a structure-wrapper around another type with a single member field. in validateGroupAsyncCopyPtr()
222 GR.getSPIRVTypeForVReg(ElemType->getOperand(1).getReg()); in validateGroupAsyncCopyPtr()
225 unsigned MemberTypeOp = MemberType->getOpcode(); in validateGroupAsyncCopyPtr()
229 // It's a structure-wrapper around a valid type. Insert a bitcast before the in validateGroupAsyncCopyPtr()
230 // instruction to keep SPIR-V code valid. in validateGroupAsyncCopyPtr()
233 OpType->getOperand(1).getImm()); in validateGroupAsyncCopyPtr()
239 // Insert a bitcast before the function call instruction to keep SPIR-V code
252 if (FunDef->getOpcode() != SPIRV::OpFunction) in validateFunCallMachineDef()
255 for (FunDef = FunDef->getNextNode(); in validateFunCallMachineDef()
256 FunDef && FunDef->getOpcode() == SPIRV::OpFunctionParameter && in validateFunCallMachineDef()
258 FunDef = FunDef->getNextNode(), OpIdx++) { in validateFunCallMachineDef()
259 SPIRVType *DefPtrType = DefMRI->getVRegDef(FunDef->getOperand(1).getReg()); in validateFunCallMachineDef()
261 DefPtrType && DefPtrType->getOpcode() == SPIRV::OpTypePointer in validateFunCallMachineDef()
262 ? GR.getSPIRVTypeForVReg(DefPtrType->getOperand(2).getReg(), in validateFunCallMachineDef()
263 DefPtrType->getParent()->getParent()) in validateFunCallMachineDef()
272 GR.setCurrentFunc(*FunCall.getParent()->getParent()); in validateFunCallMachineDef()
293 MachineRegisterInfo *DefMRI = &FunDef->getParent()->getParent()->getRegInfo(); in validateFunCall()
307 &FunCall->getParent()->getParent()->getRegInfo(); in validateForwardCalls()
316 if (BaseTypeInst && BaseTypeInst->getOpcode() == SPIRV::OpTypePointer) { in validateAccessChain()
318 GR.getSPIRVTypeForVReg(BaseTypeInst->getOperand(2).getReg()); in validateAccessChain()
324 // to pre-IRTranslation passes eventually
336 for (MachineBasicBlock::iterator MBBI = MBB->begin(), MBBE = MBB->end(); in finalizeLowering()
338 MachineInstr &MI = *MBBI++; in finalizeLowering() local
339 switch (MI.getOpcode()) { in finalizeLowering()
360 validatePtrTypes(STI, MRI, GR, MI, 2, in finalizeLowering()
361 GR.getSPIRVTypeForVReg(MI.getOperand(0).getReg())); in finalizeLowering()
366 validatePtrTypes(STI, MRI, GR, MI, 0, in finalizeLowering()
367 GR.getSPIRVTypeForVReg(MI.getOperand(3).getReg())); in finalizeLowering()
371 validatePtrTypes(STI, MRI, GR, MI, 0, in finalizeLowering()
372 GR.getSPIRVTypeForVReg(MI.getOperand(1).getReg())); in finalizeLowering()
376 validateAccessChain(STI, MRI, GR, MI); in finalizeLowering()
379 if (MI.getNumOperands() == 4) in finalizeLowering()
380 validateAccessChain(STI, MRI, GR, MI); in finalizeLowering()
386 if (MI.getNumOperands() > 3) in finalizeLowering()
387 if (const Function *F = validateFunCall(STI, MRI, GR, MI)) in finalizeLowering()
388 GR.addForwardCall(F, &MI); in finalizeLowering()
393 validateForwardCalls(STI, MRI, GR, MI); in finalizeLowering()
396 // ensure that LLVM IR bitwise instructions result in logical SPIR-V in finalizeLowering()
400 if (GR.isScalarOrVectorOfType(MI.getOperand(1).getReg(), in finalizeLowering()
402 MI.setDesc(STI.getInstrInfo()->get(SPIRV::OpLogicalOr)); in finalizeLowering()
406 if (GR.isScalarOrVectorOfType(MI.getOperand(1).getReg(), in finalizeLowering()
408 MI.setDesc(STI.getInstrInfo()->get(SPIRV::OpLogicalAnd)); in finalizeLowering()
412 if (GR.isScalarOrVectorOfType(MI.getOperand(1).getReg(), in finalizeLowering()
414 MI.setDesc(STI.getInstrInfo()->get(SPIRV::OpLogicalNotEqual)); in finalizeLowering()
417 validateGroupAsyncCopyPtr(STI, MRI, GR, MI, 3); in finalizeLowering()
418 validateGroupAsyncCopyPtr(STI, MRI, GR, MI, 4); in finalizeLowering()
422 validateGroupWaitEventsPtr(STI, MRI, GR, MI); in finalizeLowering()
425 SPIRVType *Type = GR.getSPIRVTypeForVReg(MI.getOperand(1).getReg()); in finalizeLowering()
426 if (Type->getOpcode() != SPIRV::OpTypeInt && MI.getOperand(2).isImm() && in finalizeLowering()
427 MI.getOperand(2).getImm() == 0) { in finalizeLowering()
429 MI.setDesc(STI.getInstrInfo()->get(SPIRV::OpConstantNull)); in finalizeLowering()
430 for (unsigned i = MI.getNumOperands() - 1; i > 1; --i) in finalizeLowering()
431 MI.removeOperand(i); in finalizeLowering()