Lines Matching +full:mi +full:- +full:v
1 //===-- X86MCInstLower.cpp - Convert X86 MachineInstr to an MCInst --------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
58 static cl::opt<bool> EnableBranchHint("enable-branch-hint",
62 "branch-hint-probability-threshold",
68 /// X86MCInstLower - This class is used to lower an MachineInstr into an MCInst.
79 MCOperand LowerMachineOperand(const MachineInstr *MI,
81 void Lower(const MachineInstr *MI, MCInst &OutMI) const;
123 CodeEmitter->encodeInstruction(Inst, Code, Fixups, STI); in count()
134 emitX86Nops(OutStreamer, RequiredShadowSize - CurrentShadowSize, in emitShadowPadding()
135 &MF->getSubtarget<X86Subtarget>()); in emitShadowPadding()
140 OutStreamer->emitInstruction(Inst, getSubtargetInfo()); in EmitAndCountInstruction()
150 return AsmPrinter.MMI->getObjFileInfo<MachineModuleInfoMachO>(); in getMachOMMI()
153 /// GetSymbolFromOperand - Lower an MO_GlobalAddress or MO_ExternalSymbol
192 Sym = MO.getMBB()->getSymbol(); in GetSymbolFromOperand()
206 AsmPrinter.MMI->getObjFileInfo<MachineModuleInfoCOFF>(); in GetSymbolFromOperand()
223 !MO.getGlobal()->hasInternalLinkage()); in GetSymbolFromOperand()
319 AsmPrinter.OutStreamer->emitAssignment(Label, Expr); in LowerSymbolOperand()
338 MCOperand X86MCInstLower::LowerMachineOperand(const MachineInstr *MI, in LowerMachineOperand() argument
342 MI->print(errs()); in LowerMachineOperand()
405 void X86MCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const { in Lower() argument
406 OutMI.setOpcode(MI->getOpcode()); in Lower()
408 for (const MachineOperand &MO : MI->operands()) in Lower()
409 if (auto Op = LowerMachineOperand(MI, MO); Op.isValid()) in Lower()
413 if (X86::optimizeInstFromVEX3ToVEX2(OutMI, MI->getDesc()) || in Lower()
452 // CALL64r, CALL64pcrel32 - These instructions used to have in Lower()
481 // TAILJMPd, TAILJMPd64, TailJMPd_cc - Lower to the correct jump in Lower()
519 MI->findRegisterDefOperand(X86::EFLAGS, /*TRI=*/nullptr); in Lower()
520 if (!MF.getFunction().hasOptSize() && FlagDef && FlagDef->isDead()) in Lower()
530 const MachineInstr &MI) { in LowerTlsAddr() argument
534 MCContext &Ctx = OutStreamer->getContext(); in LowerTlsAddr()
537 switch (MI.getOpcode()) { in LowerTlsAddr()
559 MCInstLowering.GetSymbolFromOperand(MI.getOperand(3)), SRVK, Ctx); in LowerTlsAddr()
566 bool UseGot = MMI->getModule()->getRtLibUseGOT() && in LowerTlsAddr()
567 Ctx.getTargetOptions()->X86RelaxRelocations; in LowerTlsAddr()
571 MCInstLowering.GetSymbolFromOperand(MI.getOperand(3)), in LowerTlsAddr()
664 // target cpu. 15-bytes is the longest single NOP instruction, but some in emitNop()
667 if (Subtarget->is64Bit()) { in emitNop()
668 // FIXME: We can use NOOPL on 32-bit targets with FeatureNOPL, but the in emitNop()
670 if (Subtarget->hasFeature(X86::TuningFast7ByteNOP)) in emitNop()
672 else if (Subtarget->hasFeature(X86::TuningFast15ByteNOP)) in emitNop()
674 else if (Subtarget->hasFeature(X86::TuningFast11ByteNOP)) in emitNop()
678 } if (Subtarget->is32Bit()) in emitNop()
748 unsigned NumPrefixes = std::min(NumBytes - NopSize, 5U); in emitNop()
777 /// Emit the optimal amount of multi-byte nops on X86.
783 NumBytes -= emitNop(OS, NumBytes, Subtarget); in emitX86Nops()
788 void X86AsmPrinter::LowerSTATEPOINT(const MachineInstr &MI, in LowerSTATEPOINT() argument
790 assert(Subtarget->is64Bit() && "Statepoint currently only supports X86-64"); in LowerSTATEPOINT()
794 StatepointOpers SOpers(&MI); in LowerSTATEPOINT()
811 // symbol is to far away. (TODO: support non-relative addressing) in LowerSTATEPOINT()
819 // address is to far away. (TODO: support non-relative addressing) in LowerSTATEPOINT()
823 if (Subtarget->useIndirectThunkCalls()) in LowerSTATEPOINT()
838 OutStreamer->emitInstruction(CallInst, getSubtargetInfo()); in LowerSTATEPOINT()
843 auto &Ctx = OutStreamer->getContext(); in LowerSTATEPOINT()
845 OutStreamer->emitLabel(MILabel); in LowerSTATEPOINT()
846 SM.recordStatepoint(*MILabel, MI); in LowerSTATEPOINT()
859 MCSymbol *HandlerLabel = FaultingMI.getOperand(2).getMBB()->getSymbol(); in LowerFAULTING_OP()
863 auto &Ctx = OutStreamer->getContext(); in LowerFAULTING_OP()
865 OutStreamer->emitLabel(FaultingLabel); in LowerFAULTING_OP()
870 MCInst MI; in LowerFAULTING_OP() local
871 MI.setOpcode(Opcode); in LowerFAULTING_OP()
874 MI.addOperand(MCOperand::createReg(DefRegister)); in LowerFAULTING_OP()
879 MI.addOperand(Op); in LowerFAULTING_OP()
881 OutStreamer->AddComment("on-fault: " + HandlerLabel->getName()); in LowerFAULTING_OP()
882 OutStreamer->emitInstruction(MI, getSubtargetInfo()); in LowerFAULTING_OP()
885 void X86AsmPrinter::LowerFENTRY_CALL(const MachineInstr &MI, in LowerFENTRY_CALL() argument
887 bool Is64Bits = Subtarget->is64Bit(); in LowerFENTRY_CALL()
888 MCContext &Ctx = OutStreamer->getContext(); in LowerFENTRY_CALL()
898 void X86AsmPrinter::LowerKCFI_CHECK(const MachineInstr &MI) { in LowerKCFI_CHECK() argument
899 assert(std::next(MI.getIterator())->isCall() && in LowerKCFI_CHECK()
902 // Adjust the offset for patchable-function-prefix. X86InstrInfo::getNop() in LowerKCFI_CHECK()
903 // returns a 1-byte X86::NOOP, which means the offset is the same in in LowerKCFI_CHECK()
904 // bytes. This assumes that patchable-function-prefix is the same for all in LowerKCFI_CHECK()
906 const MachineFunction &MF = *MI.getMF(); in LowerKCFI_CHECK()
909 .getFnAttribute("patchable-function-prefix") in LowerKCFI_CHECK()
918 const Register AddrReg = MI.getOperand(0).getReg(); in LowerKCFI_CHECK()
919 const uint32_t Type = MI.getOperand(1).getImm(); in LowerKCFI_CHECK()
924 MCInstBuilder(X86::MOV32ri).addReg(TempReg).addImm(-MaskKCFIType(Type))); in LowerKCFI_CHECK()
931 .addImm(-(PrefixNops + 4)) in LowerKCFI_CHECK()
941 OutStreamer->emitLabel(Trap); in LowerKCFI_CHECK()
944 OutStreamer->emitLabel(Pass); in LowerKCFI_CHECK()
947 void X86AsmPrinter::LowerASAN_CHECK_MEMACCESS(const MachineInstr &MI) { in LowerASAN_CHECK_MEMACCESS() argument
948 // FIXME: Make this work on non-ELF. in LowerASAN_CHECK_MEMACCESS()
954 const auto &Reg = MI.getOperand(0).getReg(); in LowerASAN_CHECK_MEMACCESS()
955 ASanAccessInfo AccessInfo(MI.getOperand(1).getImm()); in LowerASAN_CHECK_MEMACCESS()
968 TM.getMCRegisterInfo()->getName(Reg.asMCReg())) in LowerASAN_CHECK_MEMACCESS()
980 void X86AsmPrinter::LowerPATCHABLE_OP(const MachineInstr &MI, in LowerPATCHABLE_OP() argument
986 auto NextMI = std::find_if(std::next(MI.getIterator()), in LowerPATCHABLE_OP()
987 MI.getParent()->end().getInstrIterator(), in LowerPATCHABLE_OP()
991 unsigned MinSize = MI.getOperand(0).getImm(); in LowerPATCHABLE_OP()
993 if (NextMI != MI.getParent()->end() && !NextMI->isInlineAsm()) { in LowerPATCHABLE_OP()
1001 CodeEmitter->encodeInstruction(MCI, Code, Fixups, getSubtargetInfo()); in LowerPATCHABLE_OP()
1005 if (MinSize == 2 && Subtarget->is32Bit() && in LowerPATCHABLE_OP()
1006 Subtarget->isTargetWindowsMSVC() && in LowerPATCHABLE_OP()
1007 (Subtarget->getCPU().empty() || Subtarget->getCPU() == "pentium3")) { in LowerPATCHABLE_OP()
1011 // This is only for 32-bit targets, when using /arch:IA32 or /arch:SSE. in LowerPATCHABLE_OP()
1012 OutStreamer->emitInstruction( in LowerPATCHABLE_OP()
1025 void X86AsmPrinter::LowerSTACKMAP(const MachineInstr &MI) { in LowerSTACKMAP() argument
1028 auto &Ctx = OutStreamer->getContext(); in LowerSTACKMAP()
1030 OutStreamer->emitLabel(MILabel); in LowerSTACKMAP()
1032 SM.recordStackMap(*MILabel, MI); in LowerSTACKMAP()
1033 unsigned NumShadowBytes = MI.getOperand(1).getImm(); in LowerSTACKMAP()
1039 void X86AsmPrinter::LowerPATCHPOINT(const MachineInstr &MI, in LowerPATCHPOINT() argument
1041 assert(Subtarget->is64Bit() && "Patchpoint currently only supports X86-64"); in LowerPATCHPOINT()
1047 auto &Ctx = OutStreamer->getContext(); in LowerPATCHPOINT()
1049 OutStreamer->emitLabel(MILabel); in LowerPATCHPOINT()
1050 SM.recordPatchPoint(*MILabel, MI); in LowerPATCHPOINT()
1052 PatchPointOpers opers(&MI); in LowerPATCHPOINT()
1057 // Check for null target. If target is non-null (i.e. is non-zero or is in LowerPATCHPOINT()
1077 // This is encoded with 12-13 bytes, depending on which register is used. in LowerPATCHPOINT()
1078 Register ScratchReg = MI.getOperand(ScratchIdx).getReg(); in LowerPATCHPOINT()
1087 if (Subtarget->useIndirectThunkCalls()) in LowerPATCHPOINT()
1098 emitX86Nops(*OutStreamer, NumBytes - EncodedBytes, Subtarget); in LowerPATCHPOINT()
1101 void X86AsmPrinter::LowerPATCHABLE_EVENT_CALL(const MachineInstr &MI, in LowerPATCHABLE_EVENT_CALL() argument
1103 assert(Subtarget->is64Bit() && "XRay custom events only supports X86-64"); in LowerPATCHABLE_EVENT_CALL()
1120 // nopw (2-byte nop) in LowerPATCHABLE_EVENT_CALL()
1125 // --- in LowerPATCHABLE_EVENT_CALL()
1128 OutStreamer->AddComment("# XRay Custom Event Log"); in LowerPATCHABLE_EVENT_CALL()
1129 OutStreamer->emitCodeAlignment(Align(2), &getSubtargetInfo()); in LowerPATCHABLE_EVENT_CALL()
1130 OutStreamer->emitLabel(CurSled); in LowerPATCHABLE_EVENT_CALL()
1132 // Use a two-byte `jmp`. This version of JMP takes an 8-bit relative offset as in LowerPATCHABLE_EVENT_CALL()
1135 OutStreamer->emitBinaryData("\xeb\x0f"); in LowerPATCHABLE_EVENT_CALL()
1138 // %rdx -- so we only work with those. in LowerPATCHABLE_EVENT_CALL()
1149 for (unsigned I = 0; I < MI.getNumOperands(); ++I) in LowerPATCHABLE_EVENT_CALL()
1150 if (auto Op = MCIL.LowerMachineOperand(&MI, MI.getOperand(I)); in LowerPATCHABLE_EVENT_CALL()
1168 for (unsigned I = 0; I < MI.getNumOperands(); ++I) in LowerPATCHABLE_EVENT_CALL()
1184 // Restore caller-saved and used registers. in LowerPATCHABLE_EVENT_CALL()
1185 for (unsigned I = sizeof UsedMask; I-- > 0;) in LowerPATCHABLE_EVENT_CALL()
1191 OutStreamer->AddComment("xray custom event end."); in LowerPATCHABLE_EVENT_CALL()
1195 // changed the absolute address to a PC-relative address. in LowerPATCHABLE_EVENT_CALL()
1196 recordSled(CurSled, MI, SledKind::CUSTOM_EVENT, 2); in LowerPATCHABLE_EVENT_CALL()
1199 void X86AsmPrinter::LowerPATCHABLE_TYPED_EVENT_CALL(const MachineInstr &MI, in LowerPATCHABLE_TYPED_EVENT_CALL() argument
1201 assert(Subtarget->is64Bit() && "XRay typed events only supports X86-64"); in LowerPATCHABLE_TYPED_EVENT_CALL()
1218 // nopw (2-byte nop) in LowerPATCHABLE_TYPED_EVENT_CALL()
1223 // --- in LowerPATCHABLE_TYPED_EVENT_CALL()
1226 OutStreamer->AddComment("# XRay Typed Event Log"); in LowerPATCHABLE_TYPED_EVENT_CALL()
1227 OutStreamer->emitCodeAlignment(Align(2), &getSubtargetInfo()); in LowerPATCHABLE_TYPED_EVENT_CALL()
1228 OutStreamer->emitLabel(CurSled); in LowerPATCHABLE_TYPED_EVENT_CALL()
1230 // Use a two-byte `jmp`. This version of JMP takes an 8-bit relative offset as in LowerPATCHABLE_TYPED_EVENT_CALL()
1233 OutStreamer->emitBinaryData("\xeb\x14"); in LowerPATCHABLE_TYPED_EVENT_CALL()
1235 // An x86-64 convention may place three arguments into %rcx, %rdx, and R8, in LowerPATCHABLE_TYPED_EVENT_CALL()
1248 for (unsigned I = 0; I < MI.getNumOperands(); ++I) in LowerPATCHABLE_TYPED_EVENT_CALL()
1249 if (auto Op = MCIL.LowerMachineOperand(&MI, MI.getOperand(I)); in LowerPATCHABLE_TYPED_EVENT_CALL()
1273 for (unsigned I = 0; I < MI.getNumOperands(); ++I) in LowerPATCHABLE_TYPED_EVENT_CALL()
1289 // Restore caller-saved and used registers. in LowerPATCHABLE_TYPED_EVENT_CALL()
1290 for (unsigned I = sizeof UsedMask; I-- > 0;) in LowerPATCHABLE_TYPED_EVENT_CALL()
1296 OutStreamer->AddComment("xray typed event end."); in LowerPATCHABLE_TYPED_EVENT_CALL()
1299 recordSled(CurSled, MI, SledKind::TYPED_EVENT, 2); in LowerPATCHABLE_TYPED_EVENT_CALL()
1302 void X86AsmPrinter::LowerPATCHABLE_FUNCTION_ENTER(const MachineInstr &MI, in LowerPATCHABLE_FUNCTION_ENTER() argument
1307 const Function &F = MF->getFunction(); in LowerPATCHABLE_FUNCTION_ENTER()
1308 if (F.hasFnAttribute("patchable-function-entry")) { in LowerPATCHABLE_FUNCTION_ENTER()
1310 if (F.getFnAttribute("patchable-function-entry") in LowerPATCHABLE_FUNCTION_ENTER()
1327 // mov %r10, <function id, 32-bit> // 6 bytes in LowerPATCHABLE_FUNCTION_ENTER()
1328 // call <relative offset, 32-bits> // 5 bytes in LowerPATCHABLE_FUNCTION_ENTER()
1331 OutStreamer->emitCodeAlignment(Align(2), &getSubtargetInfo()); in LowerPATCHABLE_FUNCTION_ENTER()
1332 OutStreamer->emitLabel(CurSled); in LowerPATCHABLE_FUNCTION_ENTER()
1334 // Use a two-byte `jmp`. This version of JMP takes an 8-bit relative offset as in LowerPATCHABLE_FUNCTION_ENTER()
1337 OutStreamer->emitBytes("\xeb\x09"); in LowerPATCHABLE_FUNCTION_ENTER()
1339 recordSled(CurSled, MI, SledKind::FUNCTION_ENTER, 2); in LowerPATCHABLE_FUNCTION_ENTER()
1342 void X86AsmPrinter::LowerPATCHABLE_RET(const MachineInstr &MI, in LowerPATCHABLE_RET() argument
1361 OutStreamer->emitCodeAlignment(Align(2), &getSubtargetInfo()); in LowerPATCHABLE_RET()
1362 OutStreamer->emitLabel(CurSled); in LowerPATCHABLE_RET()
1363 unsigned OpCode = MI.getOperand(0).getImm(); in LowerPATCHABLE_RET()
1366 for (auto &MO : drop_begin(MI.operands())) in LowerPATCHABLE_RET()
1367 if (auto Op = MCIL.LowerMachineOperand(&MI, MO); Op.isValid()) in LowerPATCHABLE_RET()
1369 OutStreamer->emitInstruction(Ret, getSubtargetInfo()); in LowerPATCHABLE_RET()
1371 recordSled(CurSled, MI, SledKind::FUNCTION_EXIT, 2); in LowerPATCHABLE_RET()
1374 void X86AsmPrinter::LowerPATCHABLE_TAIL_CALL(const MachineInstr &MI, in LowerPATCHABLE_TAIL_CALL() argument
1377 TC.setOpcode(convertTailJumpOpcode(MI.getOperand(0).getImm())); in LowerPATCHABLE_TAIL_CALL()
1379 auto TCOperands = drop_begin(MI.operands()); in LowerPATCHABLE_TAIL_CALL()
1399 static_cast<X86::CondCode>(MI.getOperand(2).getImm())))); in LowerPATCHABLE_TAIL_CALL()
1414 OutStreamer->emitCodeAlignment(Align(2), &getSubtargetInfo()); in LowerPATCHABLE_TAIL_CALL()
1415 OutStreamer->emitLabel(CurSled); in LowerPATCHABLE_TAIL_CALL()
1418 // Use a two-byte `jmp`. This version of JMP takes an 8-bit relative offset as in LowerPATCHABLE_TAIL_CALL()
1421 OutStreamer->emitBytes("\xeb\x09"); in LowerPATCHABLE_TAIL_CALL()
1423 OutStreamer->emitLabel(Target); in LowerPATCHABLE_TAIL_CALL()
1424 recordSled(CurSled, MI, SledKind::TAIL_CALL, 2); in LowerPATCHABLE_TAIL_CALL()
1428 OutStreamer->AddComment("TAILCALL"); in LowerPATCHABLE_TAIL_CALL()
1430 if (auto Op = MCIL.LowerMachineOperand(&MI, MO); Op.isValid()) in LowerPATCHABLE_TAIL_CALL()
1432 OutStreamer->emitInstruction(TC, getSubtargetInfo()); in LowerPATCHABLE_TAIL_CALL()
1435 OutStreamer->emitLabel(FallthroughLabel); in LowerPATCHABLE_TAIL_CALL()
1442 const MachineBasicBlock *MBB = MBBI->getParent(); in PrevCrossBBInst()
1443 while (MBBI == MBB->begin()) { in PrevCrossBBInst()
1444 if (MBB == &MBB->getParent()->front()) in PrevCrossBBInst()
1446 MBB = MBB->getPrevNode(); in PrevCrossBBInst()
1447 MBBI = MBB->end(); in PrevCrossBBInst()
1449 --MBBI; in PrevCrossBBInst()
1453 static unsigned getSrcIdx(const MachineInstr* MI, unsigned SrcIdx) { in getSrcIdx() argument
1454 if (X86II::isKMasked(MI->getDesc().TSFlags)) { in getSrcIdx()
1457 if (X86II::isKMergeMasked(MI->getDesc().TSFlags)) { in getSrcIdx()
1465 static void printDstRegisterName(raw_ostream &CS, const MachineInstr *MI, in printDstRegisterName() argument
1467 const MachineOperand &DstOp = MI->getOperand(0); in printDstRegisterName()
1473 if (X86II::isKMasked(MI->getDesc().TSFlags)) { in printDstRegisterName()
1474 const MachineOperand &WriteMaskOp = MI->getOperand(SrcOpIdx - 1); in printDstRegisterName()
1477 if (!X86II::isKMergeMasked(MI->getDesc().TSFlags)) { in printDstRegisterName()
1490 ShuffleMask[i] -= e; in printShuffleMask()
1519 --i; // For loop increments element #. in printShuffleMask()
1523 static std::string getShuffleComment(const MachineInstr *MI, unsigned SrcOp1Idx, in getShuffleComment() argument
1527 const MachineOperand &SrcOp1 = MI->getOperand(SrcOp1Idx); in getShuffleComment()
1528 const MachineOperand &SrcOp2 = MI->getOperand(SrcOp2Idx); in getShuffleComment()
1537 printDstRegisterName(CS, MI, SrcOp1Idx); in getShuffleComment()
1550 // print multi-word constant as (w0,w1) in printConstant()
1577 printConstant(CI->getValue(), CS, PrintZero); in printConstant()
1579 printConstant(CF->getValueAPF(), CS, PrintZero); in printConstant()
1581 Type *EltTy = CDS->getElementType(); in printConstant()
1582 bool IsInteger = EltTy->isIntegerTy(); in printConstant()
1583 bool IsFP = EltTy->isHalfTy() || EltTy->isFloatTy() || EltTy->isDoubleTy(); in printConstant()
1584 unsigned EltBits = EltTy->getPrimitiveSizeInBits(); in printConstant()
1585 unsigned E = std::min(BitWidth / EltBits, CDS->getNumElements()); in printConstant()
1591 printConstant(CDS->getElementAsAPInt(I), CS, PrintZero); in printConstant()
1593 printConstant(CDS->getElementAsAPFloat(I), CS, PrintZero); in printConstant()
1598 unsigned EltBits = CV->getType()->getScalarSizeInBits(); in printConstant()
1599 unsigned E = std::min(BitWidth / EltBits, CV->getNumOperands()); in printConstant()
1604 printConstant(CV->getOperand(I), EltBits, CS, PrintZero); in printConstant()
1611 static void printZeroUpperMove(const MachineInstr *MI, MCStreamer &OutStreamer, in printZeroUpperMove() argument
1614 unsigned SrcIdx = getSrcIdx(MI, 1); in printZeroUpperMove()
1618 printDstRegisterName(CS, MI, SrcIdx); in printZeroUpperMove()
1621 if (auto *C = X86::getConstantFromPool(*MI, SrcIdx)) { in printZeroUpperMove()
1630 return; // early-out in printZeroUpperMove()
1638 static void printBroadcast(const MachineInstr *MI, MCStreamer &OutStreamer, in printBroadcast() argument
1640 unsigned SrcIdx = getSrcIdx(MI, 1); in printBroadcast()
1641 if (auto *C = X86::getConstantFromPool(*MI, SrcIdx)) { in printBroadcast()
1644 printDstRegisterName(CS, MI, SrcIdx); in printBroadcast()
1656 static bool printExtend(const MachineInstr *MI, MCStreamer &OutStreamer, in printExtend() argument
1658 unsigned SrcIdx = getSrcIdx(MI, 1); in printExtend()
1659 auto *C = X86::getConstantFromPool(*MI, SrcIdx); in printExtend()
1660 if (C && C->getType()->getScalarSizeInBits() == unsigned(SrcEltBits)) { in printExtend()
1662 int NumElts = CDS->getNumElements(); in printExtend()
1665 printDstRegisterName(CS, MI, SrcIdx); in printExtend()
1670 if (CDS->getElementType()->isIntegerTy()) { in printExtend()
1671 APInt Elt = CDS->getElementAsAPInt(i); in printExtend()
1685 static void printSignExtend(const MachineInstr *MI, MCStreamer &OutStreamer, in printSignExtend() argument
1687 printExtend(MI, OutStreamer, SrcEltBits, DstEltBits, true); in printSignExtend()
1689 static void printZeroExtend(const MachineInstr *MI, MCStreamer &OutStreamer, in printZeroExtend() argument
1691 if (printExtend(MI, OutStreamer, SrcEltBits, DstEltBits, false)) in printZeroExtend()
1697 printDstRegisterName(CS, MI, getSrcIdx(MI, 1)); in printZeroExtend()
1701 unsigned Width = X86::getVectorRegisterWidth(MI->getDesc().operands()[0]); in printZeroExtend()
1710 void X86AsmPrinter::EmitSEHInstruction(const MachineInstr *MI) { in EmitSEHInstruction() argument
1711 assert(MF->hasWinCFI() && "SEH_ instruction in function without WinCFI?"); in EmitSEHInstruction()
1715 // Use the .cv_fpo directives if we're emitting CodeView on 32-bit x86. in EmitSEHInstruction()
1718 static_cast<X86TargetStreamer *>(OutStreamer->getTargetStreamer()); in EmitSEHInstruction()
1719 switch (MI->getOpcode()) { in EmitSEHInstruction()
1721 XTS->emitFPOPushReg(MI->getOperand(0).getImm()); in EmitSEHInstruction()
1724 XTS->emitFPOStackAlloc(MI->getOperand(0).getImm()); in EmitSEHInstruction()
1727 XTS->emitFPOStackAlign(MI->getOperand(0).getImm()); in EmitSEHInstruction()
1730 assert(MI->getOperand(1).getImm() == 0 && in EmitSEHInstruction()
1732 XTS->emitFPOSetFrame(MI->getOperand(0).getImm()); in EmitSEHInstruction()
1735 XTS->emitFPOEndPrologue(); in EmitSEHInstruction()
1749 switch (MI->getOpcode()) { in EmitSEHInstruction()
1751 OutStreamer->emitWinCFIPushReg(MI->getOperand(0).getImm()); in EmitSEHInstruction()
1755 OutStreamer->emitWinCFISaveReg(MI->getOperand(0).getImm(), in EmitSEHInstruction()
1756 MI->getOperand(1).getImm()); in EmitSEHInstruction()
1760 OutStreamer->emitWinCFISaveXMM(MI->getOperand(0).getImm(), in EmitSEHInstruction()
1761 MI->getOperand(1).getImm()); in EmitSEHInstruction()
1765 OutStreamer->emitWinCFIAllocStack(MI->getOperand(0).getImm()); in EmitSEHInstruction()
1769 OutStreamer->emitWinCFISetFrame(MI->getOperand(0).getImm(), in EmitSEHInstruction()
1770 MI->getOperand(1).getImm()); in EmitSEHInstruction()
1774 OutStreamer->emitWinCFIPushFrame(MI->getOperand(0).getImm()); in EmitSEHInstruction()
1778 OutStreamer->emitWinCFIEndProlog(); in EmitSEHInstruction()
1786 static void addConstantComments(const MachineInstr *MI, in addConstantComments() argument
1788 switch (MI->getOpcode()) { in addConstantComments()
1804 unsigned SrcIdx = getSrcIdx(MI, 1); in addConstantComments()
1805 if (auto *C = X86::getConstantFromPool(*MI, SrcIdx + 1)) { in addConstantComments()
1806 unsigned Width = X86::getVectorRegisterWidth(MI->getDesc().operands()[0]); in addConstantComments()
1810 OutStreamer.AddComment(getShuffleComment(MI, SrcIdx, SrcIdx, Mask)); in addConstantComments()
1826 unsigned SrcIdx = getSrcIdx(MI, 1); in addConstantComments()
1827 if (auto *C = X86::getConstantFromPool(*MI, SrcIdx + 1)) { in addConstantComments()
1828 unsigned Width = X86::getVectorRegisterWidth(MI->getDesc().operands()[0]); in addConstantComments()
1832 OutStreamer.AddComment(getShuffleComment(MI, SrcIdx, SrcIdx, Mask)); in addConstantComments()
1847 unsigned SrcIdx = getSrcIdx(MI, 1); in addConstantComments()
1848 if (auto *C = X86::getConstantFromPool(*MI, SrcIdx + 1)) { in addConstantComments()
1849 unsigned Width = X86::getVectorRegisterWidth(MI->getDesc().operands()[0]); in addConstantComments()
1853 OutStreamer.AddComment(getShuffleComment(MI, SrcIdx, SrcIdx, Mask)); in addConstantComments()
1862 assert(MI->getNumOperands() >= (3 + X86::AddrNumOperands + 1) && in addConstantComments()
1865 const MachineOperand &CtrlOp = MI->getOperand(MI->getNumOperands() - 1); in addConstantComments()
1870 switch (MI->getOpcode()) { in addConstantComments()
1876 if (auto *C = X86::getConstantFromPool(*MI, 3)) { in addConstantComments()
1877 unsigned Width = X86::getVectorRegisterWidth(MI->getDesc().operands()[0]); in addConstantComments()
1881 OutStreamer.AddComment(getShuffleComment(MI, 1, 2, Mask)); in addConstantComments()
1887 if (auto *C = X86::getConstantFromPool(*MI, 3)) { in addConstantComments()
1888 unsigned Width = X86::getVectorRegisterWidth(MI->getDesc().operands()[0]); in addConstantComments()
1892 OutStreamer.AddComment(getShuffleComment(MI, 1, 2, Mask)); in addConstantComments()
1898 if (auto *C = X86::getConstantFromPool(*MI, 1)) { in addConstantComments()
1901 const MachineOperand &DstOp = MI->getOperand(0); in addConstantComments()
1904 CS << "0x" << toString(CF->getValueAPF().bitcastToAPInt(), 16, false); in addConstantComments()
1916 INSTR_CASE(V, Instr, , ) /* AVX-128 */ \ in addConstantComments()
1917 INSTR_CASE(V, Instr, Y, ) /* AVX-256 */ \ in addConstantComments()
1918 INSTR_CASE(V, Instr, Z128, ) \ in addConstantComments()
1919 INSTR_CASE(V, Instr, Z128, k) \ in addConstantComments()
1920 INSTR_CASE(V, Instr, Z128, kz) \ in addConstantComments()
1921 INSTR_CASE(V, Instr, Z256, ) \ in addConstantComments()
1922 INSTR_CASE(V, Instr, Z256, k) \ in addConstantComments()
1923 INSTR_CASE(V, Instr, Z256, kz) \ in addConstantComments()
1924 INSTR_CASE(V, Instr, Z, ) \ in addConstantComments()
1925 INSTR_CASE(V, Instr, Z, k) \ in addConstantComments()
1926 INSTR_CASE(V, Instr, Z, kz) in addConstantComments()
1930 unsigned SrcIdx = getSrcIdx(MI, 1); in addConstantComments()
1931 if (auto *C = X86::getConstantFromPool(*MI, SrcIdx + 1)) { in addConstantComments()
1932 if (C->getType()->getScalarSizeInBits() == 8) { in addConstantComments()
1936 X86::getVectorRegisterWidth(MI->getDesc().operands()[0]); in addConstantComments()
1951 unsigned SrcIdx = getSrcIdx(MI, 1); in addConstantComments()
1952 if (auto *C = X86::getConstantFromPool(*MI, SrcIdx + 1)) { in addConstantComments()
1953 if (C->getType()->getScalarSizeInBits() == 16) { in addConstantComments()
1957 X86::getVectorRegisterWidth(MI->getDesc().operands()[0]); in addConstantComments()
1981 printZeroUpperMove(MI, OutStreamer, 64, 128, "mem[0],zero"); in addConstantComments()
1986 printZeroUpperMove(MI, OutStreamer, 16, 128, in addConstantComments()
1999 printZeroUpperMove(MI, OutStreamer, 32, 128, "mem[0],zero,zero,zero"); in addConstantComments()
2024 MOV_CASE(V, ) /* AVX-128 */ \ in addConstantComments()
2030 MOV_CASE(V, Y) /* AVX-256 */ \ in addConstantComments()
2043 printBroadcast(MI, OutStreamer, 1, 128); in addConstantComments()
2046 printBroadcast(MI, OutStreamer, 1, 256); in addConstantComments()
2049 printBroadcast(MI, OutStreamer, 1, 512); in addConstantComments()
2057 printBroadcast(MI, OutStreamer, 2, 128); in addConstantComments()
2063 printBroadcast(MI, OutStreamer, 4, 128); in addConstantComments()
2069 printBroadcast(MI, OutStreamer, 2, 256); in addConstantComments()
2079 printBroadcast(MI, OutStreamer, 2, 64); in addConstantComments()
2085 printBroadcast(MI, OutStreamer, 4, 64); in addConstantComments()
2089 printBroadcast(MI, OutStreamer, 8, 64); in addConstantComments()
2095 printBroadcast(MI, OutStreamer, 4, 32); in addConstantComments()
2101 printBroadcast(MI, OutStreamer, 8, 32); in addConstantComments()
2105 printBroadcast(MI, OutStreamer, 16, 32); in addConstantComments()
2109 printBroadcast(MI, OutStreamer, 8, 16); in addConstantComments()
2113 printBroadcast(MI, OutStreamer, 16, 16); in addConstantComments()
2116 printBroadcast(MI, OutStreamer, 32, 16); in addConstantComments()
2120 printBroadcast(MI, OutStreamer, 16, 8); in addConstantComments()
2124 printBroadcast(MI, OutStreamer, 32, 8); in addConstantComments()
2127 printBroadcast(MI, OutStreamer, 64, 8); in addConstantComments()
2135 MOVX_CASE(V, Ext, Type, , ) \ in addConstantComments()
2136 MOVX_CASE(V, Ext, Type, Y, ) \ in addConstantComments()
2137 MOVX_CASE(V, Ext, Type, Z128, ) \ in addConstantComments()
2138 MOVX_CASE(V, Ext, Type, Z128, k ) \ in addConstantComments()
2139 MOVX_CASE(V, Ext, Type, Z128, kz ) \ in addConstantComments()
2140 MOVX_CASE(V, Ext, Type, Z256, ) \ in addConstantComments()
2141 MOVX_CASE(V, Ext, Type, Z256, k ) \ in addConstantComments()
2142 MOVX_CASE(V, Ext, Type, Z256, kz ) \ in addConstantComments()
2143 MOVX_CASE(V, Ext, Type, Z, ) \ in addConstantComments()
2144 MOVX_CASE(V, Ext, Type, Z, k ) \ in addConstantComments()
2145 MOVX_CASE(V, Ext, Type, Z, kz ) in addConstantComments()
2148 printSignExtend(MI, OutStreamer, 8, 32); in addConstantComments()
2151 printSignExtend(MI, OutStreamer, 8, 64); in addConstantComments()
2154 printSignExtend(MI, OutStreamer, 8, 16); in addConstantComments()
2157 printSignExtend(MI, OutStreamer, 32, 64); in addConstantComments()
2160 printSignExtend(MI, OutStreamer, 16, 32); in addConstantComments()
2163 printSignExtend(MI, OutStreamer, 16, 64); in addConstantComments()
2167 printZeroExtend(MI, OutStreamer, 8, 32); in addConstantComments()
2170 printZeroExtend(MI, OutStreamer, 8, 64); in addConstantComments()
2173 printZeroExtend(MI, OutStreamer, 8, 16); in addConstantComments()
2176 printZeroExtend(MI, OutStreamer, 32, 64); in addConstantComments()
2179 printZeroExtend(MI, OutStreamer, 16, 32); in addConstantComments()
2182 printZeroExtend(MI, OutStreamer, 16, 64); in addConstantComments()
2187 void X86AsmPrinter::emitInstruction(const MachineInstr *MI) { in emitInstruction() argument
2189 // X86_MC::verifyInstructionPredicates(MI->getOpcode(), in emitInstruction()
2190 // Subtarget->getFeatureBits()); in emitInstruction()
2194 MF->getSubtarget<X86Subtarget>().getRegisterInfo(); in emitInstruction()
2196 if (MI->getOpcode() == X86::OR64rm) { in emitInstruction()
2197 for (auto &Opd : MI->operands()) { in emitInstruction()
2206 if (OutStreamer->isVerboseAsm()) in emitInstruction()
2207 addConstantComments(MI, *OutStreamer); in emitInstruction()
2211 if (MI->getAsmPrinterFlags() & X86::AC_EVEX_2_LEGACY) in emitInstruction()
2212 OutStreamer->AddComment("EVEX TO LEGACY Compression ", false); in emitInstruction()
2213 else if (MI->getAsmPrinterFlags() & X86::AC_EVEX_2_VEX) in emitInstruction()
2214 OutStreamer->AddComment("EVEX TO VEX Compression ", false); in emitInstruction()
2215 else if (MI->getAsmPrinterFlags() & X86::AC_EVEX_2_EVEX) in emitInstruction()
2216 OutStreamer->AddComment("EVEX TO EVEX Compression ", false); in emitInstruction()
2219 switch (MI->getOpcode()) { in emitInstruction()
2226 Register Reg = MI->getOperand(0).getReg(); in emitInstruction()
2227 OutStreamer->AddComment(StringRef("eh_return, addr: %") + in emitInstruction()
2233 OutStreamer->AddComment("CLEANUPRET"); in emitInstruction()
2239 OutStreamer->AddComment("CATCHRET"); in emitInstruction()
2246 // -fpatchable-function-entry=N,0. The entry MBB is guaranteed to be in emitInstruction()
2247 // non-empty. If MI is the initial ENDBR, place the in emitInstruction()
2251 MI == &MF->front().front()) { in emitInstruction()
2253 MCInstLowering.Lower(MI, Inst); in emitInstruction()
2256 OutStreamer->emitLabel(CurrentPatchableFunctionEntrySym); in emitInstruction()
2263 if (IndCSPrefix && MI->hasRegisterImplicitUseOperand(X86::R11)) in emitInstruction()
2276 OutStreamer->AddComment("TAILCALL"); in emitInstruction()
2287 return LowerTlsAddr(MCInstLowering, *MI); in emitInstruction()
2297 MCSymbol *PICBase = MF->getPICBaseSymbol(); in emitInstruction()
2305 MF->getSubtarget<X86Subtarget>().getFrameLowering(); in emitInstruction()
2306 bool hasFP = FrameLowering->hasFP(*MF); in emitInstruction()
2309 bool HasActiveDwarfFrame = OutStreamer->getNumFrameInfos() && in emitInstruction()
2310 !OutStreamer->getDwarfFrameInfos().back().End; in emitInstruction()
2312 int stackGrowth = -RI->getSlotSize(); in emitInstruction()
2315 OutStreamer->emitCFIAdjustCfaOffset(-stackGrowth); in emitInstruction()
2316 MF->getInfo<X86MachineFunctionInfo>()->setHasCFIAdjustCfa(true); in emitInstruction()
2320 OutStreamer->emitLabel(PICBase); in emitInstruction()
2324 MCInstBuilder(X86::POP32r).addReg(MI->getOperand(0).getReg())); in emitInstruction()
2327 OutStreamer->emitCFIAdjustCfaOffset(stackGrowth); in emitInstruction()
2334 if (MI->getOperand(2).getTargetFlags() != X86II::MO_GOT_ABSOLUTE_ADDRESS) in emitInstruction()
2341 // MYGLOBAL + (. - PICBASE) in emitInstruction()
2345 OutStreamer->emitLabel(DotSym); in emitInstruction()
2348 MCSymbol *OpSym = MCInstLowering.GetSymbolFromOperand(MI->getOperand(2)); in emitInstruction()
2352 MCSymbolRefExpr::create(MF->getPICBaseSymbol(), OutContext); in emitInstruction()
2359 .addReg(MI->getOperand(0).getReg()) in emitInstruction()
2360 .addReg(MI->getOperand(1).getReg()) in emitInstruction()
2365 return LowerSTATEPOINT(*MI, MCInstLowering); in emitInstruction()
2368 return LowerFAULTING_OP(*MI, MCInstLowering); in emitInstruction()
2371 return LowerFENTRY_CALL(*MI, MCInstLowering); in emitInstruction()
2374 return LowerPATCHABLE_OP(*MI, MCInstLowering); in emitInstruction()
2377 return LowerSTACKMAP(*MI); in emitInstruction()
2380 return LowerPATCHPOINT(*MI, MCInstLowering); in emitInstruction()
2383 return LowerPATCHABLE_FUNCTION_ENTER(*MI, MCInstLowering); in emitInstruction()
2386 return LowerPATCHABLE_RET(*MI, MCInstLowering); in emitInstruction()
2389 return LowerPATCHABLE_TAIL_CALL(*MI, MCInstLowering); in emitInstruction()
2392 return LowerPATCHABLE_EVENT_CALL(*MI, MCInstLowering); in emitInstruction()
2395 return LowerPATCHABLE_TYPED_EVENT_CALL(*MI, MCInstLowering); in emitInstruction()
2402 return LowerKCFI_CHECK(*MI); in emitInstruction()
2405 return LowerASAN_CHECK_MEMACCESS(*MI); in emitInstruction()
2422 EmitSEHInstruction(MI); in emitInstruction()
2426 assert(MF->hasWinCFI() && "SEH_ instruction in function without WinCFI?"); in emitInstruction()
2427 MachineBasicBlock::const_iterator MBBI(MI); in emitInstruction()
2435 if (MBBI->isCall() || !MBBI->isPseudo()) { in emitInstruction()
2436 if (MBBI->isCall()) in emitInstruction()
2449 .addImm(MI->getOperand(0).getImm()) in emitInstruction()
2453 if (IndCSPrefix && MI->hasRegisterImplicitUseOperand(X86::R11)) in emitInstruction()
2457 // Two instruction prefixes (2EH for branch not-taken and 3EH for branch in emitInstruction()
2463 MachineBasicBlock *DestBB = MI->getOperand(0).getMBB(); in emitInstruction()
2465 MBPI->getEdgeProbability(MI->getParent(), DestBB); in emitInstruction()
2474 MCInstLowering.Lower(MI, TmpInst); in emitInstruction()
2480 if (MI->isCall()) { in emitInstruction()
2487 OutStreamer->emitInstruction(TmpInst, getSubtargetInfo()); in emitInstruction()