Lines Matching +full:mi +full:- +full:v
1 //===-- HexagonIntrinsics.td - Instruction intrinsics ------*- tablegen -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // These intrinsic patterns are not auto-generated.
11 class T_R_pat <InstHexagon MI, Intrinsic IntID>
13 (MI I32:$Rs)>;
15 class T_RR_pat <InstHexagon MI, Intrinsic IntID>
17 (MI I32:$Rs, I32:$Rt)>;
19 class T_RP_pat <InstHexagon MI, Intrinsic IntID>
21 (MI I32:$Rs, I64:$Rt)>;
81 // Assembler mapped from Rd32=not(Rs32) to Rd32=sub(#-1,Rs32)
83 (A2_subri -1, I32:$Rs)>;
112 int64_t V = N->getSExtValue();
113 return CurDAG->getTargetConstant(V, SDLoc(N), MVT::i64);
118 // in the DAG, if the immediate was not a 64-bit value.
119 // The builtin for A2_tfrpi, on the other hand, takes a 32-bit value,
140 //===----------------------------------------------------------------------===//
142 //===----------------------------------------------------------------------===//
150 int32_t V = N->getSExtValue();
151 return CurDAG->getTargetConstant(V-2, SDLoc(N), MVT::i32);
155 int32_t V = N->getSExtValue();
156 return CurDAG->getTargetConstant(V-3, SDLoc(N), MVT::i32);
186 class T_stb_pat <InstHexagon MI, Intrinsic IntID, PatLeaf Val>
188 (MI I32:$Rs, I32:$Ru, Val:$Rt)>;
196 class T_stc_pat <InstHexagon MI, Intrinsic IntID, PatLeaf Imm, PatLeaf Val>
198 (MI I32:$Rs, Imm:$s, I32:$Ru, Val:$Rt)>;
206 multiclass MaskedStore <InstHexagon MI, Intrinsic IntID> {
208 (MI HvxQR:$src1, IntRegs:$src2, 0, HvxVR:$src3)>,
213 (MI HvxQR:$src1, IntRegs:$src2, 0, HvxVR:$src3)>,
245 int64_t v = (int64_t)(64 - N->getSExtValue());
246 return isUInt<3>(v);
250 int64_t v = (int64_t)(128 - N->getSExtValue());
251 return isUInt<3>(v);
255 int32_t Imm = N->getSExtValue();
256 return CurDAG->getTargetConstant(64 - Imm, SDLoc(N), MVT::i32);
260 int32_t Imm = N->getSExtValue();
261 return CurDAG->getTargetConstant(128 - Imm, SDLoc(N), MVT::i32);
288 multiclass T_VI_pat <InstHexagon MI, Intrinsic IntID> {
290 (MI HvxVR:$src1, HvxVR:$src1, u3_0ImmPred:$src2)>,
294 (MI HvxVR:$src1, HvxVR:$src1, u3_0ImmPred:$src2)>,
298 multiclass T_VI_inv_pat <InstHexagon MI, Intrinsic IntID> {
300 (MI HvxVR:$src1, HvxVR:$src1,
305 (MI HvxVR:$src1, HvxVR:$src1, (SUB_128_VAL u3_128_ImmPred:$src2))>,
309 multiclass T_VVI_pat <InstHexagon MI, Intrinsic IntID> {
311 (MI HvxVR:$src1, HvxVR:$src2, u3_0ImmPred:$src3)>,
316 (MI HvxVR:$src1, HvxVR:$src2,
321 multiclass T_VVI_inv_pat <InstHexagon MI, Intrinsic IntID> {
323 (MI HvxVR:$src1, HvxVR:$src2,
329 (MI HvxVR:$src1, HvxVR:$src2,
334 multiclass T_VVR_pat <InstHexagon MI, Intrinsic IntID> {
336 (MI HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>,
341 (MI HvxVR:$src1, HvxVR:$src2,
369 multiclass T_VP_pat<InstHexagon MI, Intrinsic IntID> {
371 (MI HvxVR:$Vu, DoubleRegs:$Rt)>;
374 (MI HvxVR:$Vu, DoubleRegs:$Rt)>;
377 multiclass T_WVP_pat<InstHexagon MI, Intrinsic IntID> {
379 (MI HvxWR:$Vx, HvxVR:$Vu, DoubleRegs:$Rt)>;
382 (MI HvxWR:$Vx, HvxVR:$Vu, DoubleRegs:$Rt)>;
395 multiclass T_pRI_pat<InstHexagon MI, Intrinsic IntID> {
397 (MI PredRegs:$P, IntRegs:$R, imm:$s)>;
400 (MI PredRegs:$P, IntRegs:$R, imm:$s)>;
403 multiclass T_pRM_pat<InstHexagon MI, Intrinsic IntID> {
405 (MI PredRegs:$P, IntRegs:$R, ModRegs:$M)>;
408 (MI PredRegs:$P, IntRegs:$R, ModRegs:$M)>;
427 multiclass T_pRIV_pat<InstHexagon MI, Intrinsic IntID> {
428 def: Pat<(IntID PredRegs:$P, IntRegs:$R, timm:$s, HvxVR:$V),
429 (MI PredRegs:$P, IntRegs:$R, imm:$s, HvxVR:$V)>;
431 PredRegs:$P, IntRegs:$R, timm:$s, HvxVR:$V),
432 (MI PredRegs:$P, IntRegs:$R, imm:$s, HvxVR:$V)>;
435 multiclass T_pRMV_pat<InstHexagon MI, Intrinsic IntID> {
436 def: Pat<(IntID PredRegs:$P, IntRegs:$R, ModRegs:$M, HvxVR:$V),
437 (MI PredRegs:$P, IntRegs:$R, ModRegs:$M, HvxVR:$V)>;
439 PredRegs:$P, IntRegs:$R, ModRegs:$M, HvxVR:$V),
440 (MI PredRegs:$P, IntRegs:$R, ModRegs:$M, HvxVR:$V)>;