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/freebsd/sys/modules/ossl/
H A DMakefile19 aes-armv4.S \
20 bsaes-armv7.S \
21 chacha-armv4.S \
22 ghash-armv4.S \
23 poly1305-armv4.S \
24 sha1-armv4-large.S \
25 sha256-armv4.S \
26 sha512-armv4.S \
31 chacha-armv8.S \
32 chacha-armv8-sve.S \
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/freebsd/sys/contrib/device-tree/Bindings/arm/nuvoton/
H A Dnuvoton,ma35d1.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Nuvoton MA35 series SoC based platforms
10 - Jacky Huang <ychuang3@nuvoton.com>
13 Boards with an ARMv8 based Nuvoton MA35 series SoC shall have
22 - description: MA35D1 based boards
24 - enum:
25 - nuvoton,ma35d1-iot
26 - nuvoton,ma35d1-som
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/freebsd/sys/arm64/conf/
H A Dstd.dev3 options PCI_HP # PCI-Express native HotPlug
4 options PCI_IOV # PCI SR-IOV support
20 options NVME_USE_NVD=0 # prefer the cam(4) based nda(4) driver
36 device armv8crypto # ARMv8 OpenCrypto module
56 device armv8_rng # Armv8.5 rndr RNG
76 # PCI/PCI-X/PCIe Ethernet NICs that use iflib infrastructure
105 device umass # Disks/Mass storage - Requires scbus and da
120 device mmio_sram # Generic on-chip SRAM
H A DNOTES2 # NOTES -- Lines that can be cut/pasted into kernel and hints configs.
25 makeoptions DEBUG=-g # Build kernel with gdb(1) debug symbols
30 options VFP # Floating-point support
69 # Microsoft Hyper-V
76 device armv8crypto # ARMv8 OpenCrypto module
80 device al_pci # Annapurna Alpine PCI-E
81 options PCI_HP # PCI-Express native HotPlug
82 options PCI_IOV # PCI SR-IOV support
99 device e6000sw # Marvell mv88e6085 based switches
102 # Broadcom MPT Fusion, version 4, is 64-bit only
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/freebsd/sys/contrib/device-tree/Bindings/arm/
H A Dmicrochip,sparx5.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lars Povlsen <lars.povlsen@microchip.com>
13 The Microchip Sparx5 SoC is a ARMv8-based used in a family of
14 gigabit TSN-capable gigabit switches.
16 The SparX-5 Ethernet switch family provides a rich set of switching
17 features such as advanced TCAM-based VLAN and QoS processing
19 TCAM-based frame processing using versatile content aware processor
27 - description: The Sparx5 pcb125 board is a modular board,
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H A Dcoresight-cpu-debug.txt3 CoreSight CPU debug component are compliant with the ARMv8 architecture
5 external debug module is mainly used for two modes: self-hosted debug and
8 debug module provides sample-based profiling extension, which can be used
14 - compatible : should be "arm,coresight-cpu-debug"; supplemented with
18 - reg : physical base address and length of the register set.
20 - clocks : the clock associated to this component.
22 - clock-names : the name of the clock referenced by the code. Since we are
29 - cpu : the CPU phandle the debug module is affined to. Do not assume it
34 - power-domains: a phandle to the debug power domain. We use "power-domains"
44 compatible = "arm,coresight-cpu-debug","arm,primecell";
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H A Darm,coresight-cpu-debug.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/arm/arm,coresight-cpu-debug.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Mathieu Poirier <mathieu.poirier@linaro.org>
11 - Mike Leach <mike.leach@linaro.org>
12 - Leo Yan <leo.yan@linaro.org>
13 - Suzuki K Poulose <suzuki.poulose@arm.com>
16 CoreSight CPU debug component are compliant with the ARMv8 architecture
18 external debug module is mainly used for two modes: self-hosted debug and
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H A Dcpus.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
21 with updates for 32-bit and 64-bit ARM systems provided in this document.
30 - square brackets define bitfields, eg reg[7:0] value of the bitfield in
51 On ARM 11 MPcore based systems this property is
59 On 32-bit ARM v7 or later systems this property is
68 On ARM v8 64-bit systems this property is required
71 * If cpus node's #address-cells property is set to 2
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/freebsd/contrib/llvm-project/clang/lib/Basic/Targets/
H A DAArch64.cpp1 //===--- AArch64.cpp - Implement AArch64 target feature support -----------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
70 } else if (ArchInfo->Version.getMajor() == 8) { in setArchFeatures()
71 if (ArchInfo->Version.getMinor() >= 7u) { in setArchFeatures()
74 if (ArchInfo->Version.getMinor() >= 6u) { in setArchFeatures()
78 if (ArchInfo->Version.getMinor() >= 5u) { in setArchFeatures()
86 if (ArchInfo->Version.getMinor() >= 4u) { in setArchFeatures()
91 if (ArchInfo->Version.getMinor() >= 3u) { in setArchFeatures()
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H A DARM.cpp1 //===--- ARM.cpp - Implement ARM target feature support -------------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
47 ? "E-m:o-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" in setABIAAPCS()
48 : "e-m:o-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64", in setABIAAPCS()
53 "-m:w" in setABIAAPCS()
54 "-p:32:32" in setABIAAPCS()
55 "-Fi8" in setABIAAPCS()
56 "-i64:64" in setABIAAPCS()
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/freebsd/sys/crypto/armv8/
H A Darmv8_crypto.c1 /*-
2 * Copyright (c) 2005-2008 Pawel Jakub Dawidek <pjd@FreeBSD.org>
8 * Portions of this software were developed by John-Mark Gurney
38 * This is based on the aesni code.
58 #include <crypto/armv8/armv8_crypto.h>
69 MALLOC_DEFINE(M_ARMV8_CRYPTO, "armv8_crypto", "ARMv8 Crypto Data");
78 panic("ARMv8 crypto: could not attach"); in armv8_crypto_identify()
92 device_set_desc(dev, "AES-CBC,AES-XTS"); in armv8_crypto_probe()
96 device_set_desc(dev, "AES-CBC,AES-XTS,AES-GCM"); in armv8_crypto_probe()
121 sc->has_pmul = true; in armv8_crypto_attach()
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/freebsd/sys/arm/arm/
H A Dgeneric_timer.c1 /*-
2 * SPDX-License-Identifier: BSD-3-Clause
8 * Based on mpcore_timer.c developed by Ben Gray <ben.r.gray@gmail.com>
36 * Cortex-A7, Cortex-A15, ARMv8 and later Generic Timer
131 .name = "sec-phys",
146 .name = "hyp-phys",
151 .name = "hyp-virt",
236 * Read the self-syncronized counter. These cannot be read speculatively so
303 if (arm_tmr_sc->physical_user) { in setup_user_access()
328 if (reg < nitems(frame->tf_x)) { in cntpct_handler()
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/freebsd/sys/crypto/openssl/aarch64/
H A Decp_sm2p256-armv8.S1 /* Do not modify. This file is auto-generated from ecp_sm2p256-armv8.pl. */
3 .arch armv8-a
43 .size bn_rshift1,.-bn_rshift1
68 .size bn_sub,.-bn_sub
112 .size ecp_sm2p256_div_by_2,.-ecp_sm2p256_div_by_2
156 .size ecp_sm2p256_div_by_2_mod_ord,.-ecp_sm2p256_div_by_2_mod_ord
232 .size ecp_sm2p256_mul_by_3,.-ecp_sm2p256_mul_by_3
272 // Select based on carry
282 .size ecp_sm2p256_add,.-ecp_sm2p256_add
322 // Select based on carry
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/freebsd/sys/contrib/device-tree/Bindings/interrupt-controller/
H A Darm,gic-v3.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/arm,gic-v3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marc Zyngier <maz@kernel.org>
15 Software Generated Interrupts (SGI), and Locality-specific Peripheral
19 - $ref: /schemas/interrupt-controller.yaml#
24 - items:
25 - enum:
26 - qcom,msm8996-gic-v3
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/freebsd/contrib/unbound/contrib/android/
H A Dsetenv_android.sh6 # Based upon OpenSSL's setenv-android.sh by TH, JW, and SM.
16 if [ -z "$ANDROID_API" ]; then
21 if [ -z "$ANDROID_CPU" ]; then
26 if [ ! -d "$ANDROID_NDK_ROOT" ]; then
32 # cryptest-android.sh may run this script without sourcing.
34 echo "setenv-android.sh is usually sourced, but not this time."
39 # Need to set THIS_HOST to darwin-x86_64, linux-x86_64,
40 # windows, or windows-x86_64
42 if [[ "$(uname -s | grep -i -c darwin)" -ne 0 ]]; then
43 THIS_HOST=darwin-x86_64
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/freebsd/contrib/llvm-project/llvm/include/llvm/TargetParser/
H A DAArch64TargetParser.h1 //===-- AArch64TargetParser - Parser for AArch64 features -------*- C++ -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
42 // Each ArchExtKind correponds directly to a possible -target-feature.
48 // Represents an extension that can be enabled with -march=<arch>+<extension>.
53 StringRef UserVisibleName; // Human readable name used in -march, -cpu
61 StringRef PosTargetFeature; // -target-feature/-mattr enable string,
63 StringRef NegTargetFeature; // -target-feature/-mattr disable string,
64 // e.g. "-spe".
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/freebsd/contrib/llvm-project/llvm/lib/TargetParser/
H A DARMTargetParser.cpp1 //===-- ARMTargetParser - Parser for ARM target features --------*- C++ -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
165 // We have to specify the + and - versions of the name in full so in getFPUFeatures()
172 {"+vfp2", "-vfp2", FPUVersion::VFPV2, FPURestriction::D16}, in getFPUFeatures()
173 {"+vfp2sp", "-vfp2sp", FPUVersion::VFPV2, FPURestriction::SP_D16}, in getFPUFeatures()
174 {"+vfp3", "-vfp3", FPUVersion::VFPV3, FPURestriction::None}, in getFPUFeatures()
175 {"+vfp3d16", "-vfp3d16", FPUVersion::VFPV3, FPURestriction::D16}, in getFPUFeatures()
176 {"+vfp3d16sp", "-vfp3d16sp", FPUVersion::VFPV3, FPURestriction::SP_D16}, in getFPUFeatures()
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/freebsd/contrib/unbound/contrib/ios/
H A Dsetenv_ios.sh6 # Based upon OpenSSL's setenv-ios.sh by TH, JW, and SM.
16 # mostly vice-versa). Nowadays we need it set for us because Apple
17 # platforms can be either 32-bit or 64-bit.
19 if [ -z "$IOS_SDK" ]; then
24 if [ -z "$IOS_CPU" ]; then
29 # cryptest-ios.sh may run this script without sourcing.
31 echo "setenv-ios.sh is usually sourced, but not this time."
54 if [[ "$IOS_CPU" == "aarch64" || "$IOS_CPU" == "armv8"* ]] ; then
64 # xxx-version-min=n lower. For example, Xcode 6 can use
65 # -miphoneos-version-min=5.
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/freebsd/contrib/llvm-project/clang/lib/Driver/ToolChains/Arch/
H A DARM.cpp1 //===--- ARM.cpp - ARM (not AArch64) Helpers for Tools ----------*- C++ -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
29 // True if M-profile.
36 // can be overridden by the pseudo-target flags '-mlittle-endian'/'-EL' and
37 // '-mbig-endian'/'-EB'. Unlike other targets the flag does not result in a
42 return !A->getOption().matches(options::OPT_mlittle_endian); in isARMBigEndian()
49 // True if A-profile.
59 CPU = A->getValue(); in getARMArchCPUFromArgs()
61 Arch = A->getValue(); in getARMArchCPUFromArgs()
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/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMSubtarget.cpp1 //===-- ARMSubtarget.cpp - ARM Subtarget Information ----------------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
43 #define DEBUG_TYPE "arm-subtarget"
50 UseFusedMulOps("arm-use-mulops",
60 cl::values(clEnumValN(DefaultIT, "arm-default-it",
62 clEnumValN(RestrictedIT, "arm-restrict-it",
65 /// ForceFastISel - Use the fast-isel, even for subtargets where it is not
68 ForceFastISel("arm-force-fast-isel",
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/freebsd/share/mk/
H A Dbsd.cpu.mk34 CPUTYPE = skylake-avx512
35 . elif ${CPUTYPE} == "core-avx2"
37 . elif ${CPUTYPE} == "core-avx-i"
39 . elif ${CPUTYPE} == "corei7-avx"
65 . elif ${CPUTYPE} == "p-m"
66 CPUTYPE = pentium-m
72 CPUTYPE = pentium-mmx
83 # http://gcc.gnu.org/onlinedocs/gcc/ARM-Options.html
84 # http://gcc.gnu.org/onlinedocs/gcc/RS-6000-and-PowerPC-Options.html
85 # http://gcc.gnu.org/onlinedocs/gcc/SPARC-Options.html
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/freebsd/sys/contrib/openzfs/man/man4/
H A Dzfs.41 .\" SPDX-License-Identifier: CDDL-1.0
11 .\" usr/src/OPENSOLARIS.LICENSE or https://opensource.org/licenses/CDDL-1.0.
31 .Bl -tag -width Ds
76 the array is dynamically sized based on total system memory.
98 Turbo L2ARC warm-up.
175 Percent of ARC size allowed for L2ARC-only headers.
248 of a top-level vdev before moving on to the next top-level vdev.
251 Enable metaslab groups biasing based on their over- or under-utilization
257 Controls metaslab groups biasing based on their write performance.
260 Setting to 1 equals to 2 if the pool is write-bound or 0 otherwise.
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/freebsd/sys/contrib/zlib/
H A Dcrc32.c1 /* crc32.c -- compute the CRC-32 of a data stream
2 * Copyright (C) 1995-2022 Mark Adler
6 * arithmetic-logic units, commonly found in modern CPU cores. It is due to
7 * Kadatch and Jenkins (2010). See doc/crc-doc.1.0.pdf in this distribution.
14 protection on the static variables used to control the first-use generation
45 processor. The choices for N and W below were based on testing on Intel Kaby
46 Lake i7, AMD Ryzen 7, ARM Cortex-A57, Sparc64-VII, PowerPC POWER9, and MIPS64
49 They were all tested with either gcc or clang, all using the -O3 optimization
75 # if Z_TESTW-1 != -1
109 self-respecting compiler will optimize this to a single machine byte-swap
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/freebsd/crypto/openssl/crypto/ec/asm/
H A Decp_sm2p256-armv8.pl2 # Copyright 2023-2025 The OpenSSL Project Authors. All Rights Reserved.
15 ( $xlate="${dir}arm-xlate.pl" and -f $xlate ) or
16 ( $xlate="${dir}../../perlasm/arm-xlate.pl" and -f $xlate) or
17 die "can't locate arm-xlate.pl";
63 // Select based on carry
110 // Select based on carry
166 .arch armv8-a
206 .size bn_rshift1,.-bn_rshift1
231 .size bn_sub,.-bn_sub
243 .size ecp_sm2p256_div_by_2,.-ecp_sm2p256_div_by_2
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/freebsd/contrib/llvm-project/lldb/source/Plugins/Instruction/ARM/
H A DEmulateInstructionARM.cpp1 //===-- EmulateInstructionARM.cpp -----------------------------------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
234 // FPA Registers 0-7 in LLDB_PLUGIN_DEFINE_ADV()
260 // Intel wireless MMX general purpose registers 0 - 7 XScale accumulator in LLDB_PLUGIN_DEFINE_ADV()
261 // register 0 - 7 (they do overlap with wCGR0 - wCGR7) in LLDB_PLUGIN_DEFINE_ADV()
287 // Intel wireless MMX data registers 0 - 15 in LLDB_PLUGIN_DEFINE_ADV()
423 // Intel wireless MMX control register in co-processor 0 - 7 in LLDB_PLUGIN_DEFINE_ADV()
449 // VFP-v3/Neon in LLDB_PLUGIN_DEFINE_ADV()
547 // NEON 128-bit vector registers (overlays the d registers) in LLDB_PLUGIN_DEFINE_ADV()
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