1 //===-- ARMSubtarget.cpp - ARM Subtarget Information ----------------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
43 #define DEBUG_TYPE "arm-subtarget"
50 UseFusedMulOps("arm-use-mulops",
60        cl::values(clEnumValN(DefaultIT, "arm-default-it",
62                   clEnumValN(RestrictedIT, "arm-restrict-it",
65 /// ForceFastISel - Use the fast-isel, even for subtargets where it is not
68 ForceFastISel("arm-force-fast-isel",
71 /// initializeSubtargetDependencies - Initializes using a CPU and feature string
148           (TM.getMCAsmInfo()->getExceptionHandlingType() ==  in initializeEnvironment()
164         // Default to the Cortex-a7 CPU when targeting armv7k/thumbv7k.  in initSubtargetFeatures()
166         CPUString = "cortex-a7";  in initSubtargetFeatures()
172   // based on the architecture version.  in initSubtargetFeatures()
187     // Execute only support for >= v8-M Baseline requires movt support  in initSubtargetFeatures()
191       report_fatal_error("Cannot generate execute-only code for this target");  in initSubtargetFeatures()
211   // the Thumb1 16-bit unconditional branch doesn't have sufficient relocation  in initSubtargetFeatures()
215   // For ARMv8-M, we /do/ implement tail calls.  Doing this is tricky for v8-M  in initSubtargetFeatures()
241   // NEON f32 ops are non-IEEE 754 compliant. Darwin is ok with it by default.  in initSubtargetFeatures()
352   // 32 bit macho has no relocation for a-b if a is undefined, even if b is in  in isGVIndirectSymbol()
356       (GV->isDeclarationForLinker() || GV->hasCommonLinkage()))  in isGVIndirectSymbol()
363   return isTargetELF() && TM.isPositionIndependent() && !GV->isDSOLocal();  in isGVInGOT()
374   // instructions, on cortex-m at Oz where we are size-paranoid, don't use the  in enableMachineScheduler()
379   // with the use-misched feature.  in enableMachineScheduler()
391   // with the use-mipipeliner feature.  in enableMachinePipeliner()
403   // Thumb1 cores will generally not benefit from post-ra scheduling  in enablePostRAScheduler()
424   // NOTE Windows on ARM needs to use mov.w/mov.t pairs to materialise 32-bit  in useMovt()
432   // Enable fast-isel for any target, for testing only.  in useFastISel()
436   // Limit fast-isel to the targets that are or have been tested.  in useFastISel()
448   // tradeoffs preferred by different sub-architectures and optimisation goals.  in getGPRAllocationOrder()
451   // 1: r14, r0-r13  in getGPRAllocationOrder()
452   // 2: r0-r7  in getGPRAllocationOrder()
453   // 3: r0-r7, r12, lr, r8-r11  in getGPRAllocationOrder()
455   // callee-saved registers are used later, as they require extra work in the  in getGPRAllocationOrder()
458   // For thumb1-only targets, only the low registers are allocatable.  in getGPRAllocationOrder()
462   // Allocate low registers first, so we can select more 16-bit instructions.  in getGPRAllocationOrder()
464   // with regards to callee-saved registers, because pushing extra registers is  in getGPRAllocationOrder()
480   // cost per use) so we can  use narrow encoding. By default, caller-saved  in ignoreCSRForAllocationOrder()
490   if (!MF.getTarget().getMCAsmInfo()->usesWindowsCFI() ||  in splitFramePointerPush()
494   return MFI.hasVarSizedObjects() || getRegisterInfo()->hasStackRealignment(MF);  in splitFramePointerPush()