Lines Matching +full:armv8 +full:- +full:based
1 // SPDX-License-Identifier: GPL-2.0
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/soc/bcm2835-pm.h>
10 #address-cells = <2>;
11 #size-cells = <1>;
13 interrupt-parent = <&gicv2>;
16 compatible = "brcm,bcm2711-vc5";
20 clk_27MHz: clk-27M {
21 #clock-cells = <0>;
22 compatible = "fixed-clock";
23 clock-frequency = <27000000>;
24 clock-output-names = "27MHz-clock";
27 clk_108MHz: clk-108M {
28 #clock-cells = <0>;
29 compatible = "fixed-clock";
30 clock-frequency = <108000000>;
31 clock-output-names = "108MHz-clock";
38 * BCM2711-specific peripherals
39 * ARM-local peripherals
44 /* Emulate a contiguous 30-bit address range for DMA */
45 dma-ranges = <0xc0000000 0x0 0x00000000 0x40000000>;
48 * This node is the provider for the enable-method for
51 local_intc: interrupt-controller@40000000 {
52 compatible = "brcm,bcm2836-l1-intc";
56 gicv2: interrupt-controller@40041000 {
57 interrupt-controller;
58 #interrupt-cells = <3>;
59 compatible = "arm,gic-400";
68 avs_monitor: avs-monitor@7d5d2000 {
69 compatible = "brcm,bcm2711-avs-monitor",
70 "syscon", "simple-mfd";
74 compatible = "brcm,bcm2711-thermal";
75 #thermal-sensor-cells = <0>;
79 dma: dma-controller@7e007000 {
80 compatible = "brcm,bcm2835-dma";
89 /* DMA lite 7 - 10 */
94 interrupt-names = "dma0",
105 #dma-cells = <1>;
106 brcm,dma-channel-mask = <0x07f5>;
110 compatible = "brcm,bcm2711-pm", "brcm,bcm2835-pm-wdt";
111 #power-domain-cells = <1>;
112 #reset-cells = <1>;
116 reg-names = "pm", "asb", "rpivid_asb";
121 clock-names = "v3d", "peri_image", "h264", "isp";
122 system-power-controller;
126 compatible = "brcm,bcm2711-rng200";
136 clock-names = "uartclk", "apb_pclk";
137 arm,primecell-periphid = <0x00241011>;
147 clock-names = "uartclk", "apb_pclk";
148 arm,primecell-periphid = <0x00241011>;
158 clock-names = "uartclk", "apb_pclk";
159 arm,primecell-periphid = <0x00241011>;
169 clock-names = "uartclk", "apb_pclk";
170 arm,primecell-periphid = <0x00241011>;
175 compatible = "brcm,bcm2835-spi";
179 #address-cells = <1>;
180 #size-cells = <0>;
185 compatible = "brcm,bcm2835-spi";
189 #address-cells = <1>;
190 #size-cells = <0>;
195 compatible = "brcm,bcm2835-spi";
199 #address-cells = <1>;
200 #size-cells = <0>;
205 compatible = "brcm,bcm2835-spi";
209 #address-cells = <1>;
210 #size-cells = <0>;
215 compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c";
219 #address-cells = <1>;
220 #size-cells = <0>;
225 compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c";
229 #address-cells = <1>;
230 #size-cells = <0>;
235 compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c";
239 #address-cells = <1>;
240 #size-cells = <0>;
245 compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c";
249 #address-cells = <1>;
250 #size-cells = <0>;
255 compatible = "brcm,bcm2711-pixelvalve0";
262 compatible = "brcm,bcm2711-pixelvalve1";
269 compatible = "brcm,bcm2711-pixelvalve2";
276 compatible = "brcm,bcm2835-pwm";
279 assigned-clocks = <&clocks BCM2835_CLOCK_PWM>;
280 assigned-clock-rates = <10000000>;
281 #pwm-cells = <3>;
286 compatible = "brcm,bcm2711-pixelvalve4";
293 compatible = "brcm,bcm2711-hvs";
299 compatible = "brcm,bcm2711-pixelvalve3";
306 compatible = "brcm,bcm2711-vec";
314 compatible = "brcm,brcm2711-dvp";
317 #clock-cells = <1>;
318 #reset-cells = <1>;
321 aon_intr: interrupt-controller@7ef00100 {
322 compatible = "brcm,bcm2711-l2-intc", "brcm,l2-intc";
325 interrupt-controller;
326 #interrupt-cells = <1>;
330 compatible = "brcm,bcm2711-hdmi0";
340 reg-names = "hdmi",
349 clock-names = "hdmi", "bvb", "audio", "cec";
351 interrupt-parent = <&aon_intr>;
354 interrupt-names = "cec-tx", "cec-rx", "cec-low",
355 "wakeup", "hpd-connected", "hpd-removed";
358 dma-names = "audio-rx";
363 compatible = "brcm,bcm2711-hdmi-i2c";
365 reg-names = "bsc", "auto-i2c";
366 clock-frequency = <97500>;
371 compatible = "brcm,bcm2711-hdmi1";
381 reg-names = "hdmi",
391 clock-names = "hdmi", "bvb", "audio", "cec";
393 interrupt-parent = <&aon_intr>;
396 interrupt-names = "cec-tx", "cec-rx", "cec-low",
397 "wakeup", "hpd-connected", "hpd-removed";
399 dma-names = "audio-rx";
404 compatible = "brcm,bcm2711-hdmi-i2c";
406 reg-names = "bsc", "auto-i2c";
407 clock-frequency = <97500>;
413 * emmc2 has different DMA constraints based on SoC revisions. It was
416 * so, it'll edit the dma-ranges property below accordingly.
419 compatible = "simple-bus";
420 #address-cells = <2>;
421 #size-cells = <1>;
424 dma-ranges = <0x0 0xc0000000 0x0 0x00000000 0x40000000>;
427 compatible = "brcm,bcm2711-emmc2";
435 arm-pmu {
436 compatible = "arm,cortex-a72-pmu", "arm,armv8-pmuv3";
441 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
445 compatible = "arm,armv8-timer";
455 arm,cpu-registers-not-fw-configured;
459 #address-cells = <1>;
460 #size-cells = <0>;
461 enable-method = "brcm,bcm2836-smp"; // for ARM 32-bit
463 /* Source for d/i-cache-line-size and d/i-cache-sets
465 * /Level-1-Memory-System/About-the-L1-memory-system?lang=en
466 * Source for d/i-cache-size
472 compatible = "arm,cortex-a72";
474 enable-method = "spin-table";
475 cpu-release-addr = <0x0 0x000000d8>;
476 d-cache-size = <0x8000>;
477 d-cache-line-size = <64>;
478 d-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
479 i-cache-size = <0xc000>;
480 i-cache-line-size = <64>;
481 i-cache-sets = <256>; // 48KiB(size)/64(line-size)=768ways/3-way set
482 next-level-cache = <&l2>;
487 compatible = "arm,cortex-a72";
489 enable-method = "spin-table";
490 cpu-release-addr = <0x0 0x000000e0>;
491 d-cache-size = <0x8000>;
492 d-cache-line-size = <64>;
493 d-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
494 i-cache-size = <0xc000>;
495 i-cache-line-size = <64>;
496 i-cache-sets = <256>; // 48KiB(size)/64(line-size)=768ways/3-way set
497 next-level-cache = <&l2>;
502 compatible = "arm,cortex-a72";
504 enable-method = "spin-table";
505 cpu-release-addr = <0x0 0x000000e8>;
506 d-cache-size = <0x8000>;
507 d-cache-line-size = <64>;
508 d-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
509 i-cache-size = <0xc000>;
510 i-cache-line-size = <64>;
511 i-cache-sets = <256>; // 48KiB(size)/64(line-size)=768ways/3-way set
512 next-level-cache = <&l2>;
517 compatible = "arm,cortex-a72";
519 enable-method = "spin-table";
520 cpu-release-addr = <0x0 0x000000f0>;
521 d-cache-size = <0x8000>;
522 d-cache-line-size = <64>;
523 d-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
524 i-cache-size = <0xc000>;
525 i-cache-line-size = <64>;
526 i-cache-sets = <256>; // 48KiB(size)/64(line-size)=768ways/3-way set
527 next-level-cache = <&l2>;
530 /* Source for d/i-cache-line-size and d/i-cache-sets
532 * /Level-2-Memory-System/About-the-L2-memory-system?lang=en
533 * Source for d/i-cache-size
537 l2: l2-cache0 {
539 cache-unified;
540 cache-size = <0x100000>;
541 cache-line-size = <64>;
542 cache-sets = <1024>; // 1MiB(size)/64(line-size)=16384ways/16-way set
543 cache-level = <2>;
548 compatible = "simple-bus";
549 #address-cells = <2>;
550 #size-cells = <1>;
556 compatible = "brcm,bcm2711-pcie";
559 #address-cells = <3>;
560 #interrupt-cells = <1>;
561 #size-cells = <2>;
564 interrupt-names = "pcie", "msi";
565 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
566 interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 143
574 msi-controller;
575 msi-parent = <&pcie0>;
584 dma-ranges = <0x02000000 0x0 0x00000000 0x0 0x00000000
586 brcm,enable-ssc;
590 compatible = "brcm,bcm2711-genet-v5";
592 #address-cells = <0x1>;
593 #size-cells = <0x1>;
599 compatible = "brcm,genet-mdio-v5";
601 reg-names = "mdio";
602 #address-cells = <0x1>;
603 #size-cells = <0x0>;
608 compatible = "brcm,bcm2711-xhci", "brcm,xhci-brcm-v2";
610 #address-cells = <1>;
611 #size-cells = <0>;
622 compatible = "brcm,2711-v3d";
625 reg-names = "hub", "core0";
627 power-domains = <&pm BCM2835_POWER_DOMAIN_GRAFX_V3D>;
635 clock-frequency = <54000000>;
639 compatible = "brcm,bcm2711-cprman";
643 coefficients = <(-487) 410040>;
644 thermal-sensors = <&thermal>;
653 compatible = "brcm,bcm2711-dsi1";
657 compatible = "brcm,bcm2711-gpio";
663 gpio-ranges = <&gpio 0 0 58>;
665 gpclk0_gpio49: gpclk0-gpio49 {
666 pin-gpclk {
669 bias-disable;
672 gpclk1_gpio50: gpclk1-gpio50 {
673 pin-gpclk {
676 bias-disable;
679 gpclk2_gpio51: gpclk2-gpio51 {
680 pin-gpclk {
683 bias-disable;
687 i2c0_gpio46: i2c0-gpio46 {
688 pin-sda {
691 bias-pull-up;
693 pin-scl {
696 bias-disable;
699 i2c1_gpio46: i2c1-gpio46 {
700 pin-sda {
703 bias-pull-up;
705 pin-scl {
708 bias-disable;
711 i2c3_gpio2: i2c3-gpio2 {
712 pin-sda {
715 bias-pull-up;
717 pin-scl {
720 bias-disable;
723 i2c3_gpio4: i2c3-gpio4 {
724 pin-sda {
727 bias-pull-up;
729 pin-scl {
732 bias-disable;
735 i2c4_gpio6: i2c4-gpio6 {
736 pin-sda {
739 bias-pull-up;
741 pin-scl {
744 bias-disable;
747 i2c4_gpio8: i2c4-gpio8 {
748 pin-sda {
751 bias-pull-up;
753 pin-scl {
756 bias-disable;
759 i2c5_gpio10: i2c5-gpio10 {
760 pin-sda {
763 bias-pull-up;
765 pin-scl {
768 bias-disable;
771 i2c5_gpio12: i2c5-gpio12 {
772 pin-sda {
775 bias-pull-up;
777 pin-scl {
780 bias-disable;
783 i2c6_gpio0: i2c6-gpio0 {
784 pin-sda {
787 bias-pull-up;
789 pin-scl {
792 bias-disable;
795 i2c6_gpio22: i2c6-gpio22 {
796 pin-sda {
799 bias-pull-up;
801 pin-scl {
804 bias-disable;
807 i2c_slave_gpio8: i2c-slave-gpio8 {
808 pins-i2c-slave {
817 jtag_gpio48: jtag-gpio48 {
818 pins-jtag {
829 mii_gpio28: mii-gpio28 {
830 pins-mii {
838 mii_gpio36: mii-gpio36 {
839 pins-mii {
848 pcm_gpio50: pcm-gpio50 {
849 pins-pcm {
858 pwm0_0_gpio12: pwm0-0-gpio12 {
859 pin-pwm {
862 bias-disable;
865 pwm0_0_gpio18: pwm0-0-gpio18 {
866 pin-pwm {
869 bias-disable;
872 pwm1_0_gpio40: pwm1-0-gpio40 {
873 pin-pwm {
876 bias-disable;
879 pwm0_1_gpio13: pwm0-1-gpio13 {
880 pin-pwm {
883 bias-disable;
886 pwm0_1_gpio19: pwm0-1-gpio19 {
887 pin-pwm {
890 bias-disable;
893 pwm1_1_gpio41: pwm1-1-gpio41 {
894 pin-pwm {
897 bias-disable;
900 pwm0_1_gpio45: pwm0-1-gpio45 {
901 pin-pwm {
904 bias-disable;
907 pwm0_0_gpio52: pwm0-0-gpio52 {
908 pin-pwm {
911 bias-disable;
914 pwm0_1_gpio53: pwm0-1-gpio53 {
915 pin-pwm {
918 bias-disable;
922 rgmii_gpio35: rgmii-gpio35 {
923 pin-start-stop {
927 pin-rx-ok {
932 rgmii_irq_gpio34: rgmii-irq-gpio34 {
933 pin-irq {
938 rgmii_irq_gpio39: rgmii-irq-gpio39 {
939 pin-irq {
944 rgmii_mdio_gpio28: rgmii-mdio-gpio28 {
945 pins-mdio {
951 rgmii_mdio_gpio37: rgmii-mdio-gpio37 {
952 pins-mdio {
959 spi0_gpio46: spi0-gpio46 {
960 pins-spi {
968 spi2_gpio46: spi2-gpio46 {
969 pins-spi {
978 spi3_gpio0: spi3-gpio0 {
979 pins-spi {
987 spi4_gpio4: spi4-gpio4 {
988 pins-spi {
996 spi5_gpio12: spi5-gpio12 {
997 pins-spi {
1005 spi6_gpio18: spi6-gpio18 {
1006 pins-spi {
1015 uart2_gpio0: uart2-gpio0 {
1016 pin-tx {
1019 bias-disable;
1021 pin-rx {
1024 bias-pull-up;
1027 uart2_ctsrts_gpio2: uart2-ctsrts-gpio2 {
1028 pin-cts {
1031 bias-pull-up;
1033 pin-rts {
1036 bias-disable;
1039 uart3_gpio4: uart3-gpio4 {
1040 pin-tx {
1043 bias-disable;
1045 pin-rx {
1048 bias-pull-up;
1051 uart3_ctsrts_gpio6: uart3-ctsrts-gpio6 {
1052 pin-cts {
1055 bias-pull-up;
1057 pin-rts {
1060 bias-disable;
1063 uart4_gpio8: uart4-gpio8 {
1064 pin-tx {
1067 bias-disable;
1069 pin-rx {
1072 bias-pull-up;
1075 uart4_ctsrts_gpio10: uart4-ctsrts-gpio10 {
1076 pin-cts {
1079 bias-pull-up;
1081 pin-rts {
1084 bias-disable;
1087 uart5_gpio12: uart5-gpio12 {
1088 pin-tx {
1091 bias-disable;
1093 pin-rx {
1096 bias-pull-up;
1099 uart5_ctsrts_gpio14: uart5-ctsrts-gpio14 {
1100 pin-cts {
1103 bias-pull-up;
1105 pin-rts {
1108 bias-disable;
1114 #address-cells = <2>;
1123 alloc-ranges = <0x0 0x00000000 0x40000000>;
1127 compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c";
1132 compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c";
1184 compatible = "brcm,bcm2711-vec";