Lines Matching +full:armv8 +full:- +full:based
1 //===--- ARM.cpp - Implement ARM target feature support -------------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
47 ? "E-m:o-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" in setABIAAPCS()
48 : "e-m:o-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64", in setABIAAPCS()
53 "-m:w" in setABIAAPCS()
54 "-p:32:32" in setABIAAPCS()
55 "-Fi8" in setABIAAPCS()
56 "-i64:64" in setABIAAPCS()
57 "-v128:64:128" in setABIAAPCS()
58 "-a:0:32" in setABIAAPCS()
59 "-n32" in setABIAAPCS()
60 "-S64"); in setABIAAPCS()
63 resetDataLayout("e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S128"); in setABIAAPCS()
66 ? "E-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" in setABIAAPCS()
67 : "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"); in setABIAAPCS()
87 // Do not respect the alignment of bit-field types when laying out in setABIAPCS()
97 assert(!BigEndian && "AAPCS16 does not support big-endian"); in setABIAPCS()
98 resetDataLayout("e-m:o-p:32:32-Fi8-i64:64-a:0:32-n32-S128", "_"); in setABIAPCS()
102 ? "E-m:o-p:32:32-Fi8-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" in setABIAPCS()
103 : "e-m:o-p:32:32-Fi8-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32", in setABIAPCS()
108 ? "E-m:e-p:32:32-Fi8-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" in setABIAPCS()
109 : "e-m:e-p:32:32-Fi8-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"); in setABIAPCS()
180 // For most sub-arches, the build attribute CPU name is enough. in getCPUAttr()
265 // FIXME: the isOSBinFormatMachO is a workaround for identifying a Darwin-like in ARMTargetInfo()
291 // FIXME: This duplicates code from the driver that sets the -target-abi in ARMTargetInfo()
292 // option - this code is used if -target-abi isn't passed and should in ARMTargetInfo()
295 // The backend is hardwired to assume AAPCS for M-class processors, ensure in ARMTargetInfo()
304 setABI("apcs-gnu"); in ARMTargetInfo()
310 // Select the default based on the platform. in ARMTargetInfo()
320 setABI("aapcs-linux"); in ARMTargetInfo()
327 setABI("apcs-gnu"); in ARMTargetInfo()
331 setABI("apcs-gnu"); in ARMTargetInfo()
333 setABI("aapcs-linux"); in ARMTargetInfo()
346 // Maximum alignment for ARM NEON data types should be 64-bits (AAPCS) in ARMTargetInfo()
352 // the alignment of the zero-length bitfield is greater than the member in ARMTargetInfo()
359 this->MCountName = Opts.EABIVersion == llvm::EABI::GNU in ARMTargetInfo()
363 SoftFloatABI = llvm::is_contained(Opts.FeaturesAsWritten, "+soft-float-abi"); in ARMTargetInfo()
373 // FIXME: We need support for -meabi... we could just mangle it into the in setABI()
375 if (Name == "apcs-gnu" || Name == "aapcs16") { in setABI()
379 if (Name == "aapcs" || Name == "aapcs-vfp" || Name == "aapcs-linux") { in setABI()
416 .Case("non-leaf", LangOptions::SignReturnAddressScopeKind::NonLeaf) in validateBranchProtection()
422 Err = "b-key"; in validateBranchProtection()
430 // FIXME: This should be based on Arch attributes, not CPU names.
451 // v8.x counterparts are added too. We only need these for anything > 8.0-A. in initFeatureMap()
453 I != llvm::ARM::ArchKind::INVALID; --I) in initFeatureMap()
458 --I) in initFeatureMap()
474 // Enable or disable thumb-mode explicitly per function to enable mixed in initFeatureMap()
477 Features["thumb-mode"] = true; in initFeatureMap()
479 Features["thumb-mode"] = false; in initFeatureMap()
481 // Convert user-provided arm and thumb GNU target attributes to in initFeatureMap()
482 // [-|+]thumb-mode target features respectively. in initFeatureMap()
485 // Skip soft-float-abi; it's something we only use to initialize a bit of in initFeatureMap()
487 if (Feature == "+soft-float-abi") in initFeatureMap()
492 FixedFeature = "-thumb-mode"; in initFeatureMap()
494 FixedFeature = "+thumb-mode"; in initFeatureMap()
528 // "+vfpv2" and "+vfpv3" or having "+neon" and "-fp64". in handleTargetFeatures()
530 if (Feature == "+soft-float") { in handleTargetFeatures()
549 } else if (Feature == "+fp-armv8sp" || Feature == "+fp-armv8d16sp" || in handleTargetFeatures()
550 Feature == "+fp-armv8" || Feature == "+fp-armv8d16") { in handleTargetFeatures()
553 if (Feature == "+fp-armv8" || Feature == "+fp-armv8d16") in handleTargetFeatures()
560 } else if (Feature == "+hwdiv-arm") { in handleTargetFeatures()
579 } else if (Feature == "+strict-align") { in handleTargetFeatures()
598 unsigned Coproc = Feature.back() - '0'; in handleTargetFeatures()
602 } else if (Feature == "-fpregs") { in handleTargetFeatures()
642 Features.push_back("-neonfp"); in handleTargetFeatures()
656 .Case("hwdiv-arm", HWDiv & HWDivARM) in hasFeature()
705 // Also include the ARMv8.1-A defines in getTargetDefinesARMV82A()
711 // Also include the ARMv8.2-A defines in getTargetDefinesARMV83A()
721 // For bare-metal none-eabi. in getTargetDefines()
733 // happens to be Cortex-A7 though, so it should still get __ARM_ARCH_7A__. in getTargetDefines()
764 // is not defined for the M-profile. in getTargetDefines()
770 // Thumb ISA (including v6-M and v8-M Baseline). It is set to 2 if the in getTargetDefines()
771 // core supports the Thumb-2 ISA as found in the v6T2 architecture and all in getTargetDefines()
772 // v7 and v8 architectures excluding v8-M Baseline. in getTargetDefines()
778 // __ARM_32BIT_STATE is defined to 1 if code is being generated for a 32-bit in getTargetDefines()
782 // ACLE 6.4.2 Architectural Profile (A, R, M or pre-Cortex) in getTargetDefines()
812 // ACLE 6.5.3 Fused multiply-accumulate (FMA) in getTargetDefines()
824 if (ABI == "aapcs" || ABI == "aapcs-linux" || ABI == "aapcs-vfp") { in getTargetDefines()
832 if ((!SoftFloat && !SoftFloatABI) || ABI == "aapcs-vfp" || ABI == "aapcs16") in getTargetDefines()
844 // Macros for enabling co-proc intrinsics in getTargetDefines()
918 // ACLE 6.4.9 32-bit SIMD instructions in getTargetDefines()
932 // __VFP_FP__ means that the floating-point format is VFP, not that a hardware in getTargetDefines()
955 // current AArch32 NEON implementations do not support double-precision in getTargetDefines()
956 // floating-point even when it is present in VFP. in getTargetDefines()
1006 // Armv8.2-A FP16 vector intrinsic in getTargetDefines()
1010 // Armv8.2-A FP16 scalar intrinsics in getTargetDefines()
1014 // Armv8.2-A dot product intrinsics in getTargetDefines()
1094 clang::ARM::LastTSBuiltin - Builtin::FirstTSBuiltin); in getTargetBuiltins()
1134 // don't want to substitute one of these for a different-sized one.
1146 case 'l': // r0-r7 if thumb, r0-r15 if ARM in validateAsmConstraint()
1149 case 'h': // r8-r15, thumb only in validateAsmConstraint()
1157 case 't': // s0-s31, d0-d31, or q0-q15 in validateAsmConstraint()
1158 case 'w': // s0-s15, d0-d7, or q0-q3 in validateAsmConstraint()
1159 case 'x': // s0-s31, d0-d15, or q0-q7 in validateAsmConstraint()
1177 // data-processing instruction in validateAsmConstraint()
1181 // data-processing instruction in validateAsmConstraint()
1186 Info.setRequiresImmediate(-255, -1); in validateAsmConstraint()
1188 Info.setRequiresImmediate(-4095, 4095); in validateAsmConstraint()
1198 // data-processing instruction when inverted in validateAsmConstraint()
1202 // data-processing instruction when inverted in validateAsmConstraint()
1208 Info.setRequiresImmediate(-7, 7); in validateAsmConstraint()
1211 // data-processing instruction when negated in validateAsmConstraint()
1215 // data-processing instruction when negated in validateAsmConstraint()
1238 // FIXME: should check if immediate value is a multiple of 4 between -508 in validateAsmConstraint()
1251 case 'e': // Even general-purpose register in validateAsmConstraint()
1252 case 'o': // Odd general-purpose register in validateAsmConstraint()
1264 // than 128-bits in validateAsmConstraint()
1267 case 's': // valid address for non-offset loads/stores of quad-word in validateAsmConstraint()
1281 case 'U': // Two-character constraint; add "^" hint for later parsing. in convertConstraint()
1344 return -1; in getEHDataRegisterNumber()
1461 this->WCharType = TargetInfo::UnsignedShort; in CygwinARMTargetInfo()
1464 resetDataLayout("e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"); in CygwinARMTargetInfo()