Lines Matching +full:armv8 +full:- +full:based
1 //===--- AArch64.cpp - Implement AArch64 target feature support -----------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
70 } else if (ArchInfo->Version.getMajor() == 8) { in setArchFeatures()
71 if (ArchInfo->Version.getMinor() >= 7u) { in setArchFeatures()
74 if (ArchInfo->Version.getMinor() >= 6u) { in setArchFeatures()
78 if (ArchInfo->Version.getMinor() >= 5u) { in setArchFeatures()
86 if (ArchInfo->Version.getMinor() >= 4u) { in setArchFeatures()
91 if (ArchInfo->Version.getMinor() >= 3u) { in setArchFeatures()
95 if (ArchInfo->Version.getMinor() >= 2u) { in setArchFeatures()
98 if (ArchInfo->Version.getMinor() >= 1u) { in setArchFeatures()
103 } else if (ArchInfo->Version.getMajor() == 9) { in setArchFeatures()
104 if (ArchInfo->Version.getMinor() >= 2u) { in setArchFeatures()
107 if (ArchInfo->Version.getMinor() >= 1u) { in setArchFeatures()
146 // All AArch64 implementations support ARMv8 FP, which makes half a legal type. in AArch64TargetInfo()
187 // a plain (non bit-field) member of that type would, without exception for in AArch64TargetInfo()
188 // zero-sized or anonymous bit-fields." in AArch64TargetInfo()
198 this->MCountName = "\01_mcount"; in AArch64TargetInfo()
200 this->MCountName = in AArch64TargetInfo()
207 if (Name != "aapcs" && Name != "aapcs-soft" && Name != "darwinpcs" && in setABI()
216 if (hasFeature("fp") && ABI == "aapcs-soft") { in validateTarget()
217 // aapcs-soft is not allowed for targets with an FPU, to avoid there being in validateTarget()
252 .Case("non-leaf", LangOptions::SignReturnAddressScopeKind::NonLeaf) in validateBranchProtection()
287 // Also include the ARMv8.1 defines in getTargetDefinesARMV82A()
295 // Also include the Armv8.2 defines in getTargetDefinesARMV83A()
301 // Also include the Armv8.3 defines in getTargetDefinesARMV84A()
308 // Also include the Armv8.4 defines in getTargetDefinesARMV85A()
314 // Also include the Armv8.5 defines in getTargetDefinesARMV86A()
315 // FIXME: Armv8.6 makes the following extensions mandatory: in getTargetDefinesARMV86A()
316 // - __ARM_FEATURE_BF16 in getTargetDefinesARMV86A()
317 // - __ARM_FEATURE_MATMUL_INT8 in getTargetDefinesARMV86A()
324 // Also include the Armv8.6 defines in getTargetDefinesARMV87A()
330 // Also include the Armv8.7 defines in getTargetDefinesARMV88A()
336 // Also include the Armv8.8 defines in getTargetDefinesARMV89A()
342 // Armv9-A maps to Armv8.5-A in getTargetDefinesARMV9A()
348 // Armv9.1-A maps to Armv8.6-A in getTargetDefinesARMV91A()
354 // Armv9.2-A maps to Armv8.7-A in getTargetDefinesARMV92A()
360 // Armv9.3-A maps to Armv8.8-A in getTargetDefinesARMV93A()
366 // Armv9.4-A maps to Armv8.9-A in getTargetDefinesARMV94A()
372 // Armv9.5-A does not have a v8.* equivalent, but is a superset of v9.4-A. in getTargetDefinesARMV95A()
404 std::to_string(ArchInfo->Version.getMajor())); in getTargetDefines()
406 std::string("'") + (char)ArchInfo->Profile + "'"); in getTargetDefines()
446 // 64-bit NEON supports half, single and double precision operations. in getTargetDefines()
676 return llvm::ArrayRef(BuiltinInfo, clang::AArch64::LastTSBuiltin - in getTargetBuiltins()
696 return Ext->Priority; in multiVersionSortPriority()
709 return !Ext->Features.empty(); in doesFeatureAffectCodeGen()
752 .Case("sve-bf16", FPU & SveMode && HasBFloat16) in hasFeature()
753 .Case("sve-i8mm", FPU & SveMode && HasMatMul) in hasFeature()
754 .Case("sve-b16b16", HasSVEB16B16) in hasFeature()
758 .Case("sve2-pmull128", FPU & SveMode && HasSVE2AES) in hasFeature()
759 .Case("sve2-bitperm", FPU & SveMode && HasSVE2BitPerm) in hasFeature()
760 .Case("sve2-sha3", FPU & SveMode && HasSVE2SHA3) in hasFeature()
761 .Case("sve2-sm4", FPU & SveMode && HasSVE2SM4) in hasFeature()
766 .Case("sme-f64f64", HasSMEF64F64) in hasFeature()
767 .Case("sme-i16i64", HasSMEI16I64) in hasFeature()
768 .Case("sme-fa64", HasSMEFA64) in hasFeature()
769 .Case("sme-f16f16", HasSMEF16F16) in hasFeature()
770 .Case("sme-b16b16", HasSMEB16B16) in hasFeature()
798 if (ArchInfo->implies(*OtherArch)) in setFeatureEnabled()
799 Features[OtherArch->getSubArch()] = true; in setFeatureEnabled()
803 if (llvm::AArch64::getExtensionFeatures(ArchInfo->DefaultExts, CPUFeats)) { in setFeatureEnabled()
814 if (Feature == "-fp-armv8") in handleTargetFeatures()
816 if (Feature == "-neon") in handleTargetFeatures()
818 if (Feature == "-sve") in handleTargetFeatures()
821 if (Feature == "+neon" || Feature == "+fp-armv8") in handleTargetFeatures()
850 if (Feature == "+sve2-aes") { in handleTargetFeatures()
857 if (Feature == "+sve2-sha3") { in handleTargetFeatures()
864 if (Feature == "+sve2-sm4") { in handleTargetFeatures()
871 if (Feature == "+sve-b16b16") in handleTargetFeatures()
873 if (Feature == "+sve2-bitperm") { in handleTargetFeatures()
910 if (Feature == "+sme-f64f64") { in handleTargetFeatures()
916 if (Feature == "+sme-i16i64") { in handleTargetFeatures()
922 if (Feature == "+sme-fa64") { in handleTargetFeatures()
929 if (Feature == "+sme-f16f16") { in handleTargetFeatures()
936 if (Feature == "+sme-b16b16") { in handleTargetFeatures()
954 if (Feature == "-fmv") in handleTargetFeatures()
991 if (Feature == "+strict-align") in handleTargetFeatures()
995 if (Feature == "+v8a" && ArchInfo->Version < llvm::AArch64::ARMV8A.Version) in handleTargetFeatures()
998 ArchInfo->Version < llvm::AArch64::ARMV8_1A.Version) in handleTargetFeatures()
1001 ArchInfo->Version < llvm::AArch64::ARMV8_2A.Version) in handleTargetFeatures()
1004 ArchInfo->Version < llvm::AArch64::ARMV8_3A.Version) in handleTargetFeatures()
1007 ArchInfo->Version < llvm::AArch64::ARMV8_4A.Version) in handleTargetFeatures()
1010 ArchInfo->Version < llvm::AArch64::ARMV8_5A.Version) in handleTargetFeatures()
1013 ArchInfo->Version < llvm::AArch64::ARMV8_6A.Version) in handleTargetFeatures()
1016 ArchInfo->Version < llvm::AArch64::ARMV8_7A.Version) in handleTargetFeatures()
1019 ArchInfo->Version < llvm::AArch64::ARMV8_8A.Version) in handleTargetFeatures()
1022 ArchInfo->Version < llvm::AArch64::ARMV8_9A.Version) in handleTargetFeatures()
1024 if (Feature == "+v9a" && ArchInfo->Version < llvm::AArch64::ARMV9A.Version) in handleTargetFeatures()
1027 ArchInfo->Version < llvm::AArch64::ARMV9_1A.Version) in handleTargetFeatures()
1030 ArchInfo->Version < llvm::AArch64::ARMV9_2A.Version) in handleTargetFeatures()
1033 ArchInfo->Version < llvm::AArch64::ARMV9_3A.Version) in handleTargetFeatures()
1036 ArchInfo->Version < llvm::AArch64::ARMV9_4A.Version) in handleTargetFeatures()
1039 ArchInfo->Version < llvm::AArch64::ARMV9_5A.Version) in handleTargetFeatures()
1086 if (Feature == "+pauth-lr") { in handleTargetFeatures()
1093 // This needs to be checked after architecture-related features are handled, in handleTargetFeatures()
1096 if (Feature == "-d128") in handleTargetFeatures()
1119 // "arch=<arch>" - parsed to features as per -march=..
1120 // "cpu=<cpu>" - parsed to features as per -mcpu=.., with CPU set to <cpu>
1121 // "tune=<cpu>" - TuneCPU set to <cpu>
1122 // "feature", "no-feature" - Add (or remove) feature.
1123 // "+feature", "+nofeature" - Add (or remove) feature.
1141 FeatString.split(SplitFeatures, StringRef("+"), -1, false); in parseTargetAttr()
1152 Features.push_back("-" + Feature.drop_front(2).str()); in parseTargetAttr()
1168 if (Feature.starts_with("branch-protection=")) { in parseTargetAttr()
1192 // Split the cpu string into "cpu=", "cortex-a710" and any remaining in parseTargetAttr()
1218 if (Feature.starts_with("no-")) in parseTargetAttr()
1219 Ret.Features.push_back("-" + Feature.drop_front(3).str()); in parseTargetAttr()
1258 // clang-format off
1260 // 32-bit Integer registers
1265 // 64-bit Integer registers
1270 // 32-bit floating point regsisters
1275 // 64-bit floating point regsisters
1294 // SVE predicate-as-counter registers
1301 // clang-format on
1344 // don't want to substitute one of these for a different-sized one.
1379 case 'U': // Three-character constraint; add "@3" hint for later parsing. in convertConstraint()
1386 Constraint += Len - 1; in convertConstraint()
1402 case 'w': // Floating point and SIMD registers (V0-V31) in validateAsmConstraint()
1407 case 'K': // Constant that can be used with a 32-bit logical instruction in validateAsmConstraint()
1408 case 'L': // Constant that can be used with a 64-bit logical instruction in validateAsmConstraint()
1409 case 'M': // Constant that can be used as a 32-bit MOV immediate in validateAsmConstraint()
1410 case 'N': // Constant that can be used as a 64-bit MOV immediate in validateAsmConstraint()
1423 // SVE predicate registers ("Upa"=P0-15, "Upl"=P0-P7, "Uph"=P8-P15) in validateAsmConstraint()
1429 // Gpr registers ("Uci"=w8-11, "Ucj"=w12-15) in validateAsmConstraint()
1437 // Ush: The high part (bits 32:12) of a pc-relative symbolic address. in validateAsmConstraint()
1445 case 'x': // Floating point and SIMD registers (V0-V15) in validateAsmConstraint()
1448 case 'y': // SVE registers (V0-V7) in validateAsmConstraint()
1454 Name += Len - 1; in validateAsmConstraint()
1502 return -1; in getEHDataRegisterNumber()
1519 resetDataLayout("e-m:o-p:32:32-i64:64-i128:128-n32:64-S128-Fn32", "_"); in setDataLayout()
1521 resetDataLayout("e-m:o-i64:64-i128:128-n32:64-S128-Fn32", "_"); in setDataLayout()
1523 resetDataLayout("e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"); in setDataLayout()
1546 resetDataLayout("E-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"); in setDataLayout()
1569 ? "e-m:o-i64:64-i128:128-n32:64-S128-Fn32" in setDataLayout()
1570 : "e-m:w-p:64:64-i32:32-i64:64-i128:128-n32:64-S128-Fn32", in setDataLayout()
1632 // MSVC does size based alignment for arm64 based on alignment section in in getMinGlobalAlign()
1635 // https://docs.microsoft.com/en-us/cpp/build/arm64-windows-abi-conventions in getMinGlobalAlign()
1700 // 64-bit RenderScript is aarch64