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/freebsd/sys/contrib/dev/mediatek/mt76/
H A Dmt76x02_regs.h15 #define MT_CMB_CTRL_XTAL_RDY BIT(22)
16 #define MT_CMB_CTRL_PLL_LD BIT(23)
21 #define MT_EFUSE_CTRL_LDO_OFF_TIME GENMASK(13, 8)
24 #define MT_EFUSE_CTRL_KICK BIT(30)
25 #define MT_EFUSE_CTRL_SEL BIT(31)
31 #define MT_COEXCFG0_COEX_EN BIT(0)
34 #define MT_WLAN_FUN_CTRL_WLAN_EN BIT(0)
35 #define MT_WLAN_FUN_CTRL_WLAN_CLK_EN BIT(1)
36 #define MT_WLAN_FUN_CTRL_WLAN_RESET_RF BIT(2)
43 #define MT_WLAN_FUN_CTRL_WLAN_RESET BIT(3) /* MT76x0 */
[all …]
H A Dmt76_connac3_mac.h28 #define MT_RXD0_MESH BIT(18)
29 #define MT_RXD0_MHCP BIT(19)
31 #define MT_RXD0_NORMAL_IP_SUM BIT(23)
32 #define MT_RXD0_NORMAL_UDP_TCP_SUM BIT(24)
40 #define MT_RXD1_NORMAL_GROUP_1 BIT(16)
41 #define MT_RXD1_NORMAL_GROUP_2 BIT(17)
42 #define MT_RXD1_NORMAL_GROUP_3 BIT(18)
43 #define MT_RXD1_NORMAL_GROUP_4 BIT(19)
44 #define MT_RXD1_NORMAL_GROUP_5 BIT(20)
46 #define MT_RXD1_NORMAL_CM BIT(23)
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/freebsd/sys/contrib/dev/rtw89/
H A Dreg.h9 #define B_AX_AUTOLOAD_SUS BIT(5)
13 #define B_AX_PWC_EV2EF_B15 BIT(15)
14 #define B_AX_PWC_EV2EF_B14 BIT(14)
15 #define B_AX_ISO_EB2CORE BIT(8)
18 #define B_AX_FEN_BB_GLB_RSTN BIT(1)
19 #define B_AX_FEN_BBRSTB BIT(0)
22 #define B_AX_SOP_ASWRM BIT(31)
23 #define B_AX_SOP_PWMM_DSWR BIT(29)
24 #define B_AX_XTAL_OFF_A_DIE BIT(2
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H A Dtxrx.h10 #define DATA_RATE_MODE_CTRL_MASK GENMASK(8, 7)
11 #define DATA_RATE_MODE_CTRL_MASK_V1 GENMASK(10, 8)
65 #define RTW89_TXWD_BODY0_MORE_DATA BIT(23)
66 #define RTW89_TXWD_BODY0_WD_INFO_EN BIT(22)
67 #define RTW89_TXWD_BODY0_FW_DL BIT(20)
70 #define RTW89_TXWD_BODY0_WD_PAGE BIT(7)
71 #define RTW89_TXWD_BODY0_HW_AMSDU BIT(5)
83 #define RTW89_TXWD_BODY2_TID_INDICATE BIT(23)
88 #define RTW89_TXWD_BODY3_BK BIT(13)
89 #define RTW89_TXWD_BODY3_AGG_EN BIT(1
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/freebsd/sys/contrib/dev/mediatek/mt76/mt7603/
H A Dregs.h28 #define MT_INT_RX_DONE(_n) BIT(_n)
31 #define MT_INT_TX_DONE(_n) BIT((_n) + 4)
33 #define MT_INT_RX_COHERENT BIT(20)
34 #define MT_INT_TX_COHERENT BIT(21)
35 #define MT_INT_MAC_IRQ3 BIT(27)
37 #define MT_INT_MCU_CMD BIT(30)
40 #define MT_WPDMA_GLO_CFG_TX_DMA_EN BIT(0)
41 #define MT_WPDMA_GLO_CFG_TX_DMA_BUSY BIT(1)
42 #define MT_WPDMA_GLO_CFG_RX_DMA_EN BIT(2)
43 #define MT_WPDMA_GLO_CFG_RX_DMA_BUSY BIT(3)
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H A Dmac.h10 #define MT_RXD0_NORMAL_IP_SUM BIT(23)
11 #define MT_RXD0_NORMAL_UDP_TCP_SUM BIT(24)
12 #define MT_RXD0_NORMAL_GROUP_1 BIT(25)
13 #define MT_RXD0_NORMAL_GROUP_2 BIT(26)
14 #define MT_RXD0_NORMAL_GROUP_3 BIT(27)
15 #define MT_RXD0_NORMAL_GROUP_4 BIT(28)
29 #define MT_RXD1_NORMAL_HDR_TRANS BIT(23)
30 #define MT_RXD1_NORMAL_HDR_OFFSET BIT(22)
32 #define MT_RXD1_NORMAL_CH_FREQ GENMASK(15, 8)
34 #define MT_RXD1_NORMAL_BEACON_UC BIT(5)
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/freebsd/contrib/llvm-project/clang/lib/Headers/
H A Dmmintrin.h17 typedef long long __m64 __attribute__((__vector_size__(8), __aligned__(8)));
19 typedef long long __v1di __attribute__((__vector_size__(8)));
20 typedef int __v2si __attribute__((__vector_size__(8)));
21 typedef short __v4hi __attribute__((__vector_size__(8)));
22 typedef char __v8qi __attribute__((__vector_size__(8)));
42 /// Constructs a 64-bit integer vector, setting the lower 32 bits to the
43 /// value of the 32-bit integer parameter and setting the upper 32 bits to 0.
50 /// A 32-bit integer value.
51 /// \returns A 64-bit integer vector. The lower 32 bits contain the value of the
59 /// Returns the lower 32 bits of a 64-bit integer vector as a 32-bit
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H A Davxintrin.h61 /// Adds two 256-bit vectors of [4 x double].
68 /// A 256-bit vector of [4 x double] containing one of the source operands.
70 /// A 256-bit vector of [4 x double] containing one of the source operands.
71 /// \returns A 256-bit vector of [4 x double] containing the sums of both
79 /// Adds two 256-bit vectors of [8 x float].
86 /// A 256-bit vector of [8 x float] containing one of the source operands.
88 /// A 256-bit vector of [8 x float] containing one of the source operands.
89 /// \returns A 256-bit vector of [8 x float] containing the sums of both
97 /// Subtracts two 256-bit vectors of [4 x double].
104 /// A 256-bit vector of [4 x double] containing the minuend.
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H A Dtmmintrin.h28 /// Computes the absolute value of each of the packed 8-bit signed
29 /// integers in the source operand and stores the 8-bit unsigned integer
37 /// A 64-bit vector of [8 x i8].
38 /// \returns A 64-bit integer vector containing the absolute values of the
46 /// Computes the absolute value of each of the packed 8-bit signed
47 /// integers in the source operand and stores the 8-bit unsigned integer
55 /// A 128-bit vector of [16 x i8].
56 /// \returns A 128-bit integer vector containing the absolute values of the
64 /// Computes the absolute value of each of the packed 16-bit signed
65 /// integers in the source operand and stores the 16-bit unsigned integer
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H A Davxvnniint8intrin.h25 /// Multiply groups of 4 adjacent pairs of signed 8-bit integers in \a __A with
26 /// corresponding signed 8-bit integers in \a __B, producing 4 intermediate
27 /// signed 16-bit results. Sum these 4 results with the corresponding
28 /// 32-bit integer in \a __W, and store the packed 32-bit results in \a dst.
39 /// A 128-bit vector of [16 x char].
41 /// A 128-bit vector of [16 x char].
43 /// A 128-bit vector of [4 x int].
62 /// Multiply groups of 4 adjacent pairs of signed 8-bit integers in \a __A with
63 /// corresponding signed 8-bit integers in \a __B, producing 4 intermediate
64 /// signed 16-bit results. Sum these 4 results with the corresponding
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H A Davxvnniint16intrin.h26 /// Multiply groups of 2 adjacent pairs of signed 16-bit integers in \a __A with
27 /// corresponding unsigned 16-bit integers in \a __B, producing 2 intermediate
28 /// signed 16-bit results. Sum these 2 results with the corresponding
29 /// 32-bit integer in \a __W, and store the packed 32-bit results in \a dst.
40 /// A 128-bit vector of [4 x int].
42 /// A 128-bit vector of [8 x short].
44 /// A 128-bit vector of [8 x unsigned short].
46 /// A 128-bit vector of [4 x int].
63 /// Multiply groups of 2 adjacent pairs of signed 16-bit integers in \a __A with
64 /// corresponding unsigned 16-bit integers in \a __B, producing 2 intermediate
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/freebsd/sys/dev/etherswitch/ar40xx/
H A Dar40xx_reg.h20 * Register manipulation macros that expect bit field defines
28 #define BIT(_n) (1UL << (_n)) macro
51 #define AR40XX_PSGMII_ATHR_CSCO_MODE_25M BIT(0)
101 #define AR40XX_MODULE_EN_MIB BIT(0)
104 #define AR40XX_MIB_BUSY BIT(17)
105 #define AR40XX_MIB_CPU_KEEP BIT(20)
112 #define AR40XX_ESS_SERVICE_TAG_STAG BIT(17)
115 #define AR40XX_REG_SW_MAC_ADDR0_BYTE4 BITS(8, 8)
116 #define AR40XX_REG_SW_MAC_ADDR0_BYTE4_S 8
117 #define AR40XX_REG_SW_MAC_ADDR0_BYTE5 BITS(0, 8)
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/freebsd/sys/dev/sfxge/common/
H A Defx_regs_pci.h41 * PC_VEND_ID_REG(16bit):
52 * PC_DEV_ID_REG(16bit):
63 * PC_CMD_REG(16bit):
74 #define PCRF_AZ_SERR_EN_LBN 8
94 * PC_STAT_REG(16bit):
113 #define PCRF_AZ_MDAT_PERR_LBN 8
125 * PC_REV_ID_REG(8bit):
133 #define PCRF_AZ_REV_ID_WIDTH 8
136 * PC_CC_REG(24bit):
144 #define PCRF_AZ_BASE_CC_WIDTH 8
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/freebsd/contrib/llvm-project/llvm/lib/Target/AVR/MCTargetDesc/
H A DAVRFixupKinds.h27 /// A 32-bit AVR fixup.
30 /// A 7-bit PC-relative fixup for the family of conditional
31 /// branches which take 7-bit targets (BRNE,BRGT,etc).
33 /// A 12-bit PC-relative fixup for the family of branches
34 /// which take 12-bit targets (RJMP,RCALL,etc).
39 /// aligned to 2 bytes, so the 0'th bit is always 0.
43 /// A 16-bit address.
45 /// A 16-bit program memory address.
48 /// Replaces the 8-bit immediat
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/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIInstrFormats.td17 field bit SALU = 0;
18 field bit VALU = 0;
21 field bit SOP1 = 0;
22 field bit SOP2 = 0;
23 field bit SOPC = 0;
24 field bit SOPK = 0;
25 field bit SOPP = 0;
28 field bit VOP1 = 0;
29 field bit VOP2 = 0;
30 field bit VOPC = 0;
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/freebsd/sys/dev/msk/
H A Dif_mskreg.h183 #define BIT_8 (1 << 8)
216 #define SHIFT8(x) ((x) << 8)
229 #define PCI_BASE_1ST 0x10 /* 32 bit 1st Base address */
230 #define PCI_BASE_2ND 0x14 /* 32 bit 2nd Base address */
231 #define PCI_OUR_REG_1 0x40 /* 32 bit Our Register 1 */
232 #define PCI_OUR_REG_2 0x44 /* 32 bit Our Register 2 */
233 #define PCI_OUR_STATUS 0x7c /* 32 bit Adapter Status Register */
234 #define PCI_OUR_REG_3 0x80 /* 32 bit Our Register 3 */
235 #define PCI_OUR_REG_4 0x84 /* 32 bit Our Register 4 */
236 #define PCI_OUR_REG_5 0x88 /* 32 bit Our Register 5 */
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/freebsd/sys/contrib/dev/mediatek/mt76/mt7615/
H A Dmac.h15 #define MT_RXD0_NORMAL_IP_SUM BIT(23)
16 #define MT_RXD0_NORMAL_UDP_TCP_SUM BIT(24)
17 #define MT_RXD0_NORMAL_GROUP_1 BIT(25)
18 #define MT_RXD0_NORMAL_GROUP_2 BIT(26)
19 #define MT_RXD0_NORMAL_GROUP_3 BIT(27)
20 #define MT_RXD0_NORMAL_GROUP_4 BIT(28)
25 #define MT_RXD1_MID_AMSDU_FRAME BIT(1)
26 #define MT_RXD1_LAST_AMSDU_FRAME BIT(0)
27 #define MT_RXD1_NORMAL_HDR_TRANS BIT(23)
28 #define MT_RXD1_NORMAL_HDR_OFFSET BIT(22)
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H A Dregs.h40 #define MT_TOP_3NSS BIT(24)
49 #define MT_TOP_MISC2_FW_PWR_ON BIT(1)
71 #define MT_HIF_LOGIC_RST_N BIT(4)
74 #define MT_PDMA_AXI_SLPPROT_ENABLE BIT(0)
75 #define MT_PDMA_AXI_SLPPROT_RDY BIT(16)
78 #define MT_PDMA_TX_IDX_BUSY BIT(2)
79 #define MT_PDMA_BUSY_IDX BIT(31)
93 #define MT_CFG_LPCR_HOST_FW_OWN BIT(0)
94 #define MT_CFG_LPCR_HOST_DRV_OWN BIT(1)
101 #define MT_MCU_INT_EVENT_PDMA_STOPPED BIT(0)
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/freebsd/lib/libc/arm/string/
H A Dmemcpy.S182 /* At least 8 bytes remaining */
188 /* Less than 8 bytes remaining */
220 mov r4, ip, lsr #8
227 mov r5, r5, lsr #8
229 mov r6, r6, lsr #8
231 mov r7, r7, lsr #8
249 mov r4, ip, lsr #8
304 orr r4, r4, r5, lsl #8
306 orr r5, r5, r6, lsl #8
308 orr r6, r6, r7, lsl #8
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/freebsd/sys/dev/qat/include/
H A Dicp_qat_hw.h15 ICP_QAT_HW_AE_8 = 8,
41 ICP_QAT_HW_AUTH_ALGO_AES_CBC_MAC = 8,
83 ICP_ACCEL_CAPABILITIES_CRYPTO_SYMMETRIC = BIT(0),
84 ICP_ACCEL_CAPABILITIES_CRYPTO_ASYMMETRIC = BIT(1),
85 ICP_ACCEL_CAPABILITIES_CIPHER = BIT(2),
86 ICP_ACCEL_CAPABILITIES_AUTHENTICATION = BIT(3),
87 ICP_ACCEL_CAPABILITIES_RESERVED_1 = BIT(4),
88 ICP_ACCEL_CAPABILITIES_COMPRESSION = BIT(5),
89 ICP_ACCEL_CAPABILITIES_DEPRECATED = BIT(6),
90 ICP_ACCEL_CAPABILITIES_RAND = BIT(7),
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/freebsd/sys/contrib/device-tree/include/dt-bindings/mfd/
H A Dstm32h7-rcc.h17 #define STM32H7_AHB3_RESET(bit) (STM32H7_RCC_AHB3_##bit + (0x7C * 8)) argument
28 #define STM32H7_AHB1_RESET(bit) (STM32H7_RCC_AHB1_##bit + (0x80 * 8)) argument
37 #define STM32H7_AHB2_RESET(bit) (STM32H7_RCC_AHB2_##bit + (0x84 * 8)) argument
48 #define STM32H7_RCC_AHB4_GPIOI 8
56 #define STM32H7_AHB4_RESET(bit) (STM32H7_RCC_AHB4_##bit + (0x88 * 8)) argument
62 #define STM32H7_APB3_RESET(bit) (STM32H7_RCC_APB3_##bit + (0x8C * 8)) argument
73 #define STM32H7_RCC_APB1L_TIM14 8
90 #define STM32H7_APB1L_RESET(bit) (STM32H7_RCC_APB1L_##bit + (0x90 * 8)) argument
97 #define STM32H7_RCC_APB1H_FDCAN 8
99 #define STM32H7_APB1H_RESET(bit) (STM32H7_RCC_APB1H_##bit + (0x94 * 8)) argument
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/freebsd/contrib/wpa/src/crypto/
H A Dmilenage.c27 * @opc: OPc = 128-bit value derived from OP and K
28 * @k: K = 128-bit subscriber key
29 * @_rand: RAND = 128-bit random challenge
30 * @sqn: SQN = 48-bit sequence number
31 * @amf: AMF = 16-bit authentication management field
32 * @mac_a: Buffer for MAC-A = 64-bit network authentication code, or %NULL
33 * @mac_s: Buffer for MAC-S = 64-bit resync authentication code, or %NULL
51 os_memcpy(tmp2 + 8, tmp2, 8); in milenage_f1()
55 /* rotate (tmp2 XOR OP_C) by r1 (= 0x40 = 8 bytes) */ in milenage_f1()
57 tmp3[(i + 8) % 16] = tmp2[i] ^ opc[i]; in milenage_f1()
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/freebsd/sys/contrib/dev/rtw88/
H A Dreg.h9 #define BIT_FEN_EN_25_1 BIT(13)
10 #define BIT_FEN_ELDR BIT(12)
11 #define BIT_FEN_CPUEN BIT(2)
12 #define BIT_FEN_BB_GLB_RST BIT(1)
13 #define BIT_FEN_BB_RSTB BIT(0)
14 #define BIT_R_DIS_PRST BIT(6)
15 #define BIT_WLOCK_1C_B6 BIT(5)
17 #define BIT_PFM_WOWL BIT(3)
19 #define BIT_CPU_CLK_EN BIT(14)
22 #define BIT_ANA8M BIT(
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/freebsd/sys/compat/linuxkpi/common/include/linux/
H A Dieee80211.h58 #define IEEE80211_CCMP_HDR_LEN 8 /* 802.11i .. net80211 comment */
60 #define IEEE80211_CCMP_MIC_LEN 8 /* || 16 */
61 #define IEEE80211_CCMP_256_HDR_LEN 8
63 #define IEEE80211_GCMP_HDR_LEN 8
93 #define IEEE80211_P2P_OPPPS_ENABLE_BIT BIT(7)
105 IEEE80211_RATE_SHORT_PREAMBLE = BIT(0),
109 IEEE80211_RC_BW_CHANGED = BIT(0),
110 IEEE80211_RC_NSS_CHANGED = BIT(1),
111 IEEE80211_RC_SUPP_RATES_CHANGED = BIT(2),
112 IEEE80211_RC_SMPS_CHANGED = BIT(3),
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/freebsd/contrib/wpa/src/utils/
H A Dbitfield.c25 bf = os_zalloc(sizeof(*bf) + (max_bits + 7) / 8); in bitfield_alloc()
40 void bitfield_set(struct bitfield *bf, size_t bit) in bitfield_set() argument
42 if (bit >= bf->max_bits) in bitfield_set()
44 bf->bits[bit / 8] |= BIT(bit % 8); in bitfield_set()
48 void bitfield_clear(struct bitfield *bf, size_t bit) in bitfield_clear() argument
50 if (bit >= bf->max_bits) in bitfield_clear()
52 bf->bits[bit / 8] &= ~BIT(bit % 8); in bitfield_clear()
56 int bitfield_is_set(struct bitfield *bf, size_t bit) in bitfield_is_set() argument
58 if (bit >= bf->max_bits) in bitfield_is_set()
60 return !!(bf->bits[bit / 8] & BIT(bit % 8)); in bitfield_is_set()
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