Lines Matching +full:8 +full:bit
40 #define MT_TOP_3NSS BIT(24)
49 #define MT_TOP_MISC2_FW_PWR_ON BIT(1)
71 #define MT_HIF_LOGIC_RST_N BIT(4)
74 #define MT_PDMA_AXI_SLPPROT_ENABLE BIT(0)
75 #define MT_PDMA_AXI_SLPPROT_RDY BIT(16)
78 #define MT_PDMA_TX_IDX_BUSY BIT(2)
79 #define MT_PDMA_BUSY_IDX BIT(31)
93 #define MT_CFG_LPCR_HOST_FW_OWN BIT(0)
94 #define MT_CFG_LPCR_HOST_DRV_OWN BIT(1)
101 #define MT_MCU_INT_EVENT_PDMA_STOPPED BIT(0)
102 #define MT_MCU_INT_EVENT_PDMA_INIT BIT(1)
103 #define MT_MCU_INT_EVENT_SER_TRIGGER BIT(2)
104 #define MT_MCU_INT_EVENT_RESET_DONE BIT(3)
110 #define MT_INT_RX_DONE(_n) BIT(_n)
113 #define MT_INT_TX_DONE(_n) BIT((_n) + 4)
114 #define MT7663_INT_MCU_CMD BIT(29)
115 #define MT_INT_MCU_CMD BIT(30)
118 #define MT_WPDMA_GLO_CFG_TX_DMA_EN BIT(0)
119 #define MT_WPDMA_GLO_CFG_TX_DMA_BUSY BIT(1)
120 #define MT_WPDMA_GLO_CFG_RX_DMA_EN BIT(2)
121 #define MT_WPDMA_GLO_CFG_RX_DMA_BUSY BIT(3)
123 #define MT_WPDMA_GLO_CFG_TX_WRITEBACK_DONE BIT(6)
124 #define MT_WPDMA_GLO_CFG_BIG_ENDIAN BIT(7)
125 #define MT_WPDMA_GLO_CFG_TX_BT_SIZE_BIT0 BIT(9)
126 #define MT_WPDMA_GLO_CFG_BYPASS_TX_SCH BIT(9) /* MT7622 */
128 #define MT_WPDMA_GLO_CFG_FIFO_LITTLE_ENDIAN BIT(12)
130 #define MT_WPDMA_GLO_CFG_SW_RESET BIT(24)
131 #define MT_WPDMA_GLO_CFG_FIRST_TOKEN_ONLY BIT(26)
132 #define MT_WPDMA_GLO_CFG_OMIT_TX_INFO BIT(28)
139 #define MT_MCU_CMD_CLEAR_FW_OWN BIT(0)
140 #define MT_MCU_CMD_STOP_PDMA_FW_RELOAD BIT(1)
141 #define MT_MCU_CMD_STOP_PDMA BIT(2)
142 #define MT_MCU_CMD_RESET_DONE BIT(3)
143 #define MT_MCU_CMD_RECOVERY_DONE BIT(4)
144 #define MT_MCU_CMD_NORMAL_STATE BIT(5)
145 #define MT_MCU_CMD_LMAC_ERROR BIT(24)
146 #define MT_MCU_CMD_PSE_ERROR BIT(25)
147 #define MT_MCU_CMD_PLE_ERROR BIT(26)
148 #define MT_MCU_CMD_PDMA_ERROR BIT(27)
149 #define MT_MCU_CMD_PCIE_ERROR BIT(28)
183 #define MT_HIF_0_EMPTY_MASK BIT(16)
184 #define MT_HIF_1_EMPTY_MASK BIT(17)
192 #define MT_PP_TXDWCNT_TX1_ADD_DW_CNT GENMASK(15, 8)
198 #define MT_WF_PHY_WF2_RFCTRL0_LPBCN_EN BIT(9)
228 #define MT_WF_PHY_PD_BLK(_phy) ((_phy) ? BIT(25) : BIT(19))
239 GENMASK(8, 1)
254 #define MT_CFG_CCR_MAC_D1_1X_GC_EN BIT(24)
255 #define MT_CFG_CCR_MAC_D0_1X_GC_EN BIT(25)
256 #define MT_CFG_CCR_MAC_D1_2X_GC_EN BIT(30)
257 #define MT_CFG_CCR_MAC_D0_2X_GC_EN BIT(31)
263 #define MT_AGG_ARCR_INIT_RATE1 BIT(0)
264 #define MT_AGG_ARCR_RTS_RATE_THR GENMASK(12, 8)
266 #define MT_AGG_ARCR_RATE_DOWN_RATIO_EN BIT(19)
281 #define MT_AGG_ACR_NO_BA_RULE BIT(0)
282 #define MT_AGG_ACR_NO_BA_AR_RULE BIT(1)
283 #define MT_AGG_ACR_PKT_TIME_EN BIT(2)
288 #define MT_AGG_SCR_NLNAV_MID_PTEC_DIS BIT(3)
294 #define MT_ARB_RQCR_RX_START BIT(0)
295 #define MT_ARB_RQCR_RXV_START BIT(4)
296 #define MT_ARB_RQCR_RXV_R_EN BIT(7)
297 #define MT_ARB_RQCR_RXV_T_EN BIT(8)
301 #define MT_ARB_SCR_TX0_DISABLE BIT(8)
302 #define MT_ARB_SCR_RX0_DISABLE BIT(9)
303 #define MT_ARB_SCR_TX1_DISABLE BIT(10)
304 #define MT_ARB_SCR_RX1_DISABLE BIT(11)
319 #define MT_IFS_EIFS GENMASK(8, 0)
327 #define MT_TMAC_CTCR0_INS_DDLMT_EN BIT(17)
328 #define MT_TMAC_CTCR0_INS_DDLMT_VHT_SMPDU_EN BIT(18)
334 #define MT_WF_RFCR_DROP_STBC_MULTI BIT(0)
335 #define MT_WF_RFCR_DROP_FCSFAIL BIT(1)
336 #define MT_WF_RFCR_DROP_VERSION BIT(3)
337 #define MT_WF_RFCR_DROP_PROBEREQ BIT(4)
338 #define MT_WF_RFCR_DROP_MCAST BIT(5)
339 #define MT_WF_RFCR_DROP_BCAST BIT(6)
340 #define MT_WF_RFCR_DROP_MCAST_FILTERED BIT(7)
341 #define MT_WF_RFCR_DROP_A3_MAC BIT(8)
342 #define MT_WF_RFCR_DROP_A3_BSSID BIT(9)
343 #define MT_WF_RFCR_DROP_A2_BSSID BIT(10)
344 #define MT_WF_RFCR_DROP_OTHER_BEACON BIT(11)
345 #define MT_WF_RFCR_DROP_FRAME_REPORT BIT(12)
346 #define MT_WF_RFCR_DROP_CTL_RSV BIT(13)
347 #define MT_WF_RFCR_DROP_CTS BIT(14)
348 #define MT_WF_RFCR_DROP_RTS BIT(15)
349 #define MT_WF_RFCR_DROP_DUPLICATE BIT(16)
350 #define MT_WF_RFCR_DROP_OTHER_BSS BIT(17)
351 #define MT_WF_RFCR_DROP_OTHER_UC BIT(18)
352 #define MT_WF_RFCR_DROP_OTHER_TIM BIT(19)
353 #define MT_WF_RFCR_DROP_NDPA BIT(20)
354 #define MT_WF_RFCR_DROP_UNWANTED_CTL BIT(21)
360 #define MT_WF_RFCR1_DROP_ACK BIT(4)
361 #define MT_WF_RFCR1_DROP_BF_POLL BIT(5)
362 #define MT_WF_RFCR1_DROP_BA BIT(6)
363 #define MT_WF_RFCR1_DROP_CFEND BIT(7)
364 #define MT_WF_RFCR1_DROP_CFACK BIT(8)
371 #define MT_WF_RMAC_MAR1_START BIT(16)
372 #define MT_WF_RMAC_MAR1_WRITE BIT(17)
377 #define MT_WF_RMAC_MIB_RXTIME_CLR BIT(31)
378 #define MT_WF_RMAC_MIB_RXTIME_EN BIT(30)
391 #define MT_DMA_DCR0_DAMSDU_EN BIT(16)
392 #define MT_DMA_DCR0_RX_VEC_DROP BIT(17)
393 #define MT_DMA_DCR0_RX_HDR_TRANS_EN BIT(19)
396 #define MT_DMA_RCFR0_MCU_RX_MGMT BIT(2)
397 #define MT_DMA_RCFR0_MCU_RX_CTL_NON_BAR BIT(3)
398 #define MT_DMA_RCFR0_MCU_RX_CTL_BAR BIT(4)
399 #define MT_DMA_RCFR0_MCU_RX_TDLS BIT(19)
400 #define MT_DMA_RCFR0_MCU_RX_BYPASS BIT(21)
408 #define MT_WF_PFCR_TDLS_EN BIT(9)
417 #define MT_WTBL_W0_RX_KEY_VALID BIT(26)
418 #define MT_WTBL_W0_RX_IK_VALID BIT(27)
424 #define MT_WTBL_UPDATE_RXINFO_UPDATE BIT(11)
425 #define MT_WTBL_UPDATE_ADM_COUNT_CLEAR BIT(12)
426 #define MT_WTBL_UPDATE_RATE_UPDATE BIT(13)
427 #define MT_WTBL_UPDATE_TX_COUNT_CLEAR BIT(14)
428 #define MT_WTBL_UPDATE_BUSY BIT(31)
432 #define MT_TOP_MISC2_FW_N9_RDY BIT(2)
455 #define MT_WTBL_RIUCR3_RATE6 GENMASK(19, 8)
458 #define MT_WTBL_W3_RTS BIT(22)
461 #define MT_WTBL_W5_SHORT_GI_20 BIT(8)
462 #define MT_WTBL_W5_SHORT_GI_40 BIT(9)
463 #define MT_WTBL_W5_SHORT_GI_80 BIT(10)
464 #define MT_WTBL_W5_SHORT_GI_160 BIT(11)
478 #define MT_LPON_TCR_WRITE BIT(0)
479 #define MT_LPON_TCR_ADJUST BIT(1)
488 #define MT_MIB_SCR0_AGG_CNT_RANGE_EN BIT(21)
545 #define MT_DMASHDL_Q_MAP_SHIFT(_n) (4 * ((_n) % 8))
552 #define MT_LED_CTRL_REPLAY(_n) BIT(0 + (8 * (_n)))
553 #define MT_LED_CTRL_POLARITY(_n) BIT(1 + (8 * (_n)))
554 #define MT_LED_CTRL_TX_BLINK_MODE(_n) BIT(2 + (8 * (_n)))
555 #define MT_LED_CTRL_TX_MANUAL_BLINK(_n) BIT(3 + (8 * (_n)))
556 #define MT_LED_CTRL_BAND(_n) BIT(4 + (8 * (_n)))
557 #define MT_LED_CTRL_TX_OVER_BLINK(_n) BIT(5 + (8 * (_n)))
558 #define MT_LED_CTRL_KICK(_n) BIT(7 + (8 * (_n)))
560 #define MT_LED_STATUS_0(_n) MT_LED_PHYS(0x10 + ((_n) * 8))
561 #define MT_LED_STATUS_1(_n) MT_LED_PHYS(0x14 + ((_n) * 8))
567 #define MT_PDMA_TX_BUSY BIT(0)
568 #define MT_PDMA_RX_BUSY BIT(1)
572 #define MT_EFUSE_BASE_CTRL_EMPTY BIT(30)
577 #define MT_EFUSE_CTRL_LDO_OFF_TIME GENMASK(13, 8)
580 #define MT_EFUSE_CTRL_VALID BIT(29)
581 #define MT_EFUSE_CTRL_KICK BIT(30)
582 #define MT_EFUSE_CTRL_SEL BIT(31)
589 #define MT_INFRACFG_MISC_AP2CONN_WAKE BIT(1)
594 #define MT_FW_DL_EN BIT(3)
598 #define MT_WL_TX_TMOUT_LMT GENMASK(27, 8)
602 #define MT_WL_RX_AGG_LMT GENMASK(15, 8)
603 #define MT_WL_TX_TMOUT_FUNC_EN BIT(16)
604 #define MT_WL_TX_DPH_CHK_EN BIT(17)
605 #define MT_WL_RX_MPSZ_PAD0 BIT(18)
606 #define MT_WL_RX_FLUSH BIT(19)
607 #define MT_TICK_1US_EN BIT(20)
608 #define MT_WL_RX_AGG_EN BIT(21)
609 #define MT_WL_RX_EN BIT(22)
610 #define MT_WL_TX_EN BIT(23)
611 #define MT_WL_RX_BUSY BIT(30)
612 #define MT_WL_TX_BUSY BIT(31)
618 #define MT_ANT_SWITCH_CON_MODE(_n) (GENMASK(4, 0) << (_n * 8))
619 #define MT_ANT_SWITCH_CON_MODE1(_n) (GENMASK(3, 0) << (_n * 8))