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/freebsd/sys/crypto/openssl/powerpc64/
H A Decp_nistp521-ppc64.S8 .align 5
23 stxv 59,-16*5(12)
41 lxsd 3,0(5)
42 lxsd 4,8(5)
43 lxsd 5,16(5)
44 lxsd 6,24(5)
45 lxsd 7,32(5)
46 lxsd 8,40(5)
47 lxsd 9,48(5)
48 lxsd 10,56(5)
[all …]
/freebsd/sys/crypto/openssl/powerpc64le/
H A Decp_nistp521-ppc64.S8 .align 5
23 stxv 59,-16*5(12)
41 lxsd 3,0(5)
42 lxsd 4,8(5)
43 lxsd 5,16(5)
44 lxsd 6,24(5)
45 lxsd 7,32(5)
46 lxsd 8,40(5)
47 lxsd 9,48(5)
48 lxsd 10,56(5)
[all …]
/freebsd/crypto/openssl/crypto/ec/asm/
H A Decp_nistp521-ppc64.pl48 .align 5
178 xxpermdi $t1,$in1[0],$in1[1],0b00
179 xxpermdi $t2,$in2[1],$in2[0],0b00
182 xxpermdi $t2,$in2[2],$in2[1],0b00
186 xxpermdi $t2,$in2[3],$in2[2],0b00
188 xxpermdi $t3,$in1[2],$in1[3],0b00
189 xxpermdi $t4,$in2[1],$in2[0],0b00
192 xxpermdi $t2,$in2[4],$in2[3],0b00
194 xxpermdi $t4,$in2[2],$in2[1],0b00
198 xxpermdi $t2,$in2[5],$in2[4],0b00
[all …]
/freebsd/contrib/netbsd-tests/ipf/input/
H A Dni111 0b00 5f7b 0000 0000
17 0b00 0939 0000 0000
30 0b00 5f7c 0000 0000
36 0b00 093a 0000 0000
49 0b00 0775 0000 0000
55 0b00 093b 0000 0000
57 07d0 829e 0014 0b00
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/
H A DRISCVBaseInfo.cpp153 {0b01101111, 0b00}, {0b01110000, 0b00}, {0b01110111, 0b00},
154 {0b01111000, 0b00}, {0b01111011, 0b00}, {0b01111100, 0b00},
155 {0b01111101, 0b00}, {0b01111101, 0b01}, {0b01111101, 0b10},
156 {0b01111101, 0b11}, {0b01111110, 0b00}, {0b01111110, 0b01},
157 {0b01111110, 0b10}, {0b01111110, 0b11}, {0b01111111, 0b00},
159 {0b10000000, 0b00}, {0b10000000, 0b01}, {0b10000000, 0b10},
160 {0b10000001, 0b00}, {0b10000010, 0b00}, {0b10000011, 0b00},
161 {0b10000110, 0b00}, {0b10000111, 0b00}, {0b10001110, 0b00},
162 {0b10001111, 0b00}, {0b11111111, 0b00}, {0b11111111, 0b10},
232 else if (SlistEncode > 5 && SlistEncode <= 14) in printRlist()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64InstrFormats.td35 def DestructiveBinary : DestructiveInstTypeEnum<5>;
56 def SMEMatrixTileQ : SMEMatrixTypeEnum<5>;
418 def SImm5Operand : SImmOperand<5>;
421 let DecoderMethod = "DecodeSImm<5>";
426 let DecoderMethod = "DecodeSImm<5>";
431 let DecoderMethod = "DecodeSImm<5>";
437 let DecoderMethod = "DecodeSImm<5>";
489 def UImm5s2Operand : UImmScaledMemoryIndexed<5, 2>;
490 def UImm5s4Operand : UImmScaledMemoryIndexed<5, 4>;
491 def UImm5s8Operand : UImmScaledMemoryIndexed<5, 8>;
[all …]
H A DSMEInstrFormats.td243 // AArch64SystemOperands.td since it only encodes 5 bits including op1;op2,
254 let Inst{7-5} = 0b011; // op2
278 bits<5> Zm;
281 bits<5> Zn;
289 let Inst{9-5} = Zn;
297 …def NAME : sme_fp_outer_product_inst<S, sz, 0b00, TileOp32, zpr_ty, mnemonic>, SMEPseudo2Instr<NAM…
309 …def NAME : sme_fp_outer_product_inst<S, 0b10, 0b00, TileOp64, ZPR64, mnemonic>, SMEPseudo2Instr<NA…
322 let Inst{2-1} = 0b00;
330 let Inst{2-1} = 0b00;
347 bits<5> Zm;
[all …]
H A DSVEInstrFormats.td363 bits<5> pattern;
370 let Inst{9-5} = pattern;
382 def _B : sve_int_ptrue<0b00, opc, asm, PPR8, nxv16i1, op>;
741 let Inst{23-22} = opc{5-4};
772 let Inst{23-22} = opc{5-4};
778 let Inst{8-5} = Pn;
797 class sve_int_pfirst_next<bits<2> sz8_64, bits<5> opc, string asm,
811 let Inst{8-5} = Pg;
822 multiclass sve_int_pfirst<bits<5> opc, string asm, SDPatternOperator op> {
828 multiclass sve_int_pnext<bits<5> opc, string asm, SDPatternOperator op> {
[all …]
H A DAArch64InstrInfo.td32 AssemblerPredicateWithAll<(all_of HasV8_5aOps), "armv8.5a">;
376 def SDT_AArch64CCMP : SDTypeProfile<1, 5,
382 SDTCisVT<5, i32>]>;
383 def SDT_AArch64FCCMP : SDTypeProfile<1, 5,
389 SDTCisVT<5, i32>]>;
677 SDTypeProfile<0, 5, [SDTCisPtrTy<0>,
1267 let Inst{7-5} = op2;
1284 let Inst{7-5} = op2;
1297 let Inst{7-5} = op2;
1313 let Inst{7-5} = op2;
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYInstrFormats16Instr.td9 class J16<bits<5> sop, string opstr, dag ins>
18 class J16_B<bits<5> sop, string opstr>
35 let Inst{7 - 5} = rz;
48 let Inst{5 - 2} = rx;
61 let Inst{5 - 2} = rx;
74 let Inst{5 - 2} = rx;
87 let Inst{5 - 2} = rx;
99 let Inst{5 - 2} = rx;
112 let Inst{5 - 2} = rx;
122 let Inst{5 - 2} = rx;
[all …]
H A DCSKYInstrFormatsF2.td20 class F2_XYZ<bits<5> datatype, bits<6> sop, string opcodestr, dag outs, dag ins,
23 bits<5> vry;
24 bits<5> vrx;
25 bits<5> vrz;
30 let Inst{10-5} = sop;
56 class F2_XZ<bits<5> datatype, RegisterOperand regtype, bits<6> sop, string op, SDNode opnode>
61 class F2_XZ_SET<bits<5> datatype, RegisterOperand regtype, bits<6> sop, string op>
66 class F2_XZ_P<bits<5> datatype, bits<6> sop, string op, list<dag> pattern = [],
71 multiclass F2_XZ_RM<bits<5> datatype, bits<4> sop, string op, dag outs, dag ins> {
72 def _RN : F2_XZ_P<datatype, {sop, 0b00}, op#".rn", [], outs, ins>;
[all …]
H A DCSKYInstrInfo16Instr.td70 def ADDU16XZ : R16_XZ_BINOP<0b1000, 0b00, "addu16", BinOpFrag<(add node:$LHS, node:$RHS)>>;
71 def AND16 : R16_XZ_BINOP<0b1010, 0b00, "and16", BinOpFrag<(and node:$LHS, node:$RHS)>>;
72 def OR16 : R16_XZ_BINOP<0b1011, 0b00, "or16", BinOpFrag<(or node:$LHS, node:$RHS)>>;
77 def MULT16 : R16_XZ_BINOP<0b1111, 0b00, "mult16", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
81 def LSL16 : R16_XZ_BINOP<0b1100, 0b00, "lsl16", BinOpFrag<(shl node:$LHS, node:$RHS)>>;
88 def ZEXTB16 : R16_XZ_UNOP<0b1101, 0b00, "zextb16">;
185 let Inst{5 - 2} = rx;
196 let Inst{5 - 2} = 0;
213 def JMP16 : R16_X_J<0b11100000, 0b00, "jmp16"> {
239 let Inst{15,14} = 0b00;
[all …]
/freebsd/crypto/openssl/crypto/chacha/asm/
H A Dchachap10-ppc.pl170 .align 5
223 .align 5
253 foreach (&VSX_lane_ROUND_4x(0, 5,10,15)) { eval; }
266 vpermdi $xa1,$xa0,$xa2,0b00
268 vpermdi $xa0,$xt0,$xt1,0b00
275 vpermdi $xb1,$xb0,$xb2,0b00
277 vpermdi $xb0,$xt2,$xt3,0b00
284 vpermdi $xc1,$xc0,$xc2,0b00
286 vpermdi $xc0,$xt0,$xt1,0b00
293 vpermdi $xd1,$xd0,$xd2,0b00
[all …]
/freebsd/crypto/openssl/crypto/poly1305/asm/
H A Dpoly1305-ppc.pl161 $PUSH r27,`$FRAME-$SIZE_T*5`($sp)
209 mulld $t0,$h1,$s1 # h1*5*r1
224 mulld $t0,$h2,$s1 # h2*5*r1
243 $POP r27,`$FRAME-$SIZE_T*5`($sp)
252 .byte 0,12,4,1,0x80,5,4,0
260 .align 5
296 addic $h3,$h0,5 # compare to modulus
449 $PUSH r27,`$FRAME-$SIZE_T*5`($sp)
627 $POP r27,`$FRAME-$SIZE_T*5`($sp)
644 .align 5
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMInstrNEON.td612 let Inst{5-4} = Rn{5-4};
650 let Inst{5-4} = Rn{5-4};
657 let Inst{5-4} = Rn{5-4};
740 let Inst{5-4} = Rn{5-4};
749 let Inst{5-4} = Rn{5-4};
756 let Inst{5-4} = Rn{5-4};
804 let Inst{5-4} = Rn{5-4};
834 let Inst{5-4} = Rn{5-4};
841 let Inst{5-4} = Rn{5-4};
947 let Inst{5-4} = Rn{5-4};
[all …]
H A DARMInstrVFP.td189 def VSTRD : ADI5<0b1101, 0b00, (outs), (ins DPR:$Dd, addrmode5:$addr),
194 def VSTRS : ASI5<0b1101, 0b00, (outs), (ins SPR:$Sd, addrmode5:$addr),
204 def VSTRH : AHI5<0b1101, 0b00, (outs), (ins HPR:$Sd, addrmode5fp16:$addr),
476 def VDIVD : ADbI<0b11101, 0b00, 0, 0,
483 def VDIVS : ASbI<0b11101, 0b00, 0, 0,
490 def VDIVH : AHbI<0b11101, 0b00, 0, 0,
572 defm VSELEQ : vsel_inst<"eq", 0b00, 0>;
578 def H : AHbInp<0b11101, 0b00, opc,
584 def S : ASbInp<0b11101, 0b00, opc,
590 def D : ADbInp<0b11101, 0b00, opc,
[all …]
H A DARMInstrThumb2.td33 // {5} 0 ==> lsl
165 // Returns true if all low 5-bits are 1.
489 let Inst{5-4} = ShiftedRm{6-5};
502 let Inst{5-4} = ShiftedRm{6-5};
515 let Inst{5-4} = ShiftedRm{6-5};
584 bits<5> imm;
597 bits<5> imm;
651 let Inst{5-4} = ShiftedRm{6-5};
666 let Inst{5-4} = ShiftedRm{6-5};
763 let Inst{7-6} = 0b00; // imm2
[all …]
H A DARMInstrMVE.td288 def MVE_v16i8 : MVEVectorVTInfo<v16i8, v8i16, v16i1, v8i1, 0b00, "i", ?>;
296 def MVE_v16s8 : MVEVectorVTInfo<v16i8, v8i16, v16i1, v8i1, 0b00, "s", 0b0>;
300 def MVE_v16u8 : MVEVectorVTInfo<v16i8, v8i16, v16i1, v8i1, 0b00, "u", 0b1>;
464 bits<5> imm;
470 let Inst{5-4} = op5_4{1-0};
476 def MVE_UQSHL : MVE_ScalarShiftSRegImm<"uqshl", 0b00>;
489 let Inst{7-6} = 0b00;
490 let Inst{5-4} = op5_4{1-0};
497 def MVE_UQRSHL : MVE_ScalarShiftSRegReg<"uqrshl", 0b00>;
518 bits<5> im
[all...]
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInstrInfoXwch.td19 let Inst{6-5} = funct2;
21 let Inst{1-0} = 0b00;
37 def uimm5_with_predicate : RISCVUImmLeafOp<5> {
42 return isUInt<5>(Imm);
46 // A 5-bit unsigned immediate where the least significant bit is zero.
49 let ParserMatchClass = UImmAsmOperand<5, "Lsb0">;
51 let DecoderMethod = "decodeUImmOperand<5>";
63 ImmLeaf<XLenVT, [{return isShiftedUInt<5, 1>(Imm);}]> {
72 return isShiftedUInt<5, 1>(Imm);
82 def QK_C_LBU : RVInst16CL<0b001, 0b00, (outs GPRC:$rd),
[all …]
H A DRISCVInstrInfoZc.td106 : RVInst16CLB<funct6, 0b00, (outs GPRC:$rd),
111 let Inst{6-5} = imm{0,1};
116 : RVInst16CLH<funct6, funct1, 0b00, (outs GPRC:$rd),
121 let Inst{5} = imm{1};
126 : RVInst16CSB<funct6, 0b00, (outs),
131 let Inst{6-5} = imm{0,1};
136 : RVInst16CSH<funct6, funct1, 0b00, (outs),
141 let Inst{5} = imm{1};
145 class RVZcArith_r<bits<5> funct5, string OpcodeStr> :
151 class RVInstZcCPPP<bits<5> funct5, string opcodestr,
[all …]
H A DRISCVInstrInfoXCV.td17 bits<5> is3;
18 bits<5> is2;
43 def CV_EXTRACT : CVBitManipRII<0b00, 0b000, "cv.extract">;
46 def CV_BCLR : CVBitManipRII<0b00, 0b001, "cv.bclr">;
83 bits<5> imm5;
107 def CV_MACSN : CVInstMacN<0b00, 0b110, "cv.macsn">,
117 def CV_MACUN : CVInstMacN<0b00, 0b111, "cv.macun">,
129 def CV_MULSN : CVInstMulN<0b00, 0b100, "cv.mulsn">,
139 def CV_MULUN : CVInstMulN<0b00, 0b101, "cv.mulun">,
169 bits<5> imm
[all...]
/freebsd/crypto/openssl/crypto/sha/asm/
H A Dkeccak1600p8-ppc.pl90 .align 5
105 vpermdi v31,v26,v27,0b00 ; A[0][0..1]^A[2][0..1]
107 vpermdi v27,v28,v29,0b00 ; A[0][2..3]^A[2][2..3]
126 vpermdi v29,v26,v26,0b00 ; C[0..0]
135 vpermdi v29,v27,v27,0b00 ; C[2..2]
165 vpermdi v0, v26,v28,0b00 ; [0][0] [1][0] < [0][0] [0][3]
166 vpermdi v2, v29,v5, 0b00 ; [0][2] [1][2] < [2][2] [2][0]
168 vpermdi v5, v1, v4, 0b00 ; [2][0] [3][0] < [0][1] [0][4]
172 vpermdi v7, v8, v6, 0b00 ; [2][2] [3][2] < [2][3] [2][1]
208 vpermdi v27,v12,v10,0b00 ; A[4][4..0]
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/ARC/
H A DARCInstrFormats.td84 def WordSM : DataSizeMode<0b00, "", "">;
89 def NoAM : AddrMode<0b00, "", "">;
129 // All 32-bit ARC instructions have a 5-bit "major" opcode class designator
145 // A - Inst[5-0] = A[5-0], when the format has A. A is always a register.
146 // B - Inst[14-12] = B[5-3], Inst[26-24] = B[2-0], when the format has B.
148 // C - Inst[11-6] = C[5-0], when the format has C. C can either be a register,
155 class F32_BR<bits<5> major, dag outs, dag ins, bit b16, string asmstr,
162 let Inst{5} = N;
165 class F32_BR_COND<bits<5> major, dag outs, dag ins, bit b16, string asmstr,
169 bits<5> cc;
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsMSAInstrFormats.td31 bits<5> ws;
32 bits<5> wd;
40 let Inst{5-0} = minor;
44 bits<5> ws;
45 bits<5> wd;
53 let Inst{5-0} = minor;
57 bits<5> ws;
58 bits<5> wd;
59 bits<5> m;
66 let Inst{5-0} = minor;
[all …]
/freebsd/sys/contrib/device-tree/src/arm/ti/omap/
H A Domap3430es1-clocks.dtsi33 gfx_cg1_ck: gfx_cg1_ck@b00 {
41 gfx_cg2_ck: gfx_cg2_ck@b00 {
64 fshostusb_fck: clock-fshostusb-fck@5 {
65 reg = <5>;
153 usb_l4_gate_ick: clock-usb-l4-gate-ick@5 {
154 reg = <5>;

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