Lines Matching +full:5 +full:b00
33 // {5} 0 ==> lsl
165 // Returns true if all low 5-bits are 1.
489 let Inst{5-4} = ShiftedRm{6-5};
502 let Inst{5-4} = ShiftedRm{6-5};
515 let Inst{5-4} = ShiftedRm{6-5};
584 bits<5> imm;
597 bits<5> imm;
651 let Inst{5-4} = ShiftedRm{6-5};
666 let Inst{5-4} = ShiftedRm{6-5};
763 let Inst{7-6} = 0b00; // imm2
764 let Inst{5-4} = 0b00; // type
849 let Inst{7-6} = 0b00; // imm2
850 let Inst{5-4} = 0b00; // type
1006 let Inst{7-6} = 0b00; // imm2
1007 let Inst{5-4} = 0b00; // type
1048 let Inst{7-6} = 0b00; // imm2
1049 let Inst{5-4} = 0b00; // type
1086 // 5-bit imm
1096 let Inst{5-4} = opcod;
1166 let Inst{7-6} = 0b00; // imm2
1167 let Inst{5-4} = 0b00; // type
1220 let Inst{26-25} = 0b00;
1241 let Inst{26-25} = 0b00;
1253 let Inst{3-0} = addr{5-2}; // Rm
1254 let Inst{5-4} = addr{1-0}; // imm
1267 let Inst{26-25} = 0b00;
1342 let Inst{3-0} = addr{5-2}; // Rm
1343 let Inst{5-4} = addr{1-0}; // imm
1360 let Inst{5-4} = rot; // rotate
1394 let Inst{5-4} = rot;
1464 defm t2LDRB : T2I_ld<0, 0b00, "ldrb", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
1470 defm t2LDRSB : T2I_ld<1, 0b00, "ldrsb", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
1542 def t2LDRB_PRE : T2Ipreldst<0, 0b00, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1548 def t2LDRB_POST : T2Ipostldst<0, 0b00, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1566 def t2LDRSB_PRE : T2Ipreldst<1, 0b00, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1572 def t2LDRSB_POST : T2Ipostldst<1, 0b00, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1647 let Inst{26-25} = 0b00;
1662 def t2LDRBT : T2IldT<0, 0b00, "ldrbt", IIC_iLoad_bh_i>;
1664 def t2LDRSBT : T2IldT<1, 0b00, "ldrsbt", IIC_iLoad_bh_i>;
1678 let Inst{5-4} = bit54;
1689 def t2LDAB : T2Ildacq<0b1101, 0b00, (outs rGPR:$Rt),
1698 defm t2STRB:T2I_st<0b00,"strb", IIC_iStore_bh_i, IIC_iStore_bh_si,
1728 def t2STRB_PRE : T2Ipreldst<0, 0b00, 0, 1, (outs GPRnopc:$Rn_wb),
1758 def t2STRB_POST : T2Ipostldst<0, 0b00, 0, 0, (outs GPRnopc:$Rn_wb),
1832 let Inst{26-25} = 0b00;
1848 def t2STRBT : T2IstT<0b00, "strbt", IIC_iStore_bh_i>;
1893 let Inst{5-4} = bit54;
1903 def t2STLB : T2Istrrel<0b00, (outs), (ins rGPR:$Rt, addr_offset_none:$addr),
1968 let Inst{3-0} = addr{5-2}; // Rm
1969 let Inst{5-4} = addr{1-0}; // imm2
2060 let Inst{26-25} = 0b00;
2075 let Inst{26-25} = 0b00;
2090 let Inst{26-25} = 0b00;
2105 let Inst{26-25} = 0b00;
2129 let Inst{26-25} = 0b00;
2147 let Inst{26-25} = 0b00;
2165 let Inst{26-25} = 0b00;
2183 let Inst{26-25} = 0b00;
2694 bits<5> sat_imm;
2698 let Inst{21} = sh{5};
2705 let Inst{5} = 0;
2712 let Inst{23-22} = 0b00;
2713 let Inst{5} = 0;
2719 let Inst{23-22} = 0b00;
2772 defm t2LSL : T2I_sh_ir<0b00, "lsl", imm1_31, shl>;
2814 let Inst{5-4} = 0b01; // Shift type.
2829 let Inst{5-4} = 0b10; // Shift type.
2855 bits<5> msb;
2856 bits<5> lsb;
2882 let Inst{5} = 0; // should be 0.
2885 let msb{4-0} = imm{9-5};
2936 let Inst{5} = 0; // should be 0.
2939 let msb{4-0} = imm{9-5};
2983 let Inst{7-6} = 0b00; // imm2
2984 let Inst{5-4} = 0b00; // type
3134 let Inst{7-6} = 0b00;
3135 let Inst{5-4} = op5_4;
3138 def t2SMULBB : T2ThreeRegSMUL<0b001, 0b00, "smulbb",
3146 def t2SMULWB : T2ThreeRegSMUL<0b011, 0b00, "smulwb",
3180 let Inst{7-6} = 0b00;
3181 let Inst{5-4} = op5_4;
3184 def t2SMLABB : T2FourRegSMLA<0b001, 0b00, "smlabb",
3192 def t2SMLAWB : T2FourRegSMLA<0b011, 0b00, "smlawb",
3336 let Inst{5-4} = op2;
3340 def t2CLZ : T2I_misc<0b11, 0b00, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
3349 def t2REV : T2I_misc<0b01, 0b00, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
3381 let Inst{5} = 0; // BT form
3384 bits<5> sh;
3410 let Inst{5} = 1; // TB form
3413 bits<5> sh;
3451 let Inst{5-4} = sz;
3454 def t2CRC32B : T2I_crc32<0, 0b00, "b", int_arm_crc32b>;
3455 def t2CRC32CB : T2I_crc32<1, 0b00, "cb", int_arm_crc32cb>;
3500 let Inst{7-6} = 0b00; // imm2
3501 let Inst{5-4} = 0b00; // type
3643 // Armv8.5-A speculation barrier
3980 let Inst{15-5} = 0b11110000000;
3993 let Inst{15-5} = 0b11110000000;
4081 let Inst{9} = target{5};
4093 let Inst{9} = target{5};
4109 bits<5> mode;
4115 let Inst{7-5} = iflags;
4150 def : t2InstAlias<"sevl$p.w", (t2HINT 5, pred:$p), 1> {
4213 bits<5> mode;
4219 let Inst{15-5} = 0b11000000000;
4224 def t2SRSDB_UPD : T2SRS<0b00, 1, (outs), (ins imm0_31:$mode), NoItinerary,
4226 def t2SRSDB : T2SRS<0b00, 0, (outs), (ins imm0_31:$mode), NoItinerary,
4507 let Inst{20} = banked{5}; // R bit
4511 let Inst{7-5} = 0b001;
4547 bits<5> mask;
4558 // separate encoding (distinguished by bit 5.
4566 let Inst{20} = banked{5}; // R bit
4570 let Inst{7-5} = 0b001;
4590 let Inst{9-8} = 0b00;
4621 let Inst{7-5} = opc2;
4739 let Inst{7-5} = opc2;
4765 let Inst{7-5} = opc2;
4822 let Inst{5-0} = 0b000000;
4824 let Unpredictable{5-0} = 0b111111;
4827 def t2TT : T2TT<0b00, "tt",
5566 let Inst{13-12} = 0b00;
5588 let Inst{13-12} = 0b00;
5599 let Inst{13-12} = 0b00;
5800 let Inst{11-5} = 0b1111000;