Lines Matching +full:5 +full:b00
288 def MVE_v16i8 : MVEVectorVTInfo<v16i8, v8i16, v16i1, v8i1, 0b00, "i", ?>;
296 def MVE_v16s8 : MVEVectorVTInfo<v16i8, v8i16, v16i1, v8i1, 0b00, "s", 0b0>;
300 def MVE_v16u8 : MVEVectorVTInfo<v16i8, v8i16, v16i1, v8i1, 0b00, "u", 0b1>;
464 bits<5> imm;
470 let Inst{5-4} = op5_4{1-0};
476 def MVE_UQSHL : MVE_ScalarShiftSRegImm<"uqshl", 0b00>;
489 let Inst{7-6} = 0b00;
490 let Inst{5-4} = op5_4{1-0};
497 def MVE_UQRSHL : MVE_ScalarShiftSRegReg<"uqrshl", 0b00>;
518 bits<5> imm;
524 let Inst{5-4} = op5_4{1-0};
539 let Inst{5} = op5;
577 def MVE_LSLLi : MVE_ScalarShiftDRegImm<"lsll", 0b00, ?, [(set tGPREven:$RdaLo, tGPROdd:$RdaHi,
589 def MVE_UQSHLL : MVE_ScalarShiftDRegImm<"uqshll", 0b00, 0b1>;
624 let Inst{5} = Qm{3};
674 let Inst{5} = A;
773 let Inst{5} = A;
791 SDTCisVec<4>, SDTCisVec<5>
845 let Inst{6-5} = 0b00;
906 let Inst{6-5} = 0b00;
1032 let Inst{7-6} = 0b00;
1033 let Inst{5} = A;
1135 SDTCisVec<4>, SDTCisVec<5>
1143 def SDTVecReduce2LAP : SDTypeProfile<2, 5, [ // VMLALVA
1145 SDTCisVec<4>, SDTCisVec<5>, SDTCisVec<6>
1268 let Inst{7-6} = 0b00;
1269 let Inst{5} = A;
1419 let Inst{5} = Qm{3};
1511 let Inst{5} = Qm{3};
1516 "vbic", "", "$Qd, $Qn, $Qm", "", 0b00> {
1541 let Inst{17-16} = 0b00;
1549 def MVE_VREV64_8 : MVE_VREV<"vrev64", "8", 0b00, 0b00, 0b11, "@earlyclobber $Qd">;
1550 def MVE_VREV64_16 : MVE_VREV<"vrev64", "16", 0b01, 0b00, 0b11, "@earlyclobber $Qd">;
1551 def MVE_VREV64_32 : MVE_VREV<"vrev64", "32", 0b10, 0b00, 0b11, "@earlyclobber $Qd">;
1553 def MVE_VREV32_8 : MVE_VREV<"vrev32", "8", 0b00, 0b01, 0b10>;
1556 def MVE_VREV16_8 : MVE_VREV<"vrev16", "8", 0b00, 0b10, 0b01>;
1591 "vmvn", "", "$Qd, $Qm", "", 0b00> {
1614 iname, "", "$Qd, $Qn, $Qm", "", 0b00> {
1630 def MVE_VEOR : MVE_bit_ops<"veor", 0b00, 0b1>;
1633 def MVE_VAND : MVE_bit_ops<"vand", 0b00, 0b0>;
1711 let Inst{5} = opcode;
1798 let Inst{6-5} = 0b00;
1810 let Inst{5} = 0b1;
1825 let Inst{5} = Idx{0};
1827 let VecSize = 0b00;
1955 let Inst{5} = Qm{3};
2390 let Inst{5} = E;
2397 def MVE_VDUP8 : MVE_VDUP<"8", 0b1, 0b0, 0b00>;
2451 let Inst{5} = Qm{3};
2462 let Inst{17-16} = 0b00;
2505 let Inst{12-11} = 0b00;
2604 let Inst{5} = op;
2614 def MVE_VMOVimmi8 : MVE_mod_imm<"vmov", "i8", {1,1,1,0}, 0b0, (ins nImmSplatI8:$imm), 0b00>;
2678 let Inst{5} = Qm{3};
2725 bits<5> imm;
2748 let Inst{5} = Qm{3};
2893 defm MVE_VSHLL_lws8 : MVE_VSHLL_lw<"vshll", "s8", 0b00, 0b0, "$Qd, $Qm, #8">;
2895 defm MVE_VSHLL_lwu8 : MVE_VSHLL_lw<"vshll", "u8", 0b00, 0b1, "$Qd, $Qm, #8">;
2942 bits<5> imm;
2985 bits<5> imm;
3036 bits<5> imm;
3155 let Inst{5} = Qm{3};
3219 let Inst{12-11} = 0b00;
3221 let Inst{5} = Qm{3};
3250 def MVE_VSRIimm8 : MVE_VSxI_imm<"vsri", "8", 0b0, shr_imm8, 0b00> {
3262 def MVE_VSLIimm8 : MVE_VSxI_imm<"vsli", "8", 0b1, imm0_7, 0b00> {
3454 def MVE_VSHR_imms8 : MVE_VSHR_imm<"s8", (ins shr_imm8:$imm), 0b00> {
3459 def MVE_VSHR_immu8 : MVE_VSHR_imm<"u8", (ins shr_imm8:$imm), 0b00> {
3496 def MVE_VSHL_immi8 : MVE_VSHL_imm<"i8", (ins imm0_7:$imm), 0b00> {
3554 let Inst{5} = Qm{3};
4017 defm a : MVE_VCVT_fp_int_anpm_inner<Int, Flt, "a", 0b00>;
4151 let Inst{5} = Qm{3};
4214 let Inst{5} = Qm{3};
4258 def MVE_VCMPi8 : MVE_VCMPqqi<"i8", 0b00>;
4262 def MVE_VCMPu8 : MVE_VCMPqqu<"u8", 0b00>;
4266 def MVE_VCMPs8 : MVE_VCMPqqs<"s8", 0b00>;
4288 let Inst{5} = fc{1};
4306 let Inst{5} = 0b0;
4312 let Inst{5} = 0b1;
4323 def MVE_VCMPi8r : MVE_VCMPqri<"i8", 0b00>;
4327 def MVE_VCMPu8r : MVE_VCMPqru<"u8", 0b00>;
4331 def MVE_VCMPs8r : MVE_VCMPqrs<"s8", 0b00>;
4540 let Inst{5} = Qm{3};
4869 defm MVE_VMOVNi16 : MVE_VxMOVxN_halves<"vmovn", "i16", 0b1, 0b0, 0b00>;
4871 defm MVE_VQMOVNs16 : MVE_VxMOVxN_halves<"vqmovn", "s16", 0b0, 0b1, 0b00>;
4873 defm MVE_VQMOVNu16 : MVE_VxMOVxN_halves<"vqmovn", "u16", 0b1, 0b1, 0b00>;
4875 defm MVE_VQMOVUNs16 : MVE_VxMOVxN_halves<"vqmovun", "s16", 0b0, 0b0, 0b00>;
4997 let Inst{8-7} = 0b00;
5254 let Inst{5} = bit_5;
5322 let Inst{5} = 0b1;
5369 let Inst{5} = 0b0;
5499 let Inst{5} = 0b1;
5503 def MVE_VBRSR8 : MVE_VBRSR<"vbrsr", "8", 0b00>;
5549 let Inst{5} = 0b1;
5574 let Inst{5} = 0b1;
5626 let Inst{5} = 0b0;
5723 let Inst{5} = bit_5;
5784 def MVE_VIDUPu8 : MVE_VxDUP<"vidup", "u8", 0b00, 0b0, v16i8, ARMvidup>;
5788 def MVE_VDDUPu8 : MVE_VxDUP<"vddup", "u8", 0b00, 0b1, v16i8, null_frag>;
5820 def MVE_VIWDUPu8 : MVE_VxWDUP<"viwdup", "u8", 0b00, 0b0>;
5824 def MVE_VDWDUPu8 : MVE_VxWDUP<"vdwdup", "u8", 0b00, 0b1>;
5872 bits<5> Rt;
5873 bits<5> Rt2;
5884 let Inst{12-5} = 0b01111000;
5934 // insertelt's will be in descending order by index, and need to match the 5
5988 let Inst{6-5} = stage;
6054 foreach s = [MVE_vldst24_lanesize< 8, 0b00>,
6076 def SDTARMVST2 : SDTypeProfile<1, 5, [SDTCisPtrTy<0>, SDTCisPtrTy<1>, SDTCisVT<2, i32>, SDTCisVec<3>,
6077 SDTCisSameAs<3, 4>, SDTCisVT<5, i32>]>;
6079 SDTCisSameAs<3, 4>, SDTCisSameAs<3, 5>,
6155 def MVE_memB: MVE_memsz<0b00, 0, AddrModeT2_i7, "b", ["", "u", "s"]>;
6350 let Inst{5} = 0;
6612 let Inst{5} = Qm{3};
6626 def MVE_VPTv16i8 : MVE_VPTt1i<"i8", 0b00>;
6637 def MVE_VPTv16u8 : MVE_VPTt1u<"u8", 0b00>;
6647 def MVE_VPTv16s8 : MVE_VPTt1s<"s8", 0b00>;
6657 let Inst{5} = fc{1};
6665 let Inst{5} = 0b0;
6670 def MVE_VPTv16i8r : MVE_VPTt2i<"i8", 0b00>;
6676 let Inst{5} = 0b1;
6681 def MVE_VPTv16u8r : MVE_VPTt2u<"u8", 0b00>;
6691 def MVE_VPTv16s8r : MVE_VPTt2s<"s8", 0b00>;
6726 let Inst{5} = Qm{3};
6741 let Inst{5} = fc{1};
6749 !strconcat("vpst", "${Mk}"), "", "", 0b00, []> {
6759 let Unpredictable{5} = 0b1;
6766 "vpsel", "", "$Qd, $Qn, $Qm", vpred_n, "", 0b00, []> {
6782 let Inst{5} = Qm{3};
6882 "vpnot", "", "", vpred_n, "", 0b00, []> {
6887 let Unpredictable{5} = 0b1;
6957 def MVE_DLSTP_8 : MVE_DLSTP<"dlstp.8", 0b00>;
6962 def MVE_WLSTP_8 : MVE_WLSTP<"wlstp.8", 0b00>;
6970 let Inst{22-21} = 0b00;