Lines Matching +full:5 +full:b00
84 def WordSM : DataSizeMode<0b00, "", "">;
89 def NoAM : AddrMode<0b00, "", "">;
129 // All 32-bit ARC instructions have a 5-bit "major" opcode class designator
145 // A - Inst[5-0] = A[5-0], when the format has A. A is always a register.
146 // B - Inst[14-12] = B[5-3], Inst[26-24] = B[2-0], when the format has B.
148 // C - Inst[11-6] = C[5-0], when the format has C. C can either be a register,
155 class F32_BR<bits<5> major, dag outs, dag ins, bit b16, string asmstr,
162 let Inst{5} = N;
165 class F32_BR_COND<bits<5> major, dag outs, dag ins, bit b16, string asmstr,
169 bits<5> cc;
175 class F32_BR_UCOND_FAR<bits<5> major, dag outs, dag ins, bit b16, string asmstr,
191 // |26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|9|8|7|6|5|4|3|2|1|0 |
198 // BL targets (functions) are 4-byte aligned, so S25[1-0] = 0b00
199 // |26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|9|8|7|6|5|4|3|2|1|0 |
207 // |26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|9|8|7|6|5|4|3|2|1|0|
217 // |26|25|24|23|22|21|20|19|18|17|16|15 |14|13|12|11|10|9|8|7|6|5|4|3|2|1|0|
218 // |B[2-0] |S9[7-1] | 1|S9[8]|B[5-3] |C |N|u|0|cc |
234 let Inst{14-12} = B{5-3};
236 let Inst{5} = N;
243 // Single Operand Instructions. Inst[5-0] specifies the specific operation
245 // |26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|9|8|7|6|5|4|3|2|1|0|
246 // |B[2-0] | 0| 0| 1| 0| 1| 1| 1| 1| F|B[5-3] |C |subop |
247 class F32_SOP_RR<bits<5> major, bits<6> subop, bit F, dag outs, dag ins,
256 let Inst{23-22} = 0b00;
259 let Inst{14-12} = B{5-3};
261 let Inst{5-0} = subop;
268 // |26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|9|8|7|6|5|4|3|2|1|0|
269 // |B[2-0] | 0| 0| subop| F|B[5-3] |C |A |
270 class F32_DOP_RR<bits<5> major, bits<6> subop, bit F, dag outs, dag ins,
279 let Inst{23-22} = 0b00;
282 let Inst{14-12} = B{5-3};
284 let Inst{5-0} = A;
289 // |26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|9|8|7|6|5|4|3|2|1|0|
290 // |B[2-0] | 1| 1| subop| F|B[5-3] |C |A |
291 class F32_DOP_CC_RR<bits<5> major, bits<6> subop, bit F, dag outs, dag ins,
294 bits<5> cc;
303 let Inst{14-12} = B{5-3};
305 let Inst{5} = 0;
311 // |26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|9|8|7|6|5|4|3|2|1|0|
312 // |B[2-0] | 0| 1| subop| F|B[5-3] |U6 |A |
313 class F32_DOP_RU6<bits<5> major, bits<6> subop, bit F, dag outs, dag ins,
325 let Inst{14-12} = B{5-3};
327 let Inst{5-0} = A;
332 // |26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|9|8|7|6|5|4|3|2|1|0|
333 // |B[2-0] | 1| 1| subop| F|B[5-3] |U6 |1|cc |
334 class F32_DOP_CC_RU6<bits<5> major, bits<6> subop, bit F, dag outs, dag ins,
338 bits<5> cc;
347 let Inst{14-12} = B{5-3};
349 let Inst{5} = 1;
358 // |26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|9|8|7|6|5|4|3|2|1|0|
359 // |B[2-0] | 1| 1| subop| F|B[5-3] |U6 |1|cc |
360 class F32_DOP_CC_RRU6<bits<5> major, bits<6> subop, bit F, dag outs, dag ins,
363 bits<5> cc;
372 let Inst{14-12} = B{5-3};
374 let Inst{5} = 1;
380 // |26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|9|8|7|6|5|4|3|2|1|0|
381 // |B[2-0] | 1| 0| subop| F|B[5-3] |S12[5-0] |S12[11-6] |
382 class F32_DOP_RS12<bits<5> major, bits<6> subop, bit F, dag outs, dag ins,
393 let Inst{14-12} = B{5-3};
394 let Inst{11-6} = S12{5-0};
395 let Inst{5-0} = S12{11-6};
400 // |26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|9|8|7|6|5|4|3|2|1|0|
401 // |B[2-0] | 1| 0| subop| F|B[5-3] |S12[5-0] |S12[11-6] |
402 class F32_SOP_RS12<bits<5> major, bits<6> subop, bit F, dag outs, dag ins,
413 let Inst{14-12} = B{5-3};
414 let Inst{11-6} = S12{5-0};
415 let Inst{5-0} = S12{11-6};
422 // |26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|9|8|7|6|5|4|3|2|1|0|
423 // |B[2-0] | 0| 1| subop| F|B[5-3] |U6 |0|0|0|0|0|0|
424 class F32_SOP_RU6<bits<5> major, bits<6> subop, bit F, dag outs, dag ins,
435 let Inst{14-12} = B{5-3};
437 let Inst{5-0} = 0;
445 class F32_DOP_RLIMM<bits<5> major, bits<6> subop, bit F, dag outs, dag ins,
455 let Inst{23-22} = 0b00;
458 let Inst{14-12} = B{5-3};
460 let Inst{5-0} = A;
480 // |26|25|24|23|22|21|20|19|18|17|16|15 |14|13|12|11|10|9|8|7|6|5|4|3|2|1|0|
481 // |B[2-0] |S9[7-0] |S9[8]|B[5-3] |di|aa |zz |x|A |
493 let Inst{14-12} = B{5-3};
498 let Inst{5-0} = A;
516 // |26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|9|8|7|6|5|4|3|2|1|0|
529 let Inst{14-12} = LImmReg{5-3};
534 let Inst{5-0} = A;
541 // |26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|9|8|7|6|5|4|3|2|1|0|
542 // |B[2-0] |aa | 1| 1| 0|zz | x|di|B[5-3] | 1| 1|1|1|1|0|A |
562 let Inst{14-12} = B{5-3};
564 let Inst{5-0} = A;
571 // |26|25|24|23|22|21|20|19|18|17|16|15 |14|13|12|11|10|9|8|7|6|5 |4|3|2|1|0|
572 // |B[2-0] |S9[7-0] |S9[8]|B[5-3] |C |di|aa |zz |0|
584 let Inst{14-12} = B{5-3};
586 let Inst{5} = di;
606 // |26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|9|8|7|6|5 |4|3|2|1|0|
619 let Inst{14-12} = LImmReg{5-3};
621 let Inst{5} = di;
631 // |10|9|8|7|6|5|4|3|2|1|0|
637 bits<5> h;
640 let Inst{7-5} = h{2-0};
661 let Inst{7-5} = c;
675 let Inst{6-4} = u6{5-3};
692 let Inst{10-5} = s11{10-5};
696 let s11{1-0} = 0b00;
735 let Inst{7-5} = c;
749 // |10|9|8|7|6|5|4|3|2|1|0|
761 let Inst{7-5} = c;
767 // |10|9|8|7|6|5|4|3|2|1|0|
773 bits<5> h;
777 let Inst{7-5} = h{2-0};
785 bits<5> LImmReg = 0b11110;
786 let Inst{7-5} = LImmReg{2-0};
799 class F16_GEN_DOP_BASE<bits<5> i, dag outs, dag ins, string asmstr> :
806 let Inst{7-5} = c;
810 class F16_GEN_DOP<bits<5> i, string asmstr> :
814 class F16_GEN_DOP_NODST<bits<5> i, string asmstr> :
818 class F16_GEN_DOP_SINGLESRC<bits<5> i, string asmstr> :
838 class F16_LD_ST_OFF<bits<5> opc, dag outs, dag ins, string asmstr> :
845 let Inst{7-5} = c;
848 class F16_LD_ST_WORD_OFF<bits<5> opc, dag outs, dag ins, string asmstr> :
853 let off{1-0} = 0b00;
856 class F16_LD_ST_HALF_OFF<bits<5> opc, dag outs, dag ins, string asmstr> :
860 let Inst{4-0} = off{5-1};
864 class F16_LD_ST_BYTE_OFF<bits<5> opc, dag outs, dag ins, string asmstr> :
867 bits<5> off;
872 // |10|9|8|7|6|5|4|3|2|1|0|
875 InstARC<2, (outs), (ins GPR32:$b, immU<5>:$u5), asmstr, []> {
878 bits<5> u5;
882 let Inst{7-5} = i;
890 // |10|9|8|7|6|5|4|3|2|1|0|
897 bits<5> fieldU;
901 let Inst{7-5} = i;
914 let u7{1-0} = 0b00;
950 class F16_OP_IMM<bits<5> opc, dag outs, dag ins, string asmstr> :
1038 let Inst{5-0} = s{6-1};