1//===-- RISCVInstrInfoXwch.td ------------------------------*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file describes the vendor extension(s) defined by WCH. 10// 11//===----------------------------------------------------------------------===// 12 13class QKStackInst<bits<2> funct2, dag outs, dag ins, 14 string opcodestr, string argstr> 15 : RVInst16<outs, ins, opcodestr, argstr, [], InstFormatOther> { 16 bits<3> rd_rs2; 17 18 let Inst{15-11} = 0b10000; 19 let Inst{6-5} = funct2; 20 let Inst{4-2} = rd_rs2; 21 let Inst{1-0} = 0b00; 22} 23 24//===----------------------------------------------------------------------===// 25// Operand definitions. 26//===----------------------------------------------------------------------===// 27 28def uimm4_with_predicate : RISCVUImmLeafOp<4> { 29 let MCOperandPredicate = [{ 30 int64_t Imm; 31 if (!MCOp.evaluateAsConstantImm(Imm)) 32 return false; 33 return isUInt<4>(Imm); 34 }]; 35} 36 37def uimm5_with_predicate : RISCVUImmLeafOp<5> { 38 let MCOperandPredicate = [{ 39 int64_t Imm; 40 if (!MCOp.evaluateAsConstantImm(Imm)) 41 return false; 42 return isUInt<5>(Imm); 43 }]; 44} 45 46// A 5-bit unsigned immediate where the least significant bit is zero. 47def uimm5_lsb0 : RISCVOp, 48 ImmLeaf<XLenVT, [{return isShiftedUInt<4, 1>(Imm);}]> { 49 let ParserMatchClass = UImmAsmOperand<5, "Lsb0">; 50 let EncoderMethod = "getImmOpValue"; 51 let DecoderMethod = "decodeUImmOperand<5>"; 52 let OperandType = "OPERAND_UIMM5_LSB0"; 53 let MCOperandPredicate = [{ 54 int64_t Imm; 55 if (!MCOp.evaluateAsConstantImm(Imm)) 56 return false; 57 return isShiftedUInt<4, 1>(Imm); 58 }]; 59} 60 61// A 6-bit unsigned immediate where the least significant bit is zero. 62def uimm6_lsb0 : RISCVOp, 63 ImmLeaf<XLenVT, [{return isShiftedUInt<5, 1>(Imm);}]> { 64 let ParserMatchClass = UImmAsmOperand<6, "Lsb0">; 65 let EncoderMethod = "getImmOpValue"; 66 let DecoderMethod = "decodeUImmOperand<6>"; 67 let OperandType = "OPERAND_UIMM6_LSB0"; 68 let MCOperandPredicate = [{ 69 int64_t Imm; 70 if (!MCOp.evaluateAsConstantImm(Imm)) 71 return false; 72 return isShiftedUInt<5, 1>(Imm); 73 }]; 74} 75 76//===----------------------------------------------------------------------===// 77// Instructions 78//===----------------------------------------------------------------------===// 79let Predicates = [HasVendorXwchc], DecoderNamespace = "Xwchc" in { 80 81let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in 82def QK_C_LBU : RVInst16CL<0b001, 0b00, (outs GPRC:$rd), 83 (ins GPRCMem:$rs1, uimm5_with_predicate:$imm), 84 "qk.c.lbu", "$rd, ${imm}(${rs1})">, 85 Sched<[WriteLDB, ReadMemBase]> { 86 bits<5> imm; 87 let Inst{12} = imm{0}; 88 let Inst{11-10} = imm{4-3}; 89 let Inst{6-5} = imm{2-1}; 90} 91let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in 92def QK_C_SB : RVInst16CS<0b101, 0b00, (outs), 93 (ins GPRC:$rs2, GPRCMem:$rs1, 94 uimm5_with_predicate:$imm), 95 "qk.c.sb", "$rs2, ${imm}(${rs1})">, 96 Sched<[WriteSTB, ReadStoreData, ReadMemBase]> { 97 bits<5> imm; 98 let Inst{12} = imm{0}; 99 let Inst{11-10} = imm{4-3}; 100 let Inst{6-5} = imm{2-1}; 101} 102 103let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in 104def QK_C_LHU : RVInst16CL<0b001, 0b10, (outs GPRC:$rd), 105 (ins GPRCMem:$rs1, uimm6_lsb0:$imm), 106 "qk.c.lhu", "$rd, ${imm}(${rs1})">, 107 Sched<[WriteLDH, ReadMemBase]> { 108 bits<6> imm; 109 let Inst{12-10} = imm{5-3}; 110 let Inst{6-5} = imm{2-1}; 111} 112let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in 113def QK_C_SH : RVInst16CS<0b101, 0b10, (outs), 114 (ins GPRC:$rs2, GPRCMem:$rs1, uimm6_lsb0:$imm), 115 "qk.c.sh", "$rs2, ${imm}(${rs1})">, 116 Sched<[WriteSTH, ReadStoreData, ReadMemBase]> { 117 bits<6> imm; 118 let Inst{12-10} = imm{5-3}; 119 let Inst{6-5} = imm{2-1}; 120} 121 122let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in 123def QK_C_LBUSP : QKStackInst<0b00, (outs GPRC:$rd_rs2), 124 (ins SPMem:$rs1, uimm4_with_predicate:$imm), 125 "qk.c.lbusp", "$rd_rs2, ${imm}(${rs1})">, 126 Sched<[WriteLDB, ReadMemBase]> { 127 bits<4> imm; 128 let Inst{10-7} = imm; 129} 130let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in 131def QK_C_SBSP : QKStackInst<0b10, (outs), 132 (ins GPRC:$rd_rs2, SPMem:$rs1, 133 uimm4_with_predicate:$imm), 134 "qk.c.sbsp", "$rd_rs2, ${imm}(${rs1})">, 135 Sched<[WriteSTB, ReadStoreData, ReadMemBase]> { 136 bits<4> imm; 137 let Inst{10-7} = imm; 138} 139 140let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in 141def QK_C_LHUSP : QKStackInst<0b01, (outs GPRC:$rd_rs2), 142 (ins SPMem:$rs1, uimm5_lsb0:$imm), 143 "qk.c.lhusp", "$rd_rs2, ${imm}(${rs1})">, 144 Sched<[WriteLDH, ReadMemBase]> { 145 bits<5> imm; 146 let Inst{10-8} = imm{3-1}; 147 let Inst{7} = imm{4}; 148} 149let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in 150def QK_C_SHSP : QKStackInst<0b11, (outs), 151 (ins GPRC:$rd_rs2, SPMem:$rs1, uimm5_lsb0:$imm), 152 "qk.c.shsp", "$rd_rs2, ${imm}(${rs1})">, 153 Sched<[WriteSTH, ReadStoreData, ReadMemBase]> { 154 bits<5> imm; 155 let Inst{10-8} = imm{3-1}; 156 let Inst{7} = imm{4}; 157} 158 159} // Predicates = [HasVendorXwchc], DecoderNamespace = "Xwchc" 160 161//===----------------------------------------------------------------------===// 162// Assembler Pseudo Instructions 163//===----------------------------------------------------------------------===// 164 165let EmitPriority = 0 in { 166let Predicates = [HasVendorXwchc] in { 167def : InstAlias<"qk.c.lbu $rd, (${rs1})", (QK_C_LBU GPRC:$rd, GPRCMem:$rs1, 0)>; 168def : InstAlias<"qk.c.sb $rs2, (${rs1})", (QK_C_SB GPRC:$rs2, GPRCMem:$rs1, 0)>; 169def : InstAlias<"qk.c.lhu $rd, (${rs1})", (QK_C_LHU GPRC:$rd, GPRCMem:$rs1, 0)>; 170def : InstAlias<"qk.c.sh $rs2, (${rs1})", (QK_C_SH GPRC:$rs2, GPRCMem:$rs1, 0)>; 171def : InstAlias<"qk.c.lbusp $rd, (${rs1})", (QK_C_LBUSP GPRC:$rd, SPMem:$rs1, 0)>; 172def : InstAlias<"qk.c.sbsp $rs2, (${rs1})", (QK_C_SBSP GPRC:$rs2, SPMem:$rs1, 0)>; 173def : InstAlias<"qk.c.lhusp $rd, (${rs1})", (QK_C_LHUSP GPRC:$rd, SPMem:$rs1, 0)>; 174def : InstAlias<"qk.c.shsp $rs2, (${rs1})", (QK_C_SHSP GPRC:$rs2, SPMem:$rs1, 0)>; 175} 176} 177 178//===----------------------------------------------------------------------===/ 179// Compress Instruction tablegen backend. 180//===----------------------------------------------------------------------===// 181 182let Predicates = [HasVendorXwchc] in { 183def : CompressPat<(LBU GPRC:$rd, GPRCMem:$rs1, uimm5_with_predicate:$imm), 184 (QK_C_LBU GPRC:$rd, GPRCMem:$rs1, uimm5_with_predicate:$imm)>; 185def : CompressPat<(SB GPRC:$rs2, GPRCMem:$rs1, uimm5_with_predicate:$imm), 186 (QK_C_SB GPRC:$rs2, GPRCMem:$rs1, uimm5_with_predicate:$imm)>; 187def : CompressPat<(LHU GPRC:$rd, GPRCMem:$rs1, uimm6_lsb0:$imm), 188 (QK_C_LHU GPRC:$rd, GPRCMem:$rs1, uimm6_lsb0:$imm)>; 189def : CompressPat<(SH GPRC:$rs2, GPRCMem:$rs1, uimm6_lsb0:$imm), 190 (QK_C_SH GPRC:$rs2, GPRCMem:$rs1, uimm6_lsb0:$imm)>; 191def : CompressPat<(LBU GPRC:$rd, SPMem:$rs1, uimm4_with_predicate:$imm), 192 (QK_C_LBUSP GPRC:$rd, SPMem:$rs1, uimm4_with_predicate:$imm)>; 193def : CompressPat<(SB GPRC:$rs2, SPMem:$rs1, uimm4_with_predicate:$imm), 194 (QK_C_SBSP GPRC:$rs2, SPMem:$rs1, uimm4_with_predicate:$imm)>; 195def : CompressPat<(LHU GPRC:$rd, SPMem:$rs1, uimm5_lsb0:$imm), 196 (QK_C_LHUSP GPRC:$rd, SPMem:$rs1, uimm5_lsb0:$imm)>; 197def : CompressPat<(SH GPRC:$rs2, SPMem:$rs1, uimm5_lsb0:$imm), 198 (QK_C_SHSP GPRC:$rs2, SPMem:$rs1, uimm5_lsb0:$imm)>; 199} 200