Lines Matching +full:5 +full:b00
17 bits<5> is3;
18 bits<5> is2;
43 def CV_EXTRACT : CVBitManipRII<0b00, 0b000, "cv.extract">;
46 def CV_BCLR : CVBitManipRII<0b00, 0b001, "cv.bclr">;
83 bits<5> imm5;
107 def CV_MACSN : CVInstMacN<0b00, 0b110, "cv.macsn">,
117 def CV_MACUN : CVInstMacN<0b00, 0b111, "cv.macun">,
129 def CV_MULSN : CVInstMulN<0b00, 0b100, "cv.mulsn">,
139 def CV_MULUN : CVInstMulN<0b00, 0b101, "cv.mulun">,
169 bits<5> imm5;
187 bits<5> imm5;
236 def CV_ADDN : CVInstAluRRI<0b00, 0b010, "cv.addn">,
244 def CV_SUBN : CVInstAluRRI<0b00, 0b011, "cv.subn">,
280 class CVInstSIMDRR<bits<5> funct5, bit F, bit funct1, bits<3> funct3,
290 class CVInstSIMDRI<bits<5> funct5, bit F, bits<3> funct3, RISCVOpcode opcode,
298 let Inst{24-20} = imm6{5-1};
302 class CVSIMDRR<bits<5> funct5, bit F, bit funct1, bits<3> funct3,
307 class CVSIMDRRWb<bits<5> funct5, bit F, bit funct1, bits<3> funct3,
314 class CVSIMDRI<bits<5> funct5, bit F, bits<3> funct3, string opcodestr>
318 class CVSIMDRIWb<bits<5> funct5, bit F, bits<3> funct3, string opcodestr>
325 class CVSIMDRU<bits<5> funct5, bit F, bits<3> funct3, string opcodestr,
331 class CVSIMDRUWb<bits<5> funct5, bit F, bits<3> funct3, string opcodestr>
339 class CVSIMDR<bits<5> funct5, bit F, bit funct1, bits<3> funct3,
346 multiclass CVSIMDBinarySigned<bits<5> funct5, bit F, bit funct1, string mnemonic> {
355 multiclass CVSIMDBinaryUnsigned<bits<5> funct5, bit F, bit funct1, string mnemonic> {
364 multiclass CVSIMDShift<bits<5> funct5, bit F, bit funct1, string mnemonic> {
373 multiclass CVSIMDBinarySignedWb<bits<5> funct5, bit F, bit funct1, string mnemonic> {
382 multiclass CVSIMDBinaryUnsignedWb<bits<5> funct5, bit F, bit funct1, string mnemonic> {
493 bits<5> imm5;
541 bits<5> rd;
546 let Inst{19-15} = cvrr{9-5};
590 bits<5> rs3;
591 bits<5> rs2;
592 bits<5> rs1;
607 bits<5> rs2;
612 let Inst{19-15} = cvrr{9-5};
706 def cv_tuimm5 : TImmLeaf<XLenVT, [{return isUInt<5>(Imm);}]>;
715 return CurDAG->getTargetConstant(N->getZExtValue() >> 5, SDLoc(N),