Lines Matching +full:5 +full:b00

20 class F2_XYZ<bits<5> datatype, bits<6> sop, string opcodestr, dag outs, dag ins,
23   bits<5> vry;
24   bits<5> vrx;
25   bits<5> vrz;
30   let Inst{10-5} = sop;
56 class F2_XZ<bits<5> datatype, RegisterOperand regtype, bits<6> sop, string op, SDNode opnode>
61 class F2_XZ_SET<bits<5> datatype, RegisterOperand regtype, bits<6> sop, string op>
66 class F2_XZ_P<bits<5> datatype, bits<6> sop, string op, list<dag> pattern = [],
71 multiclass F2_XZ_RM<bits<5> datatype, bits<4> sop, string op, dag outs, dag ins> {
72   def _RN  : F2_XZ_P<datatype, {sop, 0b00}, op#".rn", [], outs, ins>;
92 class F2_CXY<bits<5> datatype, RegisterOperand regtype, bits<6> sop, string op>
105 class F2_CX<bits<5> datatype, RegisterOperand regtype, bits<6> sop, string op>
121   bits<5> rx;
122   bits<5> vrz;
135     : F2_LDST<0b00, sop, op#".32", outs, ins>;
143   bits<5> rx;
150   let Inst{7-5} = sop2;
151   let Inst{4-0} = regs{9-5};
155     : F2_LDSTM<0b00, sop, sop2, op#".32", outs, ins>;
163   bits<5> rx;
164   bits<5> ry;
165   bits<5> rz;
174   let Inst{6-5} = imm;
179     : F2_LDSTR<0b00, sop, op#".32", outs, ins>;
183 class F2_CXYZ<bits<5> datatype, RegisterOperand regtype, bits<6> sop, string op>
197   bits<5> rx;
198   bits<5> vrz;