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/linux/drivers/staging/sm750fb/
H A Dddk750_reg.h1 /* SPDX-License-Identifier: GPL-2.0 */
7 #define DE_STATE1_DE_ABORT BIT(0)
10 #define DE_STATE2_DE_FIFO_EMPTY BIT(3)
11 #define DE_STATE2_DE_STATUS_BUSY BIT(2)
12 #define DE_STATE2_DE_MEM_FIFO_EMPTY BIT(1)
20 #define SYSTEM_CTRL_PCI_BURST BIT(29)
21 #define SYSTEM_CTRL_PCI_MASTER BIT(25)
22 #define SYSTEM_CTRL_LATENCY_TIMER_OFF BIT(24)
23 #define SYSTEM_CTRL_DE_FIFO_EMPTY BIT(23)
24 #define SYSTEM_CTRL_DE_STATUS_BUSY BIT(22)
[all …]
H A Dsm750_accel.h1 /* SPDX-License-Identifier: GPL-2.0 */
25 #define DE_SOURCE_WRAP BIT(31)
26 #define DE_SOURCE_X_K1_SHIFT 16
27 #define DE_SOURCE_X_K1_MASK (0x3fff << 16)
28 #define DE_SOURCE_X_K1_MONO_MASK (0x1f << 16)
32 #define DE_DESTINATION_WRAP BIT(31)
33 #define DE_DESTINATION_X_SHIFT 16
34 #define DE_DESTINATION_X_MASK (0x1fff << 16)
38 #define DE_DIMENSION_X_SHIFT 16
39 #define DE_DIMENSION_X_MASK (0x1fff << 16)
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/linux/drivers/mtd/nand/raw/
H A Dnand_ids.c1 // SPDX-License-Identifier: GPL-2.0-only
29 {"TC58NVG0S3E 1G 3.3V 8-bit",
32 {"TC58NVG2S0F 4G 3.3V 8-bit",
35 {"TC58NVG2S0H 4G 3.3V 8-bit",
38 {"TC58NVG3S0F 8G 3.3V 8-bit",
41 {"TC58NVG5D2 32G 3.3V 8-bit",
44 {"TC58NVG6D2 64G 3.3V 8-bit",
47 {"SDTNQGAMA 64G 3.3V 8-bit",
50 {"SDTNRGAMA 64G 3.3V 8-bit",
53 {"H27UCG8T2ATR-BC 64G 3.3V 8-bit",
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/linux/drivers/media/platform/ti/omap3isp/
H A Dispreg.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * TI OMAP3 ISP - Registers definitions
48 #define ISPCCP2_SYSCONFIG_SOFT_RESET BIT(1)
58 #define ISPCCP2_SYSSTATUS_RESET_DONE BIT(0)
61 #define ISPCCP2_LC01_IRQSTATUS_LC0_FS_IRQ BIT(11)
62 #define ISPCCP2_LC01_IRQSTATUS_LC0_LE_IRQ BIT(10)
63 #define ISPCCP2_LC01_IRQSTATUS_LC0_LS_IRQ BIT(9)
64 #define ISPCCP2_LC01_IRQSTATUS_LC0_FE_IRQ BIT(8)
65 #define ISPCCP2_LC01_IRQSTATUS_LC0_COUNT_IRQ BIT(7)
66 #define ISPCCP2_LC01_IRQSTATUS_LC0_FIFO_OVF_IRQ BIT(5)
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/linux/drivers/net/ethernet/mediatek/
H A Dmtk_wed_regs.h1 // SPDX-License-Identifier: GPL-2.0-only
7 #define MTK_WFDMA_DESC_CTRL_TO_HOST BIT(8)
10 #define MTK_WDMA_DESC_CTRL_LAST_SEG1 BIT(15)
11 #define MTK_WDMA_DESC_CTRL_BURST BIT(16)
12 #define MTK_WDMA_DESC_CTRL_LEN0 GENMASK(29, 16)
13 #define MTK_WDMA_DESC_CTRL_LAST_SEG0 BIT(30)
14 #define MTK_WDMA_DESC_CTRL_DMA_DONE BIT(31)
16 #define MTK_WDMA_TXD0_DESC_INFO_DMA_DONE BIT(29)
17 #define MTK_WDMA_TXD1_DESC_INFO_DMA_DONE BIT(31)
29 #define MTK_WED_RESET_TX_BM BIT(0)
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H A Dmtk_ppe_regs.h1 // SPDX-License-Identifier: GPL-2.0-only
8 #define MTK_PPE_GLO_CFG_EN BIT(0)
9 #define MTK_PPE_GLO_CFG_TSID_EN BIT(1)
10 #define MTK_PPE_GLO_CFG_IP4_L4_CS_DROP BIT(2)
11 #define MTK_PPE_GLO_CFG_IP4_CS_DROP BIT(3)
12 #define MTK_PPE_GLO_CFG_TTL0_DROP BIT(4)
13 #define MTK_PPE_GLO_CFG_PPE_BSWAP BIT(5)
14 #define MTK_PPE_GLO_CFG_PSE_HASH_OFS BIT(6)
15 #define MTK_PPE_GLO_CFG_MCAST_TB_EN BIT(7)
16 #define MTK_PPE_GLO_CFG_FLOW_DROP_KA BIT(8)
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/linux/drivers/staging/media/sunxi/sun6i-isp/
H A Dsun6i_isp_reg.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2021-2022 Bootlin
20 #define SUN6I_ISP_FE_CFG_EN BIT(0)
22 #define SUN6I_ISP_FE_CFG_SRC1_MODE(v) (((v) << 16) & GENMASK(17, 16))
25 #define SUN6I_ISP_FE_CTRL_SCAP_EN BIT(0)
26 #define SUN6I_ISP_FE_CTRL_VCAP_EN BIT(1)
27 #define SUN6I_ISP_FE_CTRL_PARA_READY BIT(2)
28 #define SUN6I_ISP_FE_CTRL_LUT_UPDATE BIT(3)
29 #define SUN6I_ISP_FE_CTRL_LENS_UPDATE BIT(4)
30 #define SUN6I_ISP_FE_CTRL_GAMMA_UPDATE BIT(5)
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/linux/include/soc/mscc/
H A Docelot_dev.h1 /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
11 #define DEV_CLOCK_CFG_MAC_TX_RST BIT(7)
12 #define DEV_CLOCK_CFG_MAC_RX_RST BIT(6)
13 #define DEV_CLOCK_CFG_PCS_TX_RST BIT(5)
14 #define DEV_CLOCK_CFG_PCS_RX_RST BIT(4)
15 #define DEV_CLOCK_CFG_PORT_RST BIT(3)
16 #define DEV_CLOCK_CFG_PHY_RST BIT(2)
20 #define DEV_PORT_MISC_FWD_ERROR_ENA BIT(4)
21 #define DEV_PORT_MISC_FWD_PAUSE_ENA BIT(3)
22 #define DEV_PORT_MISC_FWD_CTRL_ENA BIT(2)
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H A Docelot_hsio.h1 /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
85 #define HSIO_PLL5G_CFG0_ENA_ROT BIT(31)
86 #define HSIO_PLL5G_CFG0_ENA_LANE BIT(30)
87 #define HSIO_PLL5G_CFG0_ENA_CLKTREE BIT(29)
88 #define HSIO_PLL5G_CFG0_DIV4 BIT(28)
89 #define HSIO_PLL5G_CFG0_ENA_LOCK_FINE BIT(27)
96 #define HSIO_PLL5G_CFG0_SELCPI(x) (((x) << 16) & GENMASK(17, 16))
97 #define HSIO_PLL5G_CFG0_SELCPI_M GENMASK(17, 16)
98 #define HSIO_PLL5G_CFG0_SELCPI_X(x) (((x) & GENMASK(17, 16)) >> 16)
99 #define HSIO_PLL5G_CFG0_ENA_VCO_CONTRH BIT(15)
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/linux/drivers/gpu/drm/mxsfb/
H A Dlcdif_regs.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
39 #define CTRL_SFTRST BIT(31)
40 #define CTRL_CLKGATE BIT(30)
41 #define CTRL_BYPASS_COUNT BIT(19)
42 #define CTRL_VSYNC_MODE BIT(18)
43 #define CTRL_DOTCLK_MODE BIT(17)
44 #define CTRL_DATA_SELECT BIT(16)
54 #define CTRL_MASTER BIT(5)
55 #define CTRL_DF16 BIT(3)
56 #define CTRL_DF18 BIT(2)
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/linux/drivers/net/wireless/mediatek/mt76/
H A Dmt76_connac2_mac.h1 /* SPDX-License-Identifier: ISC */
45 #define MT_TX_FREE_MSDU_ID GENMASK(30, 16)
46 #define MT_TX_FREE_PAIR BIT(31)
52 #define MT_TXD0_ETH_TYPE_OFFSET GENMASK(22, 16)
55 #define MT_TXD1_LONG_FORMAT BIT(31)
56 #define MT_TXD1_TGID BIT(30)
58 #define MT_TXD1_AMSDU BIT(23)
61 #define MT_TXD1_HDR_FORMAT GENMASK(17, 16)
63 #define MT_TXD1_ETH_802_3 BIT(15)
64 #define MT_TXD1_VTA BIT(10)
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/linux/drivers/net/ethernet/airoha/
H A Dairoha_regs.h1 /* SPDX-License-Identifier: GPL-2.0-only */
33 #define FE_DMA_GLO_PG_SZ_MASK BIT(3)
36 #define FE_RST_GDM4_MBI_ARB_MASK BIT(3)
37 #define FE_RST_GDM3_MBI_ARB_MASK BIT(2)
38 #define FE_RST_CORE_MASK BIT(0)
43 #define WAN1_EN_MASK BIT(16)
59 #define PCE_DPI_EN_MASK BIT(2)
60 #define PCE_KA_EN_MASK BIT(1)
61 #define PCE_MC_EN_MASK BIT(0)
65 #define PSE_CFG_QUEUE_ID_MASK GENMASK(20, 16)
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/linux/drivers/clk/stm32/
H A Dstm32mp13_rcc.h1 /* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */
3 * Copyright (C) 2020, STMicroelectronics - All Rights Reserved
225 #define RCC_SECCFGR_APB3DIVSEC 16
238 #define RCC_MP_SREQSETR_STPREQ_P0 BIT(0)
241 #define RCC_MP_SREQCLRR_STPREQ_P0 BIT(0)
244 #define RCC_MP_APRSTCR_RDCTLEN BIT(0)
257 #define RCC_MP_GRSTCSETR_MPSYSRST BIT(0)
258 #define RCC_MP_GRSTCSETR_MPUP0RST BIT(4)
261 #define RCC_BR_RSTSCLRR_PORRSTF BIT(0)
262 #define RCC_BR_RSTSCLRR_BORRSTF BIT(1)
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/linux/drivers/net/ethernet/marvell/
H A Dskge.h1 /* SPDX-License-Identifier: GPL-2.0 */
131 /* B0_CTST 16 bit Control/Status register */
133 CS_CLK_RUN_HOT = 1<<13,/* CLK_RUN hot m. (YUKON-Lite only) */
134 CS_CLK_RUN_RST = 1<<12,/* CLK_RUN reset (YUKON-Lite only) */
135 CS_CLK_RUN_ENA = 1<<11,/* CLK_RUN enable (YUKON-Lite only) */
138 CS_BUS_SLOT_SZ = 1<<8, /* Slot Size 0/1 = 32/64 bit slot */
142 CS_STOP_MAST = 1<<4, /* Command Bit to stop the master */
148 /* B0_LED 8 Bit LED register */
149 /* Bit 7.. 2: reserved */
153 /* B0_POWER_CTRL 8 Bit Power Control reg (YUKON only) */
[all …]
/linux/drivers/media/platform/nxp/imx8-isi/
H A Dimx8-isi-regs.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright 2019-2020 NXP
14 #define CHNL_CTRL_CHNL_EN BIT(31)
15 #define CHNL_CTRL_CLK_EN BIT(30)
16 #define CHNL_CTRL_CHNL_BYPASS BIT(29)
21 #define CHNL_CTRL_SW_RST BIT(24)
22 #define CHNL_CTRL_BLANK_PXL(n) ((n) << 16)
23 #define CHNL_CTRL_BLANK_PXL_MASK GENMASK(23, 16)
27 #define CHNL_CTRL_SRC_TYPE_MASK BIT(4)
86 #define CHNL_IMG_CTRL_GBL_ALPHA_VAL(n) ((n) << 16)
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/linux/drivers/net/wireless/mediatek/mt76/mt7603/
H A Dregs.h1 /* SPDX-License-Identifier: ISC */
28 #define MT_INT_RX_DONE(_n) BIT(_n)
31 #define MT_INT_TX_DONE(_n) BIT((_n) + 4)
33 #define MT_INT_RX_COHERENT BIT(20)
34 #define MT_INT_TX_COHERENT BIT(21)
35 #define MT_INT_MAC_IRQ3 BIT(27)
37 #define MT_INT_MCU_CMD BIT(30)
40 #define MT_WPDMA_GLO_CFG_TX_DMA_EN BIT(0)
41 #define MT_WPDMA_GLO_CFG_TX_DMA_BUSY BIT(1)
42 #define MT_WPDMA_GLO_CFG_RX_DMA_EN BIT(2)
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H A Dmac.h1 /* SPDX-License-Identifier: ISC */
9 #define MT_RXD0_NORMAL_ETH_TYPE_OFS GENMASK(22, 16)
10 #define MT_RXD0_NORMAL_IP_SUM BIT(23)
11 #define MT_RXD0_NORMAL_UDP_TCP_SUM BIT(24)
12 #define MT_RXD0_NORMAL_GROUP_1 BIT(25)
13 #define MT_RXD0_NORMAL_GROUP_2 BIT(26)
14 #define MT_RXD0_NORMAL_GROUP_3 BIT(27)
15 #define MT_RXD0_NORMAL_GROUP_4 BIT(28)
29 #define MT_RXD1_NORMAL_HDR_TRANS BIT(23)
30 #define MT_RXD1_NORMAL_HDR_OFFSET BIT(22)
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/linux/drivers/net/wireless/mediatek/mt76/mt7615/
H A Dmac.h1 /* SPDX-License-Identifier: ISC */
11 #define MT_RXD0_PKT_FLAG GENMASK(19, 16)
14 #define MT_RXD0_NORMAL_ETH_TYPE_OFS GENMASK(22, 16)
15 #define MT_RXD0_NORMAL_IP_SUM BIT(23)
16 #define MT_RXD0_NORMAL_UDP_TCP_SUM BIT(24)
17 #define MT_RXD0_NORMAL_GROUP_1 BIT(25)
18 #define MT_RXD0_NORMAL_GROUP_2 BIT(26)
19 #define MT_RXD0_NORMAL_GROUP_3 BIT(27)
20 #define MT_RXD0_NORMAL_GROUP_4 BIT(28)
25 #define MT_RXD1_MID_AMSDU_FRAME BIT(1)
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/linux/drivers/gpu/drm/vc4/
H A Dvc4_regs.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright © 2014-2015 Broadcom
24 WARN_ON(!FIELD_FIT(hvs->vc4->gen == VC4_GEN_6_C ? \
27 FIELD_PREP(hvs->vc4->gen == VC4_GEN_6_C ? \
32 #define VC6_GET_FIELD(word, field) FIELD_GET(hvs->vc4->gen == VC4_GEN_6_C ? \
41 ('D' << 16))
47 # define V3D_IDENT1_NSEM_MASK VC4_MASK(23, 16)
48 # define V3D_IDENT1_NSEM_SHIFT 16
61 # define V3D_L2CACTL_L2CCLR BIT(2)
62 # define V3D_L2CACTL_L2CDIS BIT(1)
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/linux/drivers/crypto/intel/qat/qat_common/
H A Dicp_qat_hw.h1 /* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0-only) */
2 /* Copyright(c) 2014 - 2020 Intel Corporation */
25 ICP_QAT_HW_AE_16 = 16,
56 ICP_QAT_HW_AUTH_RESERVED_2 = 16,
81 ICP_ACCEL_MASK_CIPHER_SLICE = BIT(0),
82 ICP_ACCEL_MASK_AUTH_SLICE = BIT(1),
83 ICP_ACCEL_MASK_PKE_SLICE = BIT(2),
84 ICP_ACCEL_MASK_COMPRESS_SLICE = BIT(3),
85 ICP_ACCEL_MASK_LZS_SLICE = BIT(4),
86 ICP_ACCEL_MASK_EIA3_SLICE = BIT(5),
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/linux/drivers/infiniband/hw/ocrdma/
H A Docrdma_sli.h3 * Copyright (C) 2012-2015 Emulex. All rights reserved.
16 * - Redistributions of source code must retain the above copyright notice,
19 * - Redistributions in binary form must reproduce the above copyright
36 * linux-drivers@emulex.com
77 OCRDMA_CMD_QUERY_NSMR = 16,
122 #define OCRDMA_MAX_SGID 16
139 OCRDMA_DB_SQ_SHIFT = 16,
149 #define OCRDMA_DB_CQ_RING_ID_MASK 0x3FF /* bits 0 - 9 */
150 #define OCRDMA_DB_CQ_RING_ID_EXT_MASK 0x0C00 /* bits 10-11 of qid at 12-11 */
151 /* qid #2 msbits at 12-11 */
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/linux/drivers/memory/tegra/
H A Dtegra30.c1 // SPDX-License-Identifier: GPL-2.0-only
10 #include <dt-bindings/memory/tegra30-mc.h>
48 .fifo_size = 16 * 2,
56 .bit = 1,
65 .fifo_size = 16 * 128,
73 .bit = 2,
82 .fifo_size = 16 * 128,
90 .bit = 3,
94 .shift = 16,
99 .fifo_size = 16 * 64,
[all …]
/linux/drivers/gpu/drm/arm/display/komeda/d71/
H A Dd71_regs.h1 /* SPDX-License-Identifier: GPL-2.0 */
46 #define BLK_CTRL_EN BIT(0)
48 #define HV_SIZE(h, v) (((h) & 0x1FFF) + (((v) & 0x1FFF) << 16))
49 #define HV_OFFSET(h, v) (((h) & 0xFFF) + (((v) & 0xFFF) << 16))
50 #define HV_CROP(h, v) (((h) & 0xFFF) + (((v) & 0xFFF) << 16))
56 #define AD_AEN BIT(0)
57 #define AD_YT BIT(1)
58 #define AD_BS BIT(2)
59 #define AD_WB BIT(3)
60 #define AD_TH BIT(4)
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/linux/drivers/staging/media/starfive/camss/
H A Dstf-isp.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 * StarFive Camera Subsystem - ISP Module
7 * Copyright (C) 2021-2023 StarFive Technology Co., Ltd.
13 #include <media/v4l2-subdev.h>
15 #include "stf-video.h"
24 #define CSI_SCD_ERR BIT(6)
25 #define CSI_ITU656_ERR BIT(4)
26 #define CSI_ITU656_F BIT(3)
27 #define CSI_SCD_DONE BIT(2)
28 #define CSI_BUSY_S BIT(1)
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/linux/drivers/media/platform/sunxi/sun6i-csi/
H A Dsun6i_csi_reg.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (c) 2011-2018 Magewell Electronics Co., Ltd. (Nanjing)
5 * Copyright 2021-2022 Bootlin
17 #define SUN6I_CSI_EN_VER_EN BIT(30)
18 #define SUN6I_CSI_EN_PTN_CYCLE(v) (((v) << 16) & GENMASK(23, 16))
19 #define SUN6I_CSI_EN_SRAM_PWDN BIT(8)
20 #define SUN6I_CSI_EN_PTN_START BIT(4)
21 #define SUN6I_CSI_EN_CLK_CNT_SPL_VSYNC BIT(3)
22 #define SUN6I_CSI_EN_CLK_CNT_EN BIT(2)
23 #define SUN6I_CSI_EN_PTN_GEN_EN BIT(1)
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