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/freebsd/contrib/llvm-project/clang/include/clang/Basic/
H A DMSP430Target.def1 //===--- MSP430Target.def - MSP430 Feature/Processor Database----*- C++ -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
12 // Target/MSP430/gen-msp430-def.py - use this tool rather than adding
15 //===----------------------------------------------------------------------===//
203 // With 16-bit hardware multiplier
204 MSP430_MCU_FEAT("msp430c336", "16bit")
205 MSP430_MCU_FEAT("msp430c337", "16bit")
206 MSP430_MCU_FEAT("msp430cg4616", "16bit")
207 MSP430_MCU_FEAT("msp430cg4617", "16bit")
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/freebsd/contrib/llvm-project/llvm/lib/Target/AVR/MCTargetDesc/
H A DAVRFixupKinds.h1 //===-- AVRFixupKinds.h - AVR Specific Fixup Entries -------
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/freebsd/contrib/llvm-project/clang/lib/Headers/
H A Davxvnniint16intrin.h1 /*===----------- avxvnniint16intrin.h - AVXVNNIINT16 intrinsics-------------===
5 * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 *===-----------------------------------------------------------------------===
26 /// Multiply groups of 2 adjacent pairs of signed 16-bit integers in \a __A with
27 /// corresponding unsigned 16-bit integers in \a __B, producing 2 intermediate
28 /// signed 16-bit results. Sum these 2 results with the corresponding
29 /// 32-bit integer in \a __W, and store the packed 32-bit results in \a dst.
40 /// A 128-bit vector of [4 x int].
42 /// A 128-bit vector of [8 x short].
44 /// A 128-bit vector of [8 x unsigned short].
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H A Davxneconvertintrin.h1 /*===-------------- avxneconvertintrin.h - AVXNECONVERT --------------------===
5 * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 *===-----------------------------------------------------------------------===
28 /// Convert scalar BF16 (16-bit) floating-point element
30 /// single-precision (32-bit) floating-point, broadcast it to packed
31 /// single-precision (32-bit) floating-point elements, and store the results in
43 /// A pointer to a 16-bit memory location. The address of the memory
46 /// A 128-bit vector of [4 x float].
61 /// Convert scalar BF16 (16-bit) floating-point element
63 /// single-precision (32-bit) floating-point, broadcast it to packed
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H A Df16cintrin.h1 /*===---- f16cintrin.h - F16C intrinsics -----------------------------------===
5 * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 *===-----------------------------------------------------------------------===
23 /* NOTE: Intel documents the 128-bit versions of these as being in emmintrin.h,
28 /// Converts a 16-bit half-precision float value into a 32-bit float
36 /// A 16-bit half-precision float value.
37 /// \returns The converted 32-bit float value.
46 /// Converts a 32-bit single-precision float value to a 16-bit
47 /// half-precision float value.
58 /// A 32-bit single-precision float value to be converted to a 16-bit
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H A Dmmintrin.h1 /*===---- mmintrin.h - MMX intrinsics --------------------------------------===
5 * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 *===-----------------------------------------------------------------------===
26 __attribute__((__always_inline__, __nodebug__, __target__("mmx,no-evex512"), \
37 __target__("mmx,no-evex512")))
42 /// Constructs a 64-bit integer vector, setting the lower 32 bits to the
43 /// value of the 32-bit integer parameter and setting the upper 32 bits to 0.
50 /// A 32-bit integer value.
51 /// \returns A 64-bit integer vector. The lower 32 bits contain the value of the
59 /// Returns the lower 32 bits of a 64-bit integer vector as a 32-bit
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/freebsd/sys/contrib/dev/rtw89/
H A Dtxrx.h1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
28 if (rtwdev->chip->chip_gen == RTW89_CHIP_BE) in rtw89_get_data_rate_mode()
41 if (rtwdev->chip->chip_gen == RTW89_CHIP_BE) in rtw89_get_data_ht_mcs()
49 if (rtwdev->chip->chip_gen == RTW89_CHIP_BE) in rtw89_get_data_mcs()
62 if (rtwdev->chip->chip_gen == RTW89_CHIP_BE) in rtw89_get_data_nss()
71 #define RTW89_TXWD_BODY0_MORE_DATA BIT(23)
72 #define RTW89_TXWD_BODY0_WD_INFO_EN BIT(22)
73 #define RTW89_TXWD_BODY0_FW_DL BIT(20)
74 #define RTW89_TXWD_BODY0_CHANNEL_DMA GENMASK(19, 16)
76 #define RTW89_TXWD_BODY0_STF_MODE BIT(10)
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/illumos-gate/usr/src/uts/common/sys/fibre-channel/fca/qlc/
H A Dql_init.h37 * * COPYRIGHT (C) 1996-2015 QLOGIC CORPORATION **
69 * LSB BIT 0 = enable_hard_loop_id
70 * LSB BIT 1 = enable_fairness
71 * LSB BIT 2 = enable_full_duplex
72 * LSB BIT 3 = enable_fast_posting
73 * LSB BIT 4 = enable_target_mode
74 * LSB BIT 5 = disable_initiator_mode
75 * LSB BIT 6 = enable_adisc
76 * LSB BIT 7 = enable_target_inquiry_data
78 * MSB BIT 0 = enable_port_update_ae
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/freebsd/sys/contrib/dev/mediatek/mt76/
H A Dmt76_connac2_mac.h1 /* SPDX-License-Identifier: ISC */
45 #define MT_TX_FREE_MSDU_ID GENMASK(30, 16)
46 #define MT_TX_FREE_PAIR BIT(31)
52 #define MT_TXD0_ETH_TYPE_OFFSET GENMASK(22, 16)
55 #define MT_TXD1_LONG_FORMAT BIT(31)
56 #define MT_TXD1_TGID BIT(30)
58 #define MT_TXD1_AMSDU BIT(23)
61 #define MT_TXD1_HDR_FORMAT GENMASK(17, 16)
63 #define MT_TXD1_ETH_802_3 BIT(15)
64 #define MT_TXD1_VTA BIT(10)
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H A Dmt76_connac3_mac.h1 /* SPDX-License-Identifier: ISC */
25 #define MT_RXD0_PKT_FLAG GENMASK(19, 16)
28 #define MT_RXD0_MESH BIT(18)
29 #define MT_RXD0_MHCP BIT(19)
30 #define MT_RXD0_NORMAL_ETH_TYPE_OFS GENMASK(22, 16)
32 #define MT_RXD0_SW_PKT_TYPE_MASK GENMASK(31, 16)
38 #define MT_RXD1_NORMAL_GROUP_1 BIT(16)
39 #define MT_RXD1_NORMAL_GROUP_2 BIT(17)
40 #define MT_RXD1_NORMAL_GROUP_3 BIT(18)
41 #define MT_RXD1_NORMAL_GROUP_4 BIT(19)
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H A Dmt76x02_regs.h1 /* SPDX-License-Identifier: ISC */
15 #define MT_CMB_CTRL_XTAL_RDY BIT(22)
16 #define MT_CMB_CTRL_PLL_LD BIT(23)
23 #define MT_EFUSE_CTRL_AIN GENMASK(25, 16)
24 #define MT_EFUSE_CTRL_KICK BIT(30)
25 #define MT_EFUSE_CTRL_SEL BIT(31)
31 #define MT_COEXCFG0_COEX_EN BIT(0)
34 #define MT_WLAN_FUN_CTRL_WLAN_EN BIT(0)
35 #define MT_WLAN_FUN_CTRL_WLAN_CLK_EN BIT(1)
36 #define MT_WLAN_FUN_CTRL_WLAN_RESET_RF BIT(2)
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/freebsd/sys/contrib/dev/mediatek/mt76/mt7603/
H A Dregs.h1 /* SPDX-License-Identifier: ISC */
28 #define MT_INT_RX_DONE(_n) BIT(_n)
31 #define MT_INT_TX_DONE(_n) BIT((_n) + 4)
33 #define MT_INT_RX_COHERENT BIT(20)
34 #define MT_INT_TX_COHERENT BIT(21)
35 #define MT_INT_MAC_IRQ3 BIT(27)
37 #define MT_INT_MCU_CMD BIT(30)
40 #define MT_WPDMA_GLO_CFG_TX_DMA_EN BIT(0)
41 #define MT_WPDMA_GLO_CFG_TX_DMA_BUSY BIT(1)
42 #define MT_WPDMA_GLO_CFG_RX_DMA_EN BIT(2)
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H A Dmac.h1 /* SPDX-License-Identifier: ISC */
9 #define MT_RXD0_NORMAL_ETH_TYPE_OFS GENMASK(22, 16)
10 #define MT_RXD0_NORMAL_IP_SUM BIT(23)
11 #define MT_RXD0_NORMAL_UDP_TCP_SUM BIT(24)
12 #define MT_RXD0_NORMAL_GROUP_1 BIT(25)
13 #define MT_RXD0_NORMAL_GROUP_2 BIT(26)
14 #define MT_RXD0_NORMAL_GROUP_3 BIT(27)
15 #define MT_RXD0_NORMAL_GROUP_4 BIT(28)
29 #define MT_RXD1_NORMAL_HDR_TRANS BIT(23)
30 #define MT_RXD1_NORMAL_HDR_OFFSET BIT(22)
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/illumos-gate/usr/src/uts/common/io/yge/
H A Dyge.h12 * are provided to you under the BSD-type license terms provided
17 * - Redistributions of source code must retain the above copyright
19 * - Redistributions in binary form must reproduce the above
23 * - Neither the name of Marvell nor the names of its contributors
57 * D-Link PCI vendor ID
91 * D-Link gigabit ethernet device ID
97 #define BIT(n) (1U << n) macro
102 #define PCI_BASE_1ST 0x10 /* 32 bit 1st Base address */
103 #define PCI_BASE_2ND 0x14 /* 32 bit 2nd Base address */
104 #define PCI_OUR_REG_1 0x40 /* 32 bit Our Register 1 */
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/freebsd/sys/contrib/dev/mediatek/mt76/mt7615/
H A Dmac.h1 /* SPDX-License-Identifier: ISC */
11 #define MT_RXD0_PKT_FLAG GENMASK(19, 16)
14 #define MT_RXD0_NORMAL_ETH_TYPE_OFS GENMASK(22, 16)
15 #define MT_RXD0_NORMAL_IP_SUM BIT(23)
16 #define MT_RXD0_NORMAL_UDP_TCP_SUM BIT(24)
17 #define MT_RXD0_NORMAL_GROUP_1 BIT(25)
18 #define MT_RXD0_NORMAL_GROUP_2 BIT(26)
19 #define MT_RXD0_NORMAL_GROUP_3 BIT(27)
20 #define MT_RXD0_NORMAL_GROUP_4 BIT(28)
25 #define MT_RXD1_MID_AMSDU_FRAME BIT(1)
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H A Dregs.h1 /* SPDX-License-Identifier: ISC */
35 #define MT_HW_INFO_BASE ((dev)->reg_map[MT_HW_BASE])
40 #define MT_TOP_3NSS BIT(24)
43 #define MT_TOP_OFF_RSV_FW_STATE GENMASK(18, 16)
45 #define MT_TOP_MISC2 ((dev)->reg_map[MT_TOP_CFG_BASE] + 0x134)
49 #define MT_TOP_MISC2_FW_PWR_ON BIT(1)
59 #define MT_MCU_PCIE_REMAP_2 ((dev)->reg_map[MT_PCIE_REMAP_2])
62 #define MT_PCIE_REMAP_BASE_2 ((dev)->reg_map[MT_PCIE_REMAP_BASE2])
69 #define MT_HIF(ofs) ((dev)->reg_map[MT_HIF_BASE] + (ofs))
71 #define MT_HIF_LOGIC_RST_N BIT(4)
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/illumos-gate/usr/src/uts/common/io/sdcard/adapters/sdhost/
H A Dsdhost.h48 #define BIT(x) (1 << (x)) macro
72 * Slot-specific CSRs
75 #define REG_BLKSZ 0x0004 /* 16 bits */
76 #define REG_BLOCK_COUNT 0x0006 /* 16 bits */
78 #define REG_XFR_MODE 0x000C /* 16 bits */
79 #define REG_COMMAND 0x000E /* 16 bits */
90 #define REG_CLOCK_CONTROL 0x002C /* 16 bits */
93 #define REG_INT_STAT 0x0030 /* 16 bits */
94 #define REG_ERR_STAT 0x0032 /* 16 bits */
95 #define REG_INT_EN 0x0034 /* 16 bits */
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/freebsd/sys/dev/qat/include/
H A Dicp_qat_hw.h1 /* SPDX-License-Identifier: BSD-3-Clause */
2 /* Copyright(c) 2007-2022 Intel Corporation */
49 ICP_QAT_HW_AUTH_RESERVED_2 = 16,
83 ICP_ACCEL_CAPABILITIES_CRYPTO_SYMMETRIC = BIT(0),
84 ICP_ACCEL_CAPABILITIES_CRYPTO_ASYMMETRIC = BIT(1),
85 ICP_ACCEL_CAPABILITIES_CIPHER = BIT(2),
86 ICP_ACCEL_CAPABILITIES_AUTHENTICATION = BIT(3),
87 ICP_ACCEL_CAPABILITIES_RESERVED_1 = BIT(4),
88 ICP_ACCEL_CAPABILITIES_COMPRESSION = BIT(5),
89 ICP_ACCEL_CAPABILITIES_DEPRECATED = BIT(6),
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/illumos-gate/usr/src/uts/intel/io/amd8111s/
H A Damd8111s_hw.h10 * Copyright (c) 2001-2006 Advanced Micro Devices, Inc. All rights reserved.
40 * Import/Export/Re-Export/Use/Release/Transfer Restrictions and
43 * transfer, importation, exportation and/or re-exportation under
101 #define TX_RING_MOD_MASK (2 * TX_RING_SIZE - 1)
106 #define RX_RING_MOD_MASK (RX_RING_SIZE - 1)
130 #define MII_NWAYTEST 0x14 /* N-way auto-neg test reg */
254 #define STAT_ASF 0x00 /* 32bit register */
259 #define AP_VALUE 0x98 /* 32bit register */
260 #define AUTOPOLL0 0x88 /* 16bit register */
261 #define AUTOPOLL1 0x8A /* 16bit register */
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/freebsd/sys/dev/msk/
H A Dif_mskreg.h17 * are provided to you under the BSD-type license terms provided
22 * - Redistributions of source code must retain the above copyright
24 * - Redistributions in binary form must reproduce the above
28 * - Neither the name of Marvell nor the names of its contributors
48 /*-
49 * SPDX-License-Identifier: BSD-4-Clause AND BSD-3-Clause
65 * 4. Neither the name of the author nor the names of any co-contributors
82 /*-
110 * D-Link PCI vendor ID
154 * D-Link gigabit ethernet device ID
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/freebsd/sys/dev/sfxge/common/
H A Defx_regs_pci.h1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2007-2016 Solarflare Communications Inc.
41 * PC_VEND_ID_REG(16bit):
49 #define PCRF_AZ_VEND_ID_WIDTH 16
52 * PC_DEV_ID_REG(16bit):
60 #define PCRF_AZ_DEV_ID_WIDTH 16
63 * PC_CMD_REG(16bit):
94 * PC_STAT_REG(16bit):
125 * PC_REV_ID_REG(8bit):
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/freebsd/contrib/wpa/src/crypto/
H A Dmilenage.c2 * 3GPP AKA - Milenage algorithm (3GPP TS 35.205, .206, .207, .208)
3 * Copyright (c) 2006-2007 <j@w1.fi>
10 * EAP-AKA to be tested properly with real USIM cards.
26 * milenage_f1 - Milenage f1 and f1* algorithms
27 * @opc: OPc = 128-bit value derived from OP and K
28 * @k: K = 128-bit subscriber key
29 * @_rand: RAND = 128-bit random challenge
30 * @sqn: SQN = 48-bit sequence number
31 * @amf: AMF = 16-bit authentication management field
32 * @mac_a: Buffer for MAC-A = 64-bit network authentication code, or %NULL
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/freebsd/sys/dev/stge/
H A Dif_stgereg.h3 /*-
4 * SPDX-License-Identifier: BSD-2-Clause
46 * D-Link Systems PCI vendor ID
64 * D-Link Systems device ID
77 * Note that while DMA addresses are all in 64-bit fields, only
90 bus_write_4((_sc)->sc_res[0], (reg), (val))
92 bus_write_2((_sc)->sc_res[0], (reg), (val))
94 bus_write_1((_sc)->sc_res[0], (reg), (val))
97 bus_read_4((_sc)->sc_res[0], (reg))
99 bus_read_2((_sc)->sc_res[0], (reg))
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/illumos-gate/usr/src/uts/common/io/sfxge/common/
H A Defx_regs_pci.h2 * Copyright (c) 2007-2015 Solarflare Communications Inc.
39 * PC_VEND_ID_REG(16bit):
47 #define PCRF_AZ_VEND_ID_WIDTH 16
51 * PC_DEV_ID_REG(16bit):
59 #define PCRF_AZ_DEV_ID_WIDTH 16
63 * PC_CMD_REG(16bit):
95 * PC_STAT_REG(16bit):
127 * PC_REV_ID_REG(8bit):
139 * PC_CC_REG(24bit):
146 #define PCRF_AZ_BASE_CC_LBN 16
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/freebsd/sys/contrib/dev/rtw88/
H A Drtw8723d.h1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2 /* Copyright(c) 2018-2019 Realtek Corporation
20 le32_get_bits(*((__le32 *)(phy_stat) + 0x00), GENMASK(23, 16))

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