Lines Matching +full:16 +full:- +full:bit

1 /* SPDX-License-Identifier: BSD-3-Clause */
2 /* Copyright(c) 2007-2022 Intel Corporation */
49 	ICP_QAT_HW_AUTH_RESERVED_2 = 16,
83 	ICP_ACCEL_CAPABILITIES_CRYPTO_SYMMETRIC = BIT(0),
84 	ICP_ACCEL_CAPABILITIES_CRYPTO_ASYMMETRIC = BIT(1),
85 	ICP_ACCEL_CAPABILITIES_CIPHER = BIT(2),
86 	ICP_ACCEL_CAPABILITIES_AUTHENTICATION = BIT(3),
87 	ICP_ACCEL_CAPABILITIES_RESERVED_1 = BIT(4),
88 	ICP_ACCEL_CAPABILITIES_COMPRESSION = BIT(5),
89 	ICP_ACCEL_CAPABILITIES_DEPRECATED = BIT(6),
90 	ICP_ACCEL_CAPABILITIES_RAND = BIT(7),
91 	ICP_ACCEL_CAPABILITIES_ZUC = BIT(8),
92 	ICP_ACCEL_CAPABILITIES_SHA3 = BIT(9),
93 	ICP_ACCEL_CAPABILITIES_KPT = BIT(10),
94 	ICP_ACCEL_CAPABILITIES_RL = BIT(11),
95 	ICP_ACCEL_CAPABILITIES_HKDF = BIT(12),
96 	ICP_ACCEL_CAPABILITIES_ECEDMONT = BIT(13),
97 	ICP_ACCEL_CAPABILITIES_EXT_ALGCHAIN = BIT(14),
98 	ICP_ACCEL_CAPABILITIES_SHA3_EXT = BIT(15),
99 	ICP_ACCEL_CAPABILITIES_AESGCM_SPC = BIT(16),
100 	ICP_ACCEL_CAPABILITIES_CHACHA_POLY = BIT(17),
101 	ICP_ACCEL_CAPABILITIES_SM2 = BIT(18),
102 	ICP_ACCEL_CAPABILITIES_SM3 = BIT(19),
103 	ICP_ACCEL_CAPABILITIES_SM4 = BIT(20),
104 	ICP_ACCEL_CAPABILITIES_INLINE = BIT(21),
105 	ICP_ACCEL_CAPABILITIES_CNV_INTEGRITY = BIT(22),
106 	ICP_ACCEL_CAPABILITIES_CNV_INTEGRITY64 = BIT(23),
107 	ICP_ACCEL_CAPABILITIES_LZ4_COMPRESSION = BIT(24),
108 	ICP_ACCEL_CAPABILITIES_LZ4S_COMPRESSION = BIT(25),
109 	ICP_ACCEL_CAPABILITIES_AES_V2 = BIT(26),
110 	ICP_ACCEL_CAPABILITIES_KPT2 = BIT(27),
124 #define QAT_AUTH_SHA3_PADDING_BITPOS 16
157 #define QAT_HW_ROUND_UP(val, n) (((val) + ((n)-1)) & (~(n - 1)))
159 #define ICP_QAT_HW_MD5_STATE1_SZ 16
169 #define ICP_QAT_HW_AES_XCBC_MAC_STATE1_SZ 16
170 #define ICP_QAT_HW_AES_CBC_MAC_STATE1_SZ 16
172 #define ICP_QAT_HW_KASUMI_F9_STATE1_SZ 16
173 #define ICP_QAT_HW_GALOIS_128_STATE1_SZ 16
177 #define ICP_QAT_HW_MD5_STATE2_SZ 16
187 #define ICP_QAT_HW_AES_XCBC_MAC_KEY_SZ 16
188 #define ICP_QAT_HW_AES_CBC_MAC_KEY_SZ 16
189 #define ICP_QAT_HW_AES_CCM_CBC_E_CTR0_SZ 16
190 #define ICP_QAT_HW_F9_IK_SZ 16
191 #define ICP_QAT_HW_F9_FK_SZ 16
197 #define ICP_QAT_HW_GALOIS_H_SZ 16
199 #define ICP_QAT_HW_GALOIS_E_CTR0_SZ 16
271 #define QAT_CIPHER_AEAD_AAD_SIZE_BITPOS 16
282 #define ICP_QAT_HW_AES_BLK_SZ 16
289 #define ICP_QAT_HW_AES_128_KEY_SZ 16
302 #define ICP_QAT_HW_KASUMI_KEY_SZ 16
310 #define ICP_QAT_HW_SNOW_3G_UEA2_KEY_SZ 16
311 #define ICP_QAT_HW_SNOW_3G_UEA2_IV_SZ 16
312 #define ICP_QAT_HW_ZUC_3G_EEA3_KEY_SZ 16
313 #define ICP_QAT_HW_ZUC_3G_EEA3_IV_SZ 16