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/freebsd/sys/contrib/device-tree/Bindings/media/
H A Dqcom,sdm660-camss.yaml109 port@0:
341 iommus = <&mmss_smmu 0xc00>,
342 <&mmss_smmu 0xc01>,
343 <&mmss_smmu 0xc02>,
344 <&mmss_smmu 0xc03>;
349 reg = <0x0ca00020 0x10>,
350 <0x0ca30000 0x100>,
351 <0x0ca30400 0x100>,
352 <0x0ca30800 0x100>,
353 <0x0ca30c00 0x100>,
[all …]
H A Dqcom,sm8250-camss.yaml113 port@0:
308 reg = <0 0xac6a000 0 0x2000>,
309 <0 0xac6c000 0 0x2000>,
310 <0 0xac6e000 0 0x1000>,
311 <0 0xac70000 0 0x1000>,
312 <0 0xac72000 0 0x1000>,
313 <0 0xac74000 0 0x1000>,
314 <0 0xacb4000 0 0xd000>,
315 <0 0xacc3000 0 0xd000>,
316 <0 0xacd9000 0 0x2200>,
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/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMSystemRegister.td3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
40 let M2M3Encoding8{7-0} = Enc12{7-0};
47 def : MClassSysReg<0, 0, 0, 0x400, "apsr_g">;
48 def : MClassSysReg<0, 1, 1, 0xc00, "apsr_nzcvqg">;
49 def : MClassSysReg<0, 0, 0, 0x401, "iapsr_g">;
50 def : MClassSysReg<0, 1, 1, 0xc01, "iapsr_nzcvqg">;
51 def : MClassSysReg<0, 0, 0, 0x402, "eapsr_g">;
52 def : MClassSysReg<0, 1, 1, 0xc02, "eapsr_nzcvqg">;
53 def : MClassSysReg<0, 0, 0, 0x403, "xpsr_g">;
54 def : MClassSysReg<0, 1, 1, 0xc03, "xpsr_nzcvqg">;
[all …]
/freebsd/crypto/heimdal/lib/wind/
H A Dbidi_table.c9 {0x5be, 1},
10 {0x5c0, 1},
11 {0x5c3, 1},
12 {0x5d0, 0x1b},
13 {0x5f0, 0x5},
14 {0x61b, 1},
15 {0x61f, 1},
16 {0x621, 0x1a},
17 {0x640, 0xb},
18 {0x66d, 0x3},
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/freebsd/cddl/contrib/opensolaris/lib/libctf/common/
H A Dctf.5153 +-------------+ 0t0
155 | +-------------+ 0t4
157 || +-------------+ 0t36 + cth_lbloff
159 ||| +-------------+ 0t36 + cth_objtoff
161 |||| +-------------+ 0t36 + cth_funcoff
163 ||||| +-------------+ 0t36 + cth_typeoff
165 |||||| +-------------+ 0t36 + cth_stroff
167 ||||||| +-------------+ 0t36 + cth_stroff + cth_strlen
174 +---------| 0xcf | 0xf1 | 0x03 | 0x00 |
176 |||||| 0 1 2 3 4
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/freebsd/sys/riscv/include/
H A Dencoding.h8 #define MATCH_BEQ 0x63
9 #define MASK_BEQ 0x707f
10 #define MATCH_BNE 0x1063
11 #define MASK_BNE 0x707f
12 #define MATCH_BLT 0x4063
13 #define MASK_BLT 0x707f
14 #define MATCH_BGE 0x5063
15 #define MASK_BGE 0x707f
16 #define MATCH_BLTU 0x6063
17 #define MASK_BLTU 0x707f
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/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVSystemOperands.td3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
30 // Privilege Access: Read and Write = 0, 1, 2; Read-Only = 3.
31 // Privilege Mode: User = 0, System = 1 or Machine = 3.
37 // bits<6> Number = op{5 - 0};
39 bit isRV32Only = 0;
78 def SysRegFFLAGS : SysReg<"fflags", 0x001>;
79 def SysRegFRM : SysReg<"frm", 0x002>;
80 def SysRegFCSR : SysReg<"fcsr", 0x003>;
85 def CYCLE : SysReg<"cycle", 0xC00>;
86 def TIME : SysReg<"time", 0xC01>;
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/freebsd/contrib/file/magic/Magdir/
H A Dole2compounddocs9 0 string \320\317\021\340\241\261\032\341
12 >0x1A ushort !0xABAB OLE 2 Compound Document
13 #>0x1C uleshort x \b, endnian %#4.4x
15 >>0x1C ubeshort =0xfffe \b, big-endian
20 # Byte Order 0xFFFE means little-endian found in real world applications
21 #>>0x1C uleshort =0xfffe \b, little-endian
22 >>0x1C uleshort =0xfffe
25 >>>0x1A uleshort x \b, v%u
27 >>>0x18 uleshort x \b.%u
36 >>>60 ulelong !0xffFFffFE \b, Mini FAT start sector %#x
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/qcom/
H A Dsdm630.dtsi34 #clock-cells = <0>;
41 #clock-cells = <0>;
49 #size-cells = <0>;
54 reg = <0x0 0x100>;
74 reg = <0x0 0x101>;
89 reg = <0x0 0x102>;
104 reg = <0x
[all...]
H A Dsc8180x.dtsi28 #clock-cells = <0>;
34 #clock-cells = <0>;
42 #size-cells = <0>;
44 CPU0: cpu@0 {
47 reg = <0x0 0x0>;
51 qcom,freq-domain = <&cpufreq_hw 0>;
58 clocks = <&cpufreq_hw 0>;
76 reg = <0x0 0x10
[all...]
H A Dsm8250.dtsi82 #clock-cells = <0>;
90 #clock-cells = <0>;
96 #size-cells = <0>;
98 CPU0: cpu@0 {
101 reg = <0x0 0x0>;
102 clocks = <&cpufreq_hw 0>;
109 qcom,freq-domain = <&cpufreq_hw 0>;
111 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
[all...]
/freebsd/contrib/llvm-project/llvm/lib/TargetParser/
H A DHost.cpp3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
82 // The cpu line is second (after the 'processor: 0' line), so if this in getHostCPUNameForPowerPC()
90 size_t CPULen = 0; in getHostCPUNameForPowerPC()
173 for (unsigned I = 0, E = Lines.size(); I != E; ++I) { in getHostCPUNameForARM()
182 if (Implementer == "0x41") { // ARM Ltd. in getHostCPUNameForARM()
189 // The CPU part is a 3 digit hexadecimal number with a 0x prefix. The in getHostCPUNameForARM()
195 .Case("0x926", "arm926ej-s") in getHostCPUNameForARM()
196 .Case("0xb02", "mpcore") in getHostCPUNameForARM()
197 .Case("0xb36", "arm1136j-s") in getHostCPUNameForARM()
198 .Case("0xb56", "arm1156t2-s") in getHostCPUNameForARM()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZInstrInfo.td3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
60 def BRC : CondBranchRI <"j#", 0xA74, z_br_ccmask>;
63 def BRCL : CondBranchRIL<"jg#", 0xC04>;
65 def BC : CondBranchRX<"b#", 0x47>;
66 def BCR : CondBranchRR<"b#r", 0x07>;
67 def BIC : CondBranchRXY<"bi#", 0xe347>,
74 def BRCAsm : AsmCondBranchRI <"brc", 0xA74>;
75 def BRCLAsm : AsmCondBranchRIL<"brcl", 0xC04>;
77 def BCAsm : AsmCondBranchRX<"bc", 0x47>;
78 def BCRAsm : AsmCondBranchRR<"bcr", 0x07>;
[all …]
/freebsd/sys/dev/sfxge/common/
H A Defx_regs_mcdi.h55 #define MC_SMEM_P0_DOORBELL_OFST 0x000
56 #define MC_SMEM_P1_DOORBELL_OFST 0x004
58 #define MC_SMEM_P0_PDU_OFST 0x008
59 #define MC_SMEM_P1_PDU_OFST 0x108
60 #define MC_SMEM_PDU_LEN 0x100
61 #define MC_SMEM_P0_PTP_TIME_OFST 0x7f0
62 #define MC_SMEM_P0_STATUS_OFST 0x7f8
63 #define MC_SMEM_P1_STATUS_OFST 0x7fc
67 #define MC_STATUS_DWORD_REBOOT (0xb007b007)
68 #define MC_STATUS_DWORD_ASSERT (0xdeaddead)
[all …]