Lines Matching +full:0 +full:xc01
55 #define MC_SMEM_P0_DOORBELL_OFST 0x000
56 #define MC_SMEM_P1_DOORBELL_OFST 0x004
58 #define MC_SMEM_P0_PDU_OFST 0x008
59 #define MC_SMEM_P1_PDU_OFST 0x108
60 #define MC_SMEM_PDU_LEN 0x100
61 #define MC_SMEM_P0_PTP_TIME_OFST 0x7f0
62 #define MC_SMEM_P0_STATUS_OFST 0x7f8
63 #define MC_SMEM_P1_STATUS_OFST 0x7fc
67 #define MC_STATUS_DWORD_REBOOT (0xb007b007)
68 #define MC_STATUS_DWORD_ASSERT (0xdeaddead)
71 #define MC_FW_VERSION_IS_BOOTLOADER(_v) (((_v) >> 16) == 0xb007)
76 * least every driver must support version 0 and MCDI_PCOL_VERSION
84 /* Unused commands: 0x23, 0x27, 0x30, 0x31 */
91 * 0 7 8 16 20 22 23 24 31
117 #define MCDI_HEADER_OFST 0
118 #define MCDI_HEADER_CODE_LBN 0
137 #define MCDI_HEADER_XFLAGS_EVREQ 0x01
139 #define MCDI_HEADER_XFLAGS_DBRET 0x02
142 #define MCDI_CTL_SDU_LEN_MAX_V1 0xfc
143 #define MCDI_CTL_SDU_LEN_MAX_V2 0x400
158 * 0 32 33 36 44 52 60
168 * 0 8 16 24 32
172 * LEVEL==ERR, Datalen == 0 => Reboot
176 * examining the first byte which is 0xc0. This corresponds to the
179 * 0 7 8
180 * | command | Resync | = 0xc0
183 * providing bits 56-63 of the event are 0xc0.
186 * | Rsvd | Code | = 0xc0
188 * Which means for convenience the event code is 0xc for all MC
191 #define FSE_AZ_EV_CODE_MCDI_EVRESPONSE 0xc
241 #define MC_CMD_ERR_ALLOC_FAIL 0x1000
243 #define MC_CMD_ERR_NO_VADAPTOR 0x1001
245 #define MC_CMD_ERR_NO_EVB_PORT 0x1002
247 #define MC_CMD_ERR_NO_VSWITCH 0x1003
249 #define MC_CMD_ERR_VLAN_LIMIT 0x1004
251 #define MC_CMD_ERR_BAD_PCI_FUNC 0x1005
253 #define MC_CMD_ERR_BAD_VLAN_MODE 0x1006
255 #define MC_CMD_ERR_BAD_VSWITCH_TYPE 0x1007
257 #define MC_CMD_ERR_BAD_VPORT_TYPE 0x1008
259 #define MC_CMD_ERR_MAC_EXIST 0x1009
261 #define MC_CMD_ERR_SLAVE_NOT_PRESENT 0x100a
263 #define MC_CMD_ERR_DATAPATH_DISABLED 0x100b
265 #define MC_CMD_ERR_CLIENT_NOT_FN 0x100c
270 #define MC_CMD_ERR_TRANSPORT_NOPROXY 0x100d
272 #define MC_CMD_ERR_VLAN_EXIST 0x100e
274 #define MC_CMD_ERR_NO_MAC_ADDR 0x100f
280 #define MC_CMD_ERR_PROXY_PENDING 0x1010
285 #define MC_CMD_ERR_PROXY_INPROGRESS 0x1011
289 #define MC_CMD_ERR_PROXY_UNEXPECTED 0x1012
296 #define MC_CMD_ERR_NO_PRIVILEGE 0x1013
301 #define MC_CMD_ERR_FILTERS_PRESENT 0x1014
304 #define MC_CMD_ERR_NO_CLOCK 0x1015
307 #define MC_CMD_ERR_UNREACHABLE 0x1016
310 #define MC_CMD_ERR_QUEUE_FULL 0x1017
314 #define MC_CMD_ERR_NO_PCIE 0x1018
318 #define MC_CMD_ERR_NO_DATAPATH 0x1019
320 #define MC_CMD_ERR_VIS_PRESENT 0x101a
322 #define MC_CMD_ERR_PIOBUFS_PRESENT 0x101b
324 #define MC_CMD_ERR_CODE_OFST 0
329 #define MC_CMD_CMD_SPACE_ESCAPE_0 0x78
330 #define MC_CMD_CMD_SPACE_ESCAPE_1 0x79
331 #define MC_CMD_CMD_SPACE_ESCAPE_2 0x7A
332 #define MC_CMD_CMD_SPACE_ESCAPE_3 0x7B
333 #define MC_CMD_CMD_SPACE_ESCAPE_4 0x7C
334 #define MC_CMD_CMD_SPACE_ESCAPE_5 0x7D
335 #define MC_CMD_CMD_SPACE_ESCAPE_6 0x7E
336 #define MC_CMD_CMD_SPACE_ESCAPE_7 0x7F
340 #define SIENA_MC_BOOTROM_COPYCODE_VEC (0x800 - 3 * 0x4)
341 #define HUNT_MC_BOOTROM_COPYCODE_VEC (0x8000 - 3 * 0x4)
342 #define MEDFORD_MC_BOOTROM_COPYCODE_VEC (0x10000 - 3 * 0x4)
344 #define SIENA_MC_BOOTROM_NOFLASH_VEC (0x800 - 2 * 0x4)
345 #define HUNT_MC_BOOTROM_NOFLASH_VEC (0x8000 - 2 * 0x4)
346 #define MEDFORD_MC_BOOTROM_NOFLASH_VEC (0x10000 - 2 * 0x4)
348 #define SIENA_MC_BOOTROM_RECOVERY_VEC (0x800 - 2 * 0x4)
349 #define HUNT_MC_BOOTROM_RECOVERY_VEC (0x8000 - 2 * 0x4)
350 #define MEDFORD_MC_BOOTROM_RECOVERY_VEC (0x10000 - 2 * 0x4)
353 #define MEDFORD_MC_BOOTROM_REAL_NOFLASH_VEC (0x10000 - 4 * 0x4)
361 0, 0, 0 }
384 #define EVB_STACK_ID(n) (((n) & 0xff) << 16)
389 * may be followed by the (0-based) number of the first argument that
406 #define MCDI_EVENT_LEVEL_INFO 0x0
408 #define MCDI_EVENT_LEVEL_WARN 0x1
410 #define MCDI_EVENT_LEVEL_ERR 0x2
412 #define MCDI_EVENT_LEVEL_FATAL 0x3
413 #define MCDI_EVENT_DATA_OFST 0
415 #define MCDI_EVENT_CMDDONE_SEQ_LBN 0
421 #define MCDI_EVENT_LINKCHANGE_LP_CAP_LBN 0
426 #define MCDI_EVENT_LINKCHANGE_SPEED_UNKNOWN 0x0
428 #define MCDI_EVENT_LINKCHANGE_SPEED_100M 0x1
430 #define MCDI_EVENT_LINKCHANGE_SPEED_1G 0x2
432 #define MCDI_EVENT_LINKCHANGE_SPEED_10G 0x3
434 #define MCDI_EVENT_LINKCHANGE_SPEED_40G 0x4
436 #define MCDI_EVENT_LINKCHANGE_SPEED_25G 0x5
438 #define MCDI_EVENT_LINKCHANGE_SPEED_50G 0x6
440 #define MCDI_EVENT_LINKCHANGE_SPEED_100G 0x7
445 #define MCDI_EVENT_SENSOREVT_MONITOR_LBN 0
453 #define MCDI_EVENT_FWALERT_REASON_LBN 0
456 #define MCDI_EVENT_FWALERT_REASON_SRAM_ACCESS 0x1
457 #define MCDI_EVENT_FLR_VF_LBN 0
459 #define MCDI_EVENT_TX_ERR_TXQ_LBN 0
464 #define MCDI_EVENT_TX_ERR_DL_FAIL 0x1
466 #define MCDI_EVENT_TX_ERR_NO_EOP 0x2
468 #define MCDI_EVENT_TX_ERR_2BIG 0x3
470 #define MCDI_EVENT_TX_BAD_OPTDESC 0x5
472 #define MCDI_EVENT_TX_OPT_IN_PKT 0x8
474 #define MCDI_EVENT_TX_ERR_BAD_DMA_OR_PIO 0x9
479 #define MCDI_EVENT_TX_FLUSH_TXQ_LBN 0
481 #define MCDI_EVENT_PTP_ERR_TYPE_LBN 0
484 #define MCDI_EVENT_PTP_ERR_PLL_LOST 0x1
486 #define MCDI_EVENT_PTP_ERR_FILTER 0x2
488 #define MCDI_EVENT_PTP_ERR_FIFO 0x3
490 #define MCDI_EVENT_PTP_ERR_QUEUE 0x4
491 #define MCDI_EVENT_AOE_ERR_TYPE_LBN 0
494 #define MCDI_EVENT_AOE_NO_LOAD 0x1
496 #define MCDI_EVENT_AOE_FC_ASSERT 0x2
498 #define MCDI_EVENT_AOE_FC_WATCHDOG 0x3
500 #define MCDI_EVENT_AOE_FC_NO_START 0x4
504 #define MCDI_EVENT_AOE_FAULT 0x5
506 #define MCDI_EVENT_AOE_CPLD_REPROGRAMMED 0x6
508 #define MCDI_EVENT_AOE_LOAD 0x7
510 #define MCDI_EVENT_AOE_DMA 0x8
514 #define MCDI_EVENT_AOE_BYTEBLASTER 0x9
516 #define MCDI_EVENT_AOE_DDR_ECC_STATUS 0xa
518 #define MCDI_EVENT_AOE_PTP_STATUS 0xb
520 #define MCDI_EVENT_AOE_FPGA_LOAD_HEADER_ERR 0xc
522 #define MCDI_EVENT_AOE_FPGA_POWER_OFF 0xd
524 #define MCDI_EVENT_AOE_FPGA_LOAD_FAILED 0xe
526 #define MCDI_EVENT_AOE_INVALID_FPGA_FLASH_TYPE 0xf
528 #define MCDI_EVENT_AOE_FC_RUN_TIMEDOUT 0x10
530 #define MCDI_EVENT_AOE_FPGA_BOOT_FLASH_INVALID 0x11
532 #define MCDI_EVENT_AOE_FPGA_BOOT_FLASH_HDR_INVALID 0x12
534 #define MCDI_EVENT_AOE_FPGA_CLOCKS_PROGRAM_FAILED 0x13
536 #define MCDI_EVENT_AOE_FC_RUNNING 0x14
542 #define MCDI_EVENT_AOE_ERR_FC_ASSERT_SEEN 0x0
545 #define MCDI_EVENT_AOE_ERR_FC_ASSERT_DATA_READY 0x1
549 #define MCDI_EVENT_AOE_ERR_FPGA_HEADER_NV_READ_FAIL 0x0
551 #define MCDI_EVENT_AOE_ERR_FPGA_HEADER_MAGIC_FAIL 0x1
553 #define MCDI_EVENT_AOE_ERR_FPGA_HEADER_SILICON_TYPE 0x2
555 #define MCDI_EVENT_AOE_ERR_FPGA_HEADER_VRATIO 0x3
557 #define MCDI_EVENT_AOE_ERR_FPGA_HEADER_DDR_TYPE 0x4
559 #define MCDI_EVENT_AOE_ERR_FPGA_HEADER_DDR_VOLTAGE 0x5
561 #define MCDI_EVENT_AOE_ERR_FPGA_HEADER_DDR_SPEED 0x6
563 #define MCDI_EVENT_AOE_ERR_FPGA_HEADER_DDR_SIZE 0x7
565 #define MCDI_EVENT_AOE_ERR_FPGA_HEADER_DDR_RANK 0x8
569 #define MCDI_EVENT_AOE_FLASH_TYPE_BOOT_PRIMARY 0x0
571 #define MCDI_EVENT_AOE_FLASH_TYPE_BOOT_SECONDARY 0x1
576 #define MCDI_EVENT_RX_ERR_RXQ_LBN 0
584 #define MCDI_EVENT_RX_FLUSH_RXQ_LBN 0
586 #define MCDI_EVENT_MC_REBOOT_COUNT_LBN 0
588 #define MCDI_EVENT_MUM_ERR_TYPE_LBN 0
591 #define MCDI_EVENT_MUM_NO_LOAD 0x1
593 #define MCDI_EVENT_MUM_ASSERT 0x2
595 #define MCDI_EVENT_MUM_WATCHDOG 0x3
598 #define MCDI_EVENT_DBRET_SEQ_LBN 0
600 #define MCDI_EVENT_SUC_ERR_TYPE_LBN 0
603 #define MCDI_EVENT_SUC_BAD_APP 0x1
605 #define MCDI_EVENT_SUC_ASSERT 0x2
607 #define MCDI_EVENT_SUC_EXCEPTION 0x3
609 #define MCDI_EVENT_SUC_WATCHDOG 0x4
614 #define MCDI_EVENT_DATA_LBN 0
623 #define MCDI_EVENT_SW_EVENT 0x0
625 #define MCDI_EVENT_CODE_BADSSERT 0x1
627 #define MCDI_EVENT_CODE_PMNOTICE 0x2
629 #define MCDI_EVENT_CODE_CMDDONE 0x3
631 #define MCDI_EVENT_CODE_LINKCHANGE 0x4
633 #define MCDI_EVENT_CODE_SENSOREVT 0x5
635 #define MCDI_EVENT_CODE_SCHEDERR 0x6
637 #define MCDI_EVENT_CODE_REBOOT 0x7
639 #define MCDI_EVENT_CODE_MAC_STATS_DMA 0x8
641 #define MCDI_EVENT_CODE_FWALERT 0x9
643 #define MCDI_EVENT_CODE_FLR 0xa
645 #define MCDI_EVENT_CODE_TX_ERR 0xb
647 #define MCDI_EVENT_CODE_TX_FLUSH 0xc
649 #define MCDI_EVENT_CODE_PTP_RX 0xd
651 #define MCDI_EVENT_CODE_PTP_FAULT 0xe
653 #define MCDI_EVENT_CODE_PTP_PPS 0xf
655 #define MCDI_EVENT_CODE_RX_FLUSH 0x10
657 #define MCDI_EVENT_CODE_RX_ERR 0x11
659 #define MCDI_EVENT_CODE_AOE 0x12
661 #define MCDI_EVENT_CODE_VCAL_FAIL 0x13
663 #define MCDI_EVENT_CODE_HW_PPS 0x14
667 #define MCDI_EVENT_CODE_MC_REBOOT 0x15
669 #define MCDI_EVENT_CODE_PAR_ERR 0x16
671 #define MCDI_EVENT_CODE_ECC_CORR_ERR 0x17
673 #define MCDI_EVENT_CODE_ECC_FATAL_ERR 0x18
675 #define MCDI_EVENT_CODE_MC_BIST 0x19
677 #define MCDI_EVENT_CODE_PTP_TIME 0x1a
679 #define MCDI_EVENT_CODE_MUM 0x1b
681 #define MCDI_EVENT_CODE_PROXY_REQUEST 0x1c
685 #define MCDI_EVENT_CODE_PROXY_RESPONSE 0x1d
689 #define MCDI_EVENT_CODE_DBRET 0x1e
691 #define MCDI_EVENT_CODE_SUC 0x1f
695 #define MCDI_EVENT_CODE_TESTGEN 0xfa
696 #define MCDI_EVENT_CMDDONE_DATA_OFST 0
698 #define MCDI_EVENT_CMDDONE_DATA_LBN 0
700 #define MCDI_EVENT_LINKCHANGE_DATA_OFST 0
702 #define MCDI_EVENT_LINKCHANGE_DATA_LBN 0
704 #define MCDI_EVENT_SENSOREVT_DATA_OFST 0
706 #define MCDI_EVENT_SENSOREVT_DATA_LBN 0
708 #define MCDI_EVENT_MAC_STATS_DMA_GENERATION_OFST 0
710 #define MCDI_EVENT_MAC_STATS_DMA_GENERATION_LBN 0
712 #define MCDI_EVENT_TX_ERR_DATA_OFST 0
714 #define MCDI_EVENT_TX_ERR_DATA_LBN 0
719 #define MCDI_EVENT_PTP_SECONDS_OFST 0
721 #define MCDI_EVENT_PTP_SECONDS_LBN 0
726 #define MCDI_EVENT_PTP_MAJOR_OFST 0
728 #define MCDI_EVENT_PTP_MAJOR_LBN 0
733 #define MCDI_EVENT_PTP_NANOSECONDS_OFST 0
735 #define MCDI_EVENT_PTP_NANOSECONDS_LBN 0
740 #define MCDI_EVENT_PTP_MINOR_OFST 0
742 #define MCDI_EVENT_PTP_MINOR_LBN 0
746 #define MCDI_EVENT_PTP_UUID_OFST 0
748 #define MCDI_EVENT_PTP_UUID_LBN 0
750 #define MCDI_EVENT_RX_ERR_DATA_OFST 0
752 #define MCDI_EVENT_RX_ERR_DATA_LBN 0
754 #define MCDI_EVENT_PAR_ERR_DATA_OFST 0
756 #define MCDI_EVENT_PAR_ERR_DATA_LBN 0
758 #define MCDI_EVENT_ECC_CORR_ERR_DATA_OFST 0
760 #define MCDI_EVENT_ECC_CORR_ERR_DATA_LBN 0
762 #define MCDI_EVENT_ECC_FATAL_ERR_DATA_OFST 0
764 #define MCDI_EVENT_ECC_FATAL_ERR_DATA_LBN 0
767 #define MCDI_EVENT_PTP_TIME_MAJOR_OFST 0
769 #define MCDI_EVENT_PTP_TIME_MAJOR_LBN 0
799 #define MCDI_EVENT_PROXY_REQUEST_BUFF_INDEX_OFST 0
801 #define MCDI_EVENT_PROXY_REQUEST_BUFF_INDEX_LBN 0
803 #define MCDI_EVENT_PROXY_RESPONSE_HANDLE_OFST 0
805 #define MCDI_EVENT_PROXY_RESPONSE_HANDLE_LBN 0
813 #define MCDI_EVENT_DBRET_DATA_OFST 0
815 #define MCDI_EVENT_DBRET_DATA_LBN 0
825 #define FCDI_EVENT_LEVEL_INFO 0x0
827 #define FCDI_EVENT_LEVEL_WARN 0x1
829 #define FCDI_EVENT_LEVEL_ERR 0x2
831 #define FCDI_EVENT_LEVEL_FATAL 0x3
832 #define FCDI_EVENT_DATA_OFST 0
834 #define FCDI_EVENT_LINK_STATE_STATUS_LBN 0
836 #define FCDI_EVENT_LINK_DOWN 0x0 /* enum */
837 #define FCDI_EVENT_LINK_UP 0x1 /* enum */
838 #define FCDI_EVENT_DATA_LBN 0
847 #define FCDI_EVENT_CODE_REBOOT 0x1
849 #define FCDI_EVENT_CODE_ASSERT 0x2
851 #define FCDI_EVENT_CODE_DDR_TEST_RESULT 0x3
853 #define FCDI_EVENT_CODE_LINK_STATE 0x4
855 #define FCDI_EVENT_CODE_TIMED_READ 0x5
857 #define FCDI_EVENT_CODE_PPS_IN 0x6
859 #define FCDI_EVENT_CODE_PTP_TICK 0x7
861 #define FCDI_EVENT_CODE_DDR_ECC_STATUS 0x8
863 #define FCDI_EVENT_CODE_PTP_STATUS 0x9
865 #define FCDI_EVENT_CODE_PORT_CONFIG 0xa
867 #define FCDI_EVENT_CODE_BOOT_RESULT 0xb
870 #define FCDI_EVENT_REBOOT_FC_FW 0x0 /* enum */
871 #define FCDI_EVENT_REBOOT_FC_BOOTLOADER 0x1 /* enum */
872 #define FCDI_EVENT_ASSERT_INSTR_ADDRESS_OFST 0
874 #define FCDI_EVENT_ASSERT_INSTR_ADDRESS_LBN 0
880 #define FCDI_EVENT_DDR_TEST_RESULT_RESULT_OFST 0
882 #define FCDI_EVENT_DDR_TEST_RESULT_RESULT_LBN 0
884 #define FCDI_EVENT_LINK_STATE_DATA_OFST 0
886 #define FCDI_EVENT_LINK_STATE_DATA_LBN 0
888 #define FCDI_EVENT_PTP_STATE_OFST 0
890 #define FCDI_EVENT_PTP_UNDEFINED 0x0 /* enum */
891 #define FCDI_EVENT_PTP_SETUP_FAILED 0x1 /* enum */
892 #define FCDI_EVENT_PTP_OPERATIONAL 0x2 /* enum */
893 #define FCDI_EVENT_PTP_STATE_LBN 0
897 #define FCDI_EVENT_DDR_ECC_STATUS_STATUS_OFST 0
899 #define FCDI_EVENT_DDR_ECC_STATUS_STATUS_LBN 0
905 #define FCDI_EVENT_PORT_CONFIG_DATA_OFST 0
907 #define FCDI_EVENT_PORT_CONFIG_DATA_LBN 0
909 #define FCDI_EVENT_BOOT_RESULT_OFST 0
913 #define FCDI_EVENT_BOOT_RESULT_LBN 0
926 #define FCDI_EXTENDED_EVENT_PPS_COUNT_OFST 0
928 #define FCDI_EXTENDED_EVENT_PPS_COUNT_LBN 0
957 #define MUM_EVENT_LEVEL_INFO 0x0
959 #define MUM_EVENT_LEVEL_WARN 0x1
961 #define MUM_EVENT_LEVEL_ERR 0x2
963 #define MUM_EVENT_LEVEL_FATAL 0x3
964 #define MUM_EVENT_DATA_OFST 0
966 #define MUM_EVENT_SENSOR_ID_LBN 0
972 #define MUM_EVENT_PORT_PHY_READY_LBN 0
986 #define MUM_EVENT_DATA_LBN 0
995 #define MUM_EVENT_CODE_REBOOT 0x1
997 #define MUM_EVENT_CODE_ASSERT 0x2
999 #define MUM_EVENT_CODE_SENSOR 0x3
1001 #define MUM_EVENT_CODE_QSFP_LASI_INTERRUPT 0x4
1002 #define MUM_EVENT_SENSOR_DATA_OFST 0
1004 #define MUM_EVENT_SENSOR_DATA_LBN 0
1006 #define MUM_EVENT_PORT_PHY_FLAGS_OFST 0
1008 #define MUM_EVENT_PORT_PHY_FLAGS_LBN 0
1010 #define MUM_EVENT_PORT_PHY_COPPER_LEN_OFST 0
1012 #define MUM_EVENT_PORT_PHY_COPPER_LEN_LBN 0
1014 #define MUM_EVENT_PORT_PHY_CAPS_OFST 0
1016 #define MUM_EVENT_PORT_PHY_CAPS_LBN 0
1018 #define MUM_EVENT_PORT_PHY_TECH_OFST 0
1020 #define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_UNKNOWN 0x0 /* enum */
1021 #define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_OPTICAL 0x1 /* enum */
1022 #define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_COPPER_PASSIVE 0x2 /* enum */
1023 #define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_COPPER_PASSIVE_EQUALIZED 0x3 /* enum */
1024 #define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_COPPER_ACTIVE_LIMITING 0x4 /* enum */
1025 #define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_COPPER_ACTIVE_LINEAR 0x5 /* enum */
1026 #define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_BASE_T 0x6 /* enum */
1027 #define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_LOOPBACK_PASSIVE 0x7 /* enum */
1028 #define MUM_EVENT_PORT_PHY_TECH_LBN 0
1032 #define MUM_EVENT_PORT_PHY_SRC_DATA_ID_FLAGS 0x0 /* enum */
1033 #define MUM_EVENT_PORT_PHY_SRC_DATA_ID_COPPER_LEN 0x1 /* enum */
1034 #define MUM_EVENT_PORT_PHY_SRC_DATA_ID_CAPS 0x2 /* enum */
1035 #define MUM_EVENT_PORT_PHY_SRC_DATA_ID_TECH 0x3 /* enum */
1036 #define MUM_EVENT_PORT_PHY_SRC_DATA_ID_MAX 0x4 /* enum */
1046 #define MC_CMD_READ32 0x1
1053 #define MC_CMD_READ32_IN_ADDR_OFST 0
1061 #define MC_CMD_READ32_OUT_LEN(num) (0+4*(num))
1062 #define MC_CMD_READ32_OUT_BUFFER_OFST 0
1071 #define MC_CMD_WRITE32 0x2
1080 #define MC_CMD_WRITE32_IN_ADDR_OFST 0
1088 #define MC_CMD_WRITE32_OUT_LEN 0
1096 #define MC_CMD_COPYCODE 0x3
1109 #define MC_CMD_COPYCODE_IN_SRC_ADDR_OFST 0
1112 #define MC_CMD_COPYCODE_HUNT_NO_MAGIC_ADDR 0x10000
1116 #define MC_CMD_COPYCODE_HUNT_NO_DATAPATH_MAGIC_ADDR 0x1d0d0
1121 #define MC_CMD_COPYCODE_HUNT_IGNORE_CONFIG_MAGIC_ADDR 0x1badc
1143 #define MC_CMD_COPYCODE_JUMP_NONE 0x1
1146 #define MC_CMD_COPYCODE_OUT_LEN 0
1152 #define MC_CMD_SET_FUNC 0x4
1160 #define MC_CMD_SET_FUNC_IN_FUNC_OFST 0
1164 #define MC_CMD_SET_FUNC_OUT_LEN 0
1170 #define MC_CMD_GET_BOOT_STATUS 0x5
1176 #define MC_CMD_GET_BOOT_STATUS_IN_LEN 0
1181 #define MC_CMD_GET_BOOT_STATUS_OUT_BOOT_OFFSET_OFST 0
1184 #define MC_CMD_GET_BOOT_STATUS_OUT_BOOT_OFFSET_NULL 0xdeadbeef
1187 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_WATCHDOG_LBN 0
1200 #define MC_CMD_GET_ASSERTS 0x6
1208 #define MC_CMD_GET_ASSERTS_IN_CLEAR_OFST 0
1214 #define MC_CMD_GET_ASSERTS_OUT_GLOBAL_FLAGS_OFST 0
1217 #define MC_CMD_GET_ASSERTS_FLAGS_NO_FAILS 0x1
1219 #define MC_CMD_GET_ASSERTS_FLAGS_SYS_FAIL 0x2
1221 #define MC_CMD_GET_ASSERTS_FLAGS_THR_FAIL 0x3
1223 #define MC_CMD_GET_ASSERTS_FLAGS_WDOG_FIRED 0x4
1225 #define MC_CMD_GET_ASSERTS_FLAGS_ADDR_TRAP 0x5
1236 #define MC_CMD_GET_ASSERTS_REG_NO_DATA 0xda7a1057
1248 #define MC_CMD_LOG_CTRL 0x7
1256 #define MC_CMD_LOG_CTRL_IN_LOG_DEST_OFST 0
1259 #define MC_CMD_LOG_CTRL_IN_LOG_DEST_UART 0x1
1261 #define MC_CMD_LOG_CTRL_IN_LOG_DEST_EVQ 0x2
1267 #define MC_CMD_LOG_CTRL_OUT_LEN 0
1273 #define MC_CMD_GET_VERSION 0x8
1279 #define MC_CMD_GET_VERSION_IN_LEN 0
1283 /* placeholder, set to 0 */
1284 #define MC_CMD_GET_VERSION_EXT_IN_EXT_FLAGS_OFST 0
1289 #define MC_CMD_GET_VERSION_OUT_FIRMWARE_OFST 0
1292 #define MC_CMD_GET_VERSION_OUT_FIRMWARE_ANY 0xffffffff
1294 #define MC_CMD_GET_VERSION_OUT_FIRMWARE_SIENA_BOOTROM 0xb0070000
1296 #define MC_CMD_GET_VERSION_OUT_FIRMWARE_HUNT_BOOTROM 0xb0070001
1298 #define MC_CMD_GET_VERSION_OUT_FIRMWARE_MEDFORD2_BOOTROM 0xb0070002
1302 /* MC_CMD_GET_VERSION_OUT_FIRMWARE_OFST 0 */
1318 /* MC_CMD_GET_VERSION_OUT_FIRMWARE_OFST 0 */
1339 #define MC_CMD_PTP 0xb
1347 #define MC_CMD_PTP_IN_OP_OFST 0
1350 #define MC_CMD_PTP_OP_ENABLE 0x1
1352 #define MC_CMD_PTP_OP_DISABLE 0x2
1357 #define MC_CMD_PTP_OP_TRANSMIT 0x3
1359 #define MC_CMD_PTP_OP_READ_NIC_TIME 0x4
1363 #define MC_CMD_PTP_OP_STATUS 0x5
1365 #define MC_CMD_PTP_OP_ADJUST 0x6
1367 #define MC_CMD_PTP_OP_SYNCHRONIZE 0x7
1369 #define MC_CMD_PTP_OP_MANFTEST_BASIC 0x8
1371 #define MC_CMD_PTP_OP_MANFTEST_PACKET 0x9
1373 #define MC_CMD_PTP_OP_RESET_STATS 0xa
1375 #define MC_CMD_PTP_OP_DEBUG 0xb
1377 #define MC_CMD_PTP_OP_FPGAREAD 0xc
1379 #define MC_CMD_PTP_OP_FPGAWRITE 0xd
1381 #define MC_CMD_PTP_OP_CLOCK_OFFSET_ADJUST 0xe
1383 #define MC_CMD_PTP_OP_CLOCK_FREQ_ADJUST 0xf
1387 #define MC_CMD_PTP_OP_RX_SET_VLAN_FILTER 0x10
1391 #define MC_CMD_PTP_OP_RX_SET_UUID_FILTER 0x11
1395 #define MC_CMD_PTP_OP_RX_SET_DOMAIN_FILTER 0x12
1399 #define MC_CMD_PTP_OP_SET_CLK_SRC 0x13
1401 #define MC_CMD_PTP_OP_RST_CLK 0x14
1403 #define MC_CMD_PTP_OP_PPS_ENABLE 0x15
1405 #define MC_CMD_PTP_OP_GET_TIME_FORMAT 0x16
1409 #define MC_CMD_PTP_OP_GET_ATTRIBUTES 0x16
1413 #define MC_CMD_PTP_OP_GET_TIMESTAMP_CORRECTIONS 0x17
1417 #define MC_CMD_PTP_OP_TIME_EVENT_SUBSCRIBE 0x18
1419 #define MC_CMD_PTP_OP_TIME_EVENT_UNSUBSCRIBE 0x19
1423 #define MC_CMD_PTP_OP_MANFTEST_PPS 0x1a
1427 #define MC_CMD_PTP_OP_SET_SYNC_STATUS 0x1b
1429 #define MC_CMD_PTP_OP_MAX 0x1c
1433 #define MC_CMD_PTP_IN_CMD_OFST 0
1437 /* Not used. Events are always sent to function relative queue 0. */
1444 #define MC_CMD_PTP_MODE_V1 0x0
1446 #define MC_CMD_PTP_MODE_V1_VLAN 0x1
1448 #define MC_CMD_PTP_MODE_V2 0x2
1450 #define MC_CMD_PTP_MODE_V2_VLAN 0x3
1452 #define MC_CMD_PTP_MODE_V2_ENHANCED 0x4
1454 #define MC_CMD_PTP_MODE_FCOE 0x5
1458 /* MC_CMD_PTP_IN_CMD_OFST 0 */
1467 /* MC_CMD_PTP_IN_CMD_OFST 0 */
1482 /* MC_CMD_PTP_IN_CMD_OFST 0 */
1489 /* MC_CMD_PTP_IN_CMD_OFST 0 */
1496 /* MC_CMD_PTP_IN_CMD_OFST 0 */
1503 /* MC_CMD_PTP_IN_CMD_OFST 0 */
1513 #define MC_CMD_PTP_IN_ADJUST_BITS 0x28
1518 #define MC_CMD_PTP_IN_ADJUST_BITS_FP44 0x2c
1534 /* MC_CMD_PTP_IN_CMD_OFST 0 */
1544 /* MC_CMD_PTP_IN_ADJUST_BITS 0x28 */
1549 /* MC_CMD_PTP_IN_ADJUST_BITS_FP44 0x2c */
1568 /* MC_CMD_PTP_IN_CMD_OFST 0 */
1585 /* MC_CMD_PTP_IN_CMD_OFST 0 */
1592 /* MC_CMD_PTP_IN_CMD_OFST 0 */
1602 /* MC_CMD_PTP_IN_CMD_OFST 0 */
1609 /* MC_CMD_PTP_IN_CMD_OFST 0 */
1619 /* MC_CMD_PTP_IN_CMD_OFST 0 */
1632 /* MC_CMD_PTP_IN_CMD_OFST 0 */
1645 /* MC_CMD_PTP_IN_CMD_OFST 0 */
1664 /* MC_CMD_PTP_IN_CMD_OFST 0 */
1686 /* MC_CMD_PTP_IN_CMD_OFST 0 */
1700 /* MC_CMD_PTP_IN_CMD_OFST 0 */
1704 /* Number of VLAN tags, 0 if not VLAN */
1714 /* MC_CMD_PTP_IN_CMD_OFST 0 */
1718 /* 1 to enable UUID filtering, 0 to disable */
1729 /* MC_CMD_PTP_IN_CMD_OFST 0 */
1733 /* 1 to enable Domain filtering, 0 to disable */
1742 /* MC_CMD_PTP_IN_CMD_OFST 0 */
1750 #define MC_CMD_PTP_CLK_SRC_INTERNAL 0x0
1752 #define MC_CMD_PTP_CLK_SRC_EXTERNAL 0x1
1756 /* MC_CMD_PTP_IN_CMD_OFST 0 */
1763 /* MC_CMD_PTP_IN_CMD_OFST 0 */
1769 #define MC_CMD_PTP_ENABLE_PPS 0x0
1771 #define MC_CMD_PTP_DISABLE_PPS 0x1
1772 /* Not used. Events are always sent to function relative queue 0. */
1778 /* MC_CMD_PTP_IN_CMD_OFST 0 */
1785 /* MC_CMD_PTP_IN_CMD_OFST 0 */
1792 /* MC_CMD_PTP_IN_CMD_OFST 0 */
1799 /* MC_CMD_PTP_IN_CMD_OFST 0 */
1806 #define MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE_ID_LBN 0
1813 /* MC_CMD_PTP_IN_CMD_OFST 0 */
1821 #define MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_SINGLE 0x0
1823 #define MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_ALL 0x1
1830 /* MC_CMD_PTP_IN_CMD_OFST 0 */
1834 /* 1 to enable PPS test mode, 0 to disable and return result. */
1840 /* MC_CMD_PTP_IN_CMD_OFST 0 */
1848 #define MC_CMD_PTP_IN_SET_SYNC_STATUS_NOT_IN_SYNC 0x0
1850 #define MC_CMD_PTP_IN_SET_SYNC_STATUS_IN_SYNC 0x1
1862 #define MC_CMD_PTP_OUT_LEN 0
1867 #define MC_CMD_PTP_OUT_TRANSMIT_SECONDS_OFST 0
1870 #define MC_CMD_PTP_OUT_TRANSMIT_MAJOR_OFST 0
1880 #define MC_CMD_PTP_OUT_TIME_EVENT_SUBSCRIBE_LEN 0
1883 #define MC_CMD_PTP_OUT_TIME_EVENT_UNSUBSCRIBE_LEN 0
1888 #define MC_CMD_PTP_OUT_READ_NIC_TIME_SECONDS_OFST 0
1891 #define MC_CMD_PTP_OUT_READ_NIC_TIME_MAJOR_OFST 0
1903 #define MC_CMD_PTP_OUT_READ_NIC_TIME_V2_SECONDS_OFST 0
1906 #define MC_CMD_PTP_OUT_READ_NIC_TIME_V2_MAJOR_OFST 0
1921 #define MC_CMD_PTP_OUT_STATUS_CLOCK_FREQ_OFST 0
1972 #define MC_CMD_PTP_OUT_SYNCHRONIZE_LEN(num) (0+20*(num))
1974 #define MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_OFST 0
1979 #define MC_CMD_PTP_OUT_SYNCHRONIZE_HOSTSTART_OFST 0
2003 #define MC_CMD_PTP_OUT_MANFTEST_BASIC_TEST_RESULT_OFST 0
2006 #define MC_CMD_PTP_MANF_SUCCESS 0x0
2008 #define MC_CMD_PTP_MANF_FPGA_LOAD 0x1
2010 #define MC_CMD_PTP_MANF_FPGA_VERSION 0x2
2012 #define MC_CMD_PTP_MANF_FPGA_REGISTERS 0x3
2014 #define MC_CMD_PTP_MANF_OSCILLATOR 0x4
2016 #define MC_CMD_PTP_MANF_TIMESTAMPS 0x5
2018 #define MC_CMD_PTP_MANF_PACKET_COUNT 0x6
2020 #define MC_CMD_PTP_MANF_FILTER_COUNT 0x7
2022 #define MC_CMD_PTP_MANF_PACKET_ENOUGH 0x8
2024 #define MC_CMD_PTP_MANF_GPIO_TRIGGER 0x9
2026 #define MC_CMD_PTP_MANF_PPS_ENOUGH 0xa
2028 #define MC_CMD_PTP_MANF_PPS_PERIOD 0xb
2030 #define MC_CMD_PTP_MANF_PPS_NS 0xc
2032 #define MC_CMD_PTP_MANF_REGISTERS 0xd
2034 #define MC_CMD_PTP_MANF_CLOCK_READ 0xe
2042 #define MC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_RESULT_OFST 0
2054 #define MC_CMD_PTP_OUT_FPGAREAD_LEN(num) (0+1*(num))
2055 #define MC_CMD_PTP_OUT_FPGAREAD_BUFFER_OFST 0
2068 #define MC_CMD_PTP_OUT_GET_TIME_FORMAT_FORMAT_OFST 0
2071 #define MC_CMD_PTP_OUT_GET_TIME_FORMAT_SECONDS_NANOSECONDS 0x0
2073 #define MC_CMD_PTP_OUT_GET_TIME_FORMAT_16SECONDS_8NANOSECONDS 0x1
2075 #define MC_CMD_PTP_OUT_GET_TIME_FORMAT_SECONDS_27FRACTION 0x2
2084 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_TIME_FORMAT_OFST 0
2087 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_SECONDS_NANOSECONDS 0x0
2089 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_16SECONDS_8NANOSECONDS 0x1
2091 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_SECONDS_27FRACTION 0x2
2094 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_SECONDS_QTR_NANOSECONDS 0x3
2107 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_REPORT_SYNC_STATUS_LBN 0
2125 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_TRANSMIT_OFST 0
2140 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PTP_TX_OFST 0
2161 #define MC_CMD_PTP_OUT_MANFTEST_PPS_TEST_RESULT_OFST 0
2167 #define MC_CMD_PTP_OUT_SET_SYNC_STATUS_LEN 0
2173 #define MC_CMD_CSR_READ32 0xc
2181 #define MC_CMD_CSR_READ32_IN_ADDR_OFST 0
2191 #define MC_CMD_CSR_READ32_OUT_LEN(num) (0+4*(num))
2193 #define MC_CMD_CSR_READ32_OUT_BUFFER_OFST 0
2202 #define MC_CMD_CSR_WRITE32 0xd
2212 #define MC_CMD_CSR_WRITE32_IN_ADDR_OFST 0
2223 #define MC_CMD_CSR_WRITE32_OUT_STATUS_OFST 0
2231 #define MC_CMD_HP 0x54
2240 * INTERVAL is interpreted as a command: 0: stop OCSD / 1: Report OCSD current
2244 #define MC_CMD_HP_IN_SUBCMD_OFST 0
2247 #define MC_CMD_HP_IN_OCSD_SUBCMD 0x0
2249 #define MC_CMD_HP_IN_LAST_SUBCMD 0x0
2264 #define MC_CMD_HP_OUT_OCSD_STATUS_OFST 0
2267 #define MC_CMD_HP_OUT_OCSD_STOPPED 0x1
2269 #define MC_CMD_HP_OUT_OCSD_STARTED 0x2
2271 #define MC_CMD_HP_OUT_OCSD_ALREADY_STARTED 0x3
2277 #define MC_CMD_STACKINFO 0xf
2283 #define MC_CMD_STACKINFO_IN_LEN 0
2288 #define MC_CMD_STACKINFO_OUT_LEN(num) (0+12*(num))
2290 #define MC_CMD_STACKINFO_OUT_THREAD_INFO_OFST 0
2299 #define MC_CMD_MDIO_READ 0x10
2309 #define MC_CMD_MDIO_READ_IN_BUS_OFST 0
2312 #define MC_CMD_MDIO_BUS_INTERNAL 0x0
2314 #define MC_CMD_MDIO_BUS_EXTERNAL 0x1
2324 #define MC_CMD_MDIO_CLAUSE22 0x20
2332 #define MC_CMD_MDIO_READ_OUT_VALUE_OFST 0
2340 #define MC_CMD_MDIO_STATUS_GOOD 0x8
2346 #define MC_CMD_MDIO_WRITE 0x11
2356 #define MC_CMD_MDIO_WRITE_IN_BUS_OFST 0
2359 /* MC_CMD_MDIO_BUS_INTERNAL 0x0 */
2361 /* MC_CMD_MDIO_BUS_EXTERNAL 0x1 */
2371 /* MC_CMD_MDIO_CLAUSE22 0x20 */
2384 #define MC_CMD_MDIO_WRITE_OUT_STATUS_OFST 0
2387 /* MC_CMD_MDIO_STATUS_GOOD 0x8 */
2393 #define MC_CMD_DBI_WRITE 0x12
2401 #define MC_CMD_DBI_WRITE_IN_LEN(num) (0+12*(num))
2402 /* Each write op consists of an address (offset 0), byte enable/VF/CS2 (offset
2405 #define MC_CMD_DBI_WRITE_IN_DBIWROP_OFST 0
2411 #define MC_CMD_DBI_WRITE_OUT_LEN 0
2415 #define MC_CMD_DBIWROP_TYPEDEF_ADDRESS_OFST 0
2417 #define MC_CMD_DBIWROP_TYPEDEF_ADDRESS_LBN 0
2439 #define MC_CMD_PORT_READ32 0x14
2444 #define MC_CMD_PORT_READ32_IN_ADDR_OFST 0
2450 #define MC_CMD_PORT_READ32_OUT_VALUE_OFST 0
2461 #define MC_CMD_PORT_WRITE32 0x15
2466 #define MC_CMD_PORT_WRITE32_IN_ADDR_OFST 0
2475 #define MC_CMD_PORT_WRITE32_OUT_STATUS_OFST 0
2483 #define MC_CMD_PORT_READ128 0x16
2488 #define MC_CMD_PORT_READ128_IN_ADDR_OFST 0
2494 #define MC_CMD_PORT_READ128_OUT_VALUE_OFST 0
2505 #define MC_CMD_PORT_WRITE128 0x17
2510 #define MC_CMD_PORT_WRITE128_IN_ADDR_OFST 0
2519 #define MC_CMD_PORT_WRITE128_OUT_STATUS_OFST 0
2525 #define MC_CMD_CAPABILITIES_SMALL_BUF_TBL_LBN 0
2552 #define MC_CMD_GET_BOARD_CFG 0x18
2558 #define MC_CMD_GET_BOARD_CFG_IN_LEN 0
2564 #define MC_CMD_GET_BOARD_CFG_OUT_BOARD_TYPE_OFST 0
2623 #define MC_CMD_DBI_READX 0x19
2631 #define MC_CMD_DBI_READX_IN_LEN(num) (0+8*(num))
2632 /* Each Read op consists of an address (offset 0), VF/CS2) */
2633 #define MC_CMD_DBI_READX_IN_DBIRDOP_OFST 0
2635 #define MC_CMD_DBI_READX_IN_DBIRDOP_LO_OFST 0
2643 #define MC_CMD_DBI_READX_OUT_LEN(num) (0+4*(num))
2645 #define MC_CMD_DBI_READX_OUT_VALUE_OFST 0
2652 #define MC_CMD_DBIRDOP_TYPEDEF_ADDRESS_OFST 0
2654 #define MC_CMD_DBIRDOP_TYPEDEF_ADDRESS_LBN 0
2671 #define MC_CMD_SET_RAND_SEED 0x1a
2679 #define MC_CMD_SET_RAND_SEED_IN_SEED_OFST 0
2683 #define MC_CMD_SET_RAND_SEED_OUT_LEN 0
2689 #define MC_CMD_LTSSM_HIST 0x1b
2692 #define MC_CMD_LTSSM_HIST_IN_LEN 0
2695 #define MC_CMD_LTSSM_HIST_OUT_LENMIN 0
2697 #define MC_CMD_LTSSM_HIST_OUT_LEN(num) (0+4*(num))
2699 #define MC_CMD_LTSSM_HIST_OUT_DATA_OFST 0
2701 #define MC_CMD_LTSSM_HIST_OUT_DATA_MINNUM 0
2713 #define MC_CMD_DRV_ATTACH 0x1c
2721 #define MC_CMD_DRV_ATTACH_IN_NEW_STATE_OFST 0
2723 #define MC_CMD_DRV_ATTACH_LBN 0
2725 #define MC_CMD_DRV_ATTACH_IN_ATTACH_LBN 0
2735 /* 1 to set new state, or 0 to just report the existing state */
2742 #define MC_CMD_FW_FULL_FEATURED 0x0
2744 #define MC_CMD_FW_LOW_LATENCY 0x1
2746 #define MC_CMD_FW_PACKED_STREAM 0x2
2750 #define MC_CMD_FW_HIGH_TX_RATE 0x3
2752 #define MC_CMD_FW_PACKED_STREAM_HASH_MODE_1 0x4
2756 #define MC_CMD_FW_RULES_ENGINE 0x5
2758 #define MC_CMD_FW_DPDK 0x6
2762 #define MC_CMD_FW_L3XUDP 0x7
2768 #define MC_CMD_FW_KEEP_CURRENT_EFTEST_ONLY 0xfffffffe
2770 #define MC_CMD_FW_DONT_CARE 0xffffffff
2775 #define MC_CMD_DRV_ATTACH_OUT_OLD_STATE_OFST 0
2781 #define MC_CMD_DRV_ATTACH_EXT_OUT_OLD_STATE_OFST 0
2787 #define MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_PRIMARY 0x0
2791 #define MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_LINKCTRL 0x1
2793 #define MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_TRUSTED 0x2
2797 #define MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_NO_ACTIVE_PORT 0x3
2802 #define MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_VI_SPREADING_ENABLED 0x4
2808 #define MC_CMD_SHMUART 0x1f
2813 #define MC_CMD_SHMUART_IN_FLAG_OFST 0
2817 #define MC_CMD_SHMUART_OUT_LEN 0
2822 * required: None; Return code: 0, ETIME. NOTE: This command is deprecated -
2825 #define MC_CMD_PORT_RESET 0x20
2831 #define MC_CMD_PORT_RESET_IN_LEN 0
2834 #define MC_CMD_PORT_RESET_OUT_LEN 0
2839 * Locks required: None; Return code: 0, ETIME. NOTE: This command is an
2842 #define MC_CMD_ENTITY_RESET 0x20
2850 #define MC_CMD_ENTITY_RESET_IN_FLAG_OFST 0
2852 #define MC_CMD_ENTITY_RESET_IN_FUNCTION_RESOURCE_RESET_LBN 0
2856 #define MC_CMD_ENTITY_RESET_OUT_LEN 0
2862 #define MC_CMD_PCIE_CREDITS 0x21
2866 /* poll period. 0 is disabled */
2867 #define MC_CMD_PCIE_CREDITS_IN_POLL_PERIOD_OFST 0
2875 #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_P_HDR_OFST 0
2896 #define MC_CMD_RXD_MONITOR 0x22
2900 #define MC_CMD_RXD_MONITOR_IN_QID_OFST 0
2909 #define MC_CMD_RXD_MONITOR_OUT_QID_OFST 0
2954 #define MC_CMD_PUTS 0x23
2963 #define MC_CMD_PUTS_IN_DEST_OFST 0
2965 #define MC_CMD_PUTS_IN_UART_LBN 0
2977 #define MC_CMD_PUTS_OUT_LEN 0
2984 #define MC_CMD_GET_PHY_CFG 0x24
2990 #define MC_CMD_GET_PHY_CFG_IN_LEN 0
2995 #define MC_CMD_GET_PHY_CFG_OUT_FLAGS_OFST 0
2997 #define MC_CMD_GET_PHY_CFG_OUT_PRESENT_LBN 0
3075 #define MC_CMD_MEDIA_XAUI 0x1
3077 #define MC_CMD_MEDIA_CX4 0x2
3079 #define MC_CMD_MEDIA_KX4 0x3
3081 #define MC_CMD_MEDIA_XFP 0x4
3083 #define MC_CMD_MEDIA_SFP_PLUS 0x5
3085 #define MC_CMD_MEDIA_BASE_T 0x6
3087 #define MC_CMD_MEDIA_QSFP_PLUS 0x7
3091 #define MC_CMD_MMD_CLAUSE22 0x0
3092 #define MC_CMD_MMD_CLAUSE45_PMAPMD 0x1 /* enum */
3093 #define MC_CMD_MMD_CLAUSE45_WIS 0x2 /* enum */
3094 #define MC_CMD_MMD_CLAUSE45_PCS 0x3 /* enum */
3095 #define MC_CMD_MMD_CLAUSE45_PHYXS 0x4 /* enum */
3096 #define MC_CMD_MMD_CLAUSE45_DTEXS 0x5 /* enum */
3097 #define MC_CMD_MMD_CLAUSE45_TC 0x6 /* enum */
3098 #define MC_CMD_MMD_CLAUSE45_AN 0x7 /* enum */
3100 #define MC_CMD_MMD_CLAUSE45_C22EXT 0x1d
3101 #define MC_CMD_MMD_CLAUSE45_VEND1 0x1e /* enum */
3102 #define MC_CMD_MMD_CLAUSE45_VEND2 0x1f /* enum */
3109 * Return code: 0, EINVAL, EACCES (if PHY_LOCK is not held)
3111 #define MC_CMD_START_BIST 0x25
3119 #define MC_CMD_START_BIST_IN_TYPE_OFST 0
3122 #define MC_CMD_PHY_BIST_CABLE_SHORT 0x1
3124 #define MC_CMD_PHY_BIST_CABLE_LONG 0x2
3126 #define MC_CMD_BPX_SERDES_BIST 0x3
3128 #define MC_CMD_MC_LOOPBACK_BIST 0x4
3130 #define MC_CMD_PHY_BIST 0x5
3132 #define MC_CMD_MC_MEM_BIST 0x6
3134 #define MC_CMD_PORT_MEM_BIST 0x7
3136 #define MC_CMD_REG_BIST 0x8
3139 #define MC_CMD_START_BIST_OUT_LEN 0
3147 * OUT.RESULT. Locks required: PHY_LOCK if doing a PHY BIST. Return code: 0,
3150 #define MC_CMD_POLL_BIST 0x26
3156 #define MC_CMD_POLL_BIST_IN_LEN 0
3161 #define MC_CMD_POLL_BIST_OUT_RESULT_OFST 0
3164 #define MC_CMD_POLL_BIST_RUNNING 0x1
3166 #define MC_CMD_POLL_BIST_PASSED 0x2
3168 #define MC_CMD_POLL_BIST_FAILED 0x3
3170 #define MC_CMD_POLL_BIST_TIMEOUT 0x4
3177 /* MC_CMD_POLL_BIST_OUT_RESULT_OFST 0 */
3193 #define MC_CMD_POLL_BIST_SFT9001_PAIR_OK 0x1
3195 #define MC_CMD_POLL_BIST_SFT9001_PAIR_OPEN 0x2
3197 #define MC_CMD_POLL_BIST_SFT9001_INTRA_PAIR_SHORT 0x3
3199 #define MC_CMD_POLL_BIST_SFT9001_INTER_PAIR_SHORT 0x4
3201 #define MC_CMD_POLL_BIST_SFT9001_PAIR_BUSY 0x9
3221 /* MC_CMD_POLL_BIST_OUT_RESULT_OFST 0 */
3228 #define MC_CMD_POLL_BIST_MRSFP_TEST_COMPLETE 0x0
3230 #define MC_CMD_POLL_BIST_MRSFP_TEST_BUS_SWITCH_OFF_I2C_WRITE 0x1
3232 #define MC_CMD_POLL_BIST_MRSFP_TEST_BUS_SWITCH_OFF_I2C_NO_ACCESS_IO_EXP 0x2
3234 #define MC_CMD_POLL_BIST_MRSFP_TEST_BUS_SWITCH_OFF_I2C_NO_ACCESS_MODULE 0x3
3236 #define MC_CMD_POLL_BIST_MRSFP_TEST_IO_EXP_I2C_CONFIGURE 0x4
3238 #define MC_CMD_POLL_BIST_MRSFP_TEST_BUS_SWITCH_I2C_NO_CROSSTALK 0x5
3240 #define MC_CMD_POLL_BIST_MRSFP_TEST_MODULE_PRESENCE 0x6
3242 #define MC_CMD_POLL_BIST_MRSFP_TEST_MODULE_ID_I2C_ACCESS 0x7
3244 #define MC_CMD_POLL_BIST_MRSFP_TEST_MODULE_ID_SANE_VALUE 0x8
3249 /* MC_CMD_POLL_BIST_OUT_RESULT_OFST 0 */
3256 #define MC_CMD_POLL_BIST_MEM_COMPLETE 0x0
3258 #define MC_CMD_POLL_BIST_MEM_MEM_WALK_ONES 0x1
3260 #define MC_CMD_POLL_BIST_MEM_MEM_WALK_ZEROS 0x2
3262 #define MC_CMD_POLL_BIST_MEM_MEM_INV_ZERO_ONE 0x3
3264 #define MC_CMD_POLL_BIST_MEM_MEM_INV_CHKBOARD 0x4
3266 #define MC_CMD_POLL_BIST_MEM_REG 0x5
3268 #define MC_CMD_POLL_BIST_MEM_ECC 0x6
3276 #define MC_CMD_POLL_BIST_MEM_BUS_MC 0x0
3278 #define MC_CMD_POLL_BIST_MEM_BUS_CSR 0x1
3280 #define MC_CMD_POLL_BIST_MEM_BUS_DPCPU_RX 0x2
3282 #define MC_CMD_POLL_BIST_MEM_BUS_DPCPU_TX0 0x3
3284 #define MC_CMD_POLL_BIST_MEM_BUS_DPCPU_TX1 0x4
3286 #define MC_CMD_POLL_BIST_MEM_BUS_DICPU_RX 0x5
3288 #define MC_CMD_POLL_BIST_MEM_BUS_DICPU_TX 0x6
3290 #define MC_CMD_POLL_BIST_MEM_BUS_DPCPU_RX1 0x7
3292 #define MC_CMD_POLL_BIST_MEM_BUS_DICPU_RX1 0x8
3318 #define MC_CMD_FLUSH_RX_QUEUES 0x27
3323 #define MC_CMD_FLUSH_RX_QUEUES_IN_LEN(num) (0+4*(num))
3324 #define MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_OFST 0
3330 #define MC_CMD_FLUSH_RX_QUEUES_OUT_LEN 0
3336 #define MC_CMD_GET_LOOPBACK_MODES 0x28
3342 #define MC_CMD_GET_LOOPBACK_MODES_IN_LEN 0
3347 #define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_OFST 0
3349 #define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_LO_OFST 0
3352 #define MC_CMD_LOOPBACK_NONE 0x0
3354 #define MC_CMD_LOOPBACK_DATA 0x1
3356 #define MC_CMD_LOOPBACK_GMAC 0x2
3358 #define MC_CMD_LOOPBACK_XGMII 0x3
3360 #define MC_CMD_LOOPBACK_XGXS 0x4
3362 #define MC_CMD_LOOPBACK_XAUI 0x5
3364 #define MC_CMD_LOOPBACK_GMII 0x6
3366 #define MC_CMD_LOOPBACK_SGMII 0x7
3368 #define MC_CMD_LOOPBACK_XGBR 0x8
3370 #define MC_CMD_LOOPBACK_XFI 0x9
3372 #define MC_CMD_LOOPBACK_XAUI_FAR 0xa
3374 #define MC_CMD_LOOPBACK_GMII_FAR 0xb
3376 #define MC_CMD_LOOPBACK_SGMII_FAR 0xc
3378 #define MC_CMD_LOOPBACK_XFI_FAR 0xd
3380 #define MC_CMD_LOOPBACK_GPHY 0xe
3382 #define MC_CMD_LOOPBACK_PHYXS 0xf
3384 #define MC_CMD_LOOPBACK_PCS 0x10
3386 #define MC_CMD_LOOPBACK_PMAPMD 0x11
3388 #define MC_CMD_LOOPBACK_XPORT 0x12
3390 #define MC_CMD_LOOPBACK_XGMII_WS 0x13
3392 #define MC_CMD_LOOPBACK_XAUI_WS 0x14
3394 #define MC_CMD_LOOPBACK_XAUI_WS_FAR 0x15
3396 #define MC_CMD_LOOPBACK_XAUI_WS_NEAR 0x16
3398 #define MC_CMD_LOOPBACK_GMII_WS 0x17
3400 #define MC_CMD_LOOPBACK_XFI_WS 0x18
3402 #define MC_CMD_LOOPBACK_XFI_WS_FAR 0x19
3404 #define MC_CMD_LOOPBACK_PHYXS_WS 0x1a
3406 #define MC_CMD_LOOPBACK_PMA_INT 0x1b
3408 #define MC_CMD_LOOPBACK_SD_NEAR 0x1c
3410 #define MC_CMD_LOOPBACK_SD_FAR 0x1d
3412 #define MC_CMD_LOOPBACK_PMA_INT_WS 0x1e
3414 #define MC_CMD_LOOPBACK_SD_FEP2_WS 0x1f
3416 #define MC_CMD_LOOPBACK_SD_FEP1_5_WS 0x20
3418 #define MC_CMD_LOOPBACK_SD_FEP_WS 0x21
3420 #define MC_CMD_LOOPBACK_SD_FES_WS 0x22
3422 #define MC_CMD_LOOPBACK_AOE_INT_NEAR 0x23
3424 #define MC_CMD_LOOPBACK_DATA_WS 0x24
3428 #define MC_CMD_LOOPBACK_FORCE_EXT_LINK 0x25
3463 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100M_OFST 0
3465 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100M_LO_OFST 0
3468 /* MC_CMD_LOOPBACK_NONE 0x0 */
3470 /* MC_CMD_LOOPBACK_DATA 0x1 */
3472 /* MC_CMD_LOOPBACK_GMAC 0x2 */
3474 /* MC_CMD_LOOPBACK_XGMII 0x3 */
3476 /* MC_CMD_LOOPBACK_XGXS 0x4 */
3478 /* MC_CMD_LOOPBACK_XAUI 0x5 */
3480 /* MC_CMD_LOOPBACK_GMII 0x6 */
3482 /* MC_CMD_LOOPBACK_SGMII 0x7 */
3484 /* MC_CMD_LOOPBACK_XGBR 0x8 */
3486 /* MC_CMD_LOOPBACK_XFI 0x9 */
3488 /* MC_CMD_LOOPBACK_XAUI_FAR 0xa */
3490 /* MC_CMD_LOOPBACK_GMII_FAR 0xb */
3492 /* MC_CMD_LOOPBACK_SGMII_FAR 0xc */
3494 /* MC_CMD_LOOPBACK_XFI_FAR 0xd */
3496 /* MC_CMD_LOOPBACK_GPHY 0xe */
3498 /* MC_CMD_LOOPBACK_PHYXS 0xf */
3500 /* MC_CMD_LOOPBACK_PCS 0x10 */
3502 /* MC_CMD_LOOPBACK_PMAPMD 0x11 */
3504 /* MC_CMD_LOOPBACK_XPORT 0x12 */
3506 /* MC_CMD_LOOPBACK_XGMII_WS 0x13 */
3508 /* MC_CMD_LOOPBACK_XAUI_WS 0x14 */
3510 /* MC_CMD_LOOPBACK_XAUI_WS_FAR 0x15 */
3512 /* MC_CMD_LOOPBACK_XAUI_WS_NEAR 0x16 */
3514 /* MC_CMD_LOOPBACK_GMII_WS 0x17 */
3516 /* MC_CMD_LOOPBACK_XFI_WS 0x18 */
3518 /* MC_CMD_LOOPBACK_XFI_WS_FAR 0x19 */
3520 /* MC_CMD_LOOPBACK_PHYXS_WS 0x1a */
3522 /* MC_CMD_LOOPBACK_PMA_INT 0x1b */
3524 /* MC_CMD_LOOPBACK_SD_NEAR 0x1c */
3526 /* MC_CMD_LOOPBACK_SD_FAR 0x1d */
3528 /* MC_CMD_LOOPBACK_PMA_INT_WS 0x1e */
3530 /* MC_CMD_LOOPBACK_SD_FEP2_WS 0x1f */
3532 /* MC_CMD_LOOPBACK_SD_FEP1_5_WS 0x20 */
3534 /* MC_CMD_LOOPBACK_SD_FEP_WS 0x21 */
3536 /* MC_CMD_LOOPBACK_SD_FES_WS 0x22 */
3538 /* MC_CMD_LOOPBACK_AOE_INT_NEAR 0x23 */
3540 /* MC_CMD_LOOPBACK_DATA_WS 0x24 */
3544 /* MC_CMD_LOOPBACK_FORCE_EXT_LINK 0x25 */
3597 #define AN_TYPE_TYPE_OFST 0
3600 #define MC_CMD_AN_NONE 0x0
3602 #define MC_CMD_AN_CLAUSE28 0x1
3604 #define MC_CMD_AN_CLAUSE37 0x2
3608 #define MC_CMD_AN_CLAUSE73 0x3
3609 #define AN_TYPE_TYPE_LBN 0
3615 #define FEC_TYPE_TYPE_OFST 0
3618 #define MC_CMD_FEC_NONE 0x0
3620 #define MC_CMD_FEC_BASER 0x1
3622 #define MC_CMD_FEC_RS 0x2
3623 #define FEC_TYPE_TYPE_LBN 0
3628 * Read the unified MAC/PHY link state. Locks required: None Return code: 0,
3631 #define MC_CMD_GET_LINK 0x29
3637 #define MC_CMD_GET_LINK_IN_LEN 0
3644 #define MC_CMD_GET_LINK_OUT_CAP_OFST 0
3663 #define MC_CMD_GET_LINK_OUT_LINK_UP_LBN 0
3682 #define MC_CMD_MAC_FAULT_XGMII_LOCAL_LBN 0
3696 #define MC_CMD_GET_LINK_OUT_V2_CAP_OFST 0
3715 #define MC_CMD_GET_LINK_OUT_V2_LINK_UP_LBN 0
3734 /* MC_CMD_MAC_FAULT_XGMII_LOCAL_LBN 0 */
3745 * bits, if the PMD requires FEC. 0 if unknown (e.g. module unplugged). Equal
3763 #define MC_CMD_GET_LINK_OUT_V2_PMD_MDI_CONNECTED_LBN 0
3785 * code: 0, EINVAL, ETIME
3787 #define MC_CMD_SET_LINK 0x2a
3797 #define MC_CMD_SET_LINK_IN_CAP_OFST 0
3802 #define MC_CMD_SET_LINK_IN_LOWPOWER_LBN 0
3813 /* A loopback speed of "0" is supported, and means (choose any available
3820 #define MC_CMD_SET_LINK_OUT_LEN 0
3824 * Set identification LED state. Locks required: None. Return code: 0, EINVAL
3826 #define MC_CMD_SET_ID_LED 0x2b
3834 #define MC_CMD_SET_ID_LED_IN_STATE_OFST 0
3836 #define MC_CMD_LED_OFF 0x0 /* enum */
3837 #define MC_CMD_LED_ON 0x1 /* enum */
3838 #define MC_CMD_LED_DEFAULT 0x2 /* enum */
3841 #define MC_CMD_SET_ID_LED_OUT_LEN 0
3845 * Set MAC configuration. Locks required: None. Return code: 0, EINVAL
3847 #define MC_CMD_SET_MAC 0x2c
3857 #define MC_CMD_SET_MAC_IN_MTU_OFST 0
3867 #define MC_CMD_SET_MAC_IN_REJECT_UNCST_LBN 0
3874 #define MC_CMD_FCNTL_OFF 0x0
3876 #define MC_CMD_FCNTL_RESPOND 0x1
3878 #define MC_CMD_FCNTL_BIDIR 0x2
3880 #define MC_CMD_FCNTL_AUTO 0x3
3882 #define MC_CMD_FCNTL_QBB 0x4
3884 #define MC_CMD_FCNTL_GENERATE 0x5
3887 #define MC_CMD_SET_MAC_IN_FLAG_INCLUDE_FCS_LBN 0
3895 #define MC_CMD_SET_MAC_EXT_IN_MTU_OFST 0
3905 #define MC_CMD_SET_MAC_EXT_IN_REJECT_UNCST_LBN 0
3912 /* MC_CMD_FCNTL_OFF 0x0 */
3914 /* MC_CMD_FCNTL_RESPOND 0x1 */
3916 /* MC_CMD_FCNTL_BIDIR 0x2 */
3918 /* MC_CMD_FCNTL_AUTO 0x3 */
3920 /* MC_CMD_FCNTL_QBB 0x4 */
3922 /* MC_CMD_FCNTL_GENERATE 0x5 */
3925 #define MC_CMD_SET_MAC_EXT_IN_FLAG_INCLUDE_FCS_LBN 0
3934 #define MC_CMD_SET_MAC_EXT_IN_CFG_MTU_LBN 0
3946 #define MC_CMD_SET_MAC_OUT_LEN 0
3952 * to 0.
3954 #define MC_CMD_SET_MAC_V2_OUT_MTU_OFST 0
3961 * by a 32bit number. If the DMA_ADDR is 0, then no DMA is performed, and the
3962 * statistics may be read from the message response. If DMA_ADDR != 0, then the
3964 * Returns: 0, ETIME
3966 #define MC_CMD_PHY_STATS 0x2d
3974 #define MC_CMD_PHY_STATS_IN_DMA_ADDR_OFST 0
3976 #define MC_CMD_PHY_STATS_IN_DMA_ADDR_LO_OFST 0
3980 #define MC_CMD_PHY_STATS_OUT_DMA_LEN 0
3984 #define MC_CMD_PHY_STATS_OUT_NO_DMA_STATISTICS_OFST 0
3988 #define MC_CMD_OUI 0x0
3990 #define MC_CMD_PMA_PMD_LINK_UP 0x1
3992 #define MC_CMD_PMA_PMD_RX_FAULT 0x2
3994 #define MC_CMD_PMA_PMD_TX_FAULT 0x3
3996 #define MC_CMD_PMA_PMD_SIGNAL 0x4
3998 #define MC_CMD_PMA_PMD_SNR_A 0x5
4000 #define MC_CMD_PMA_PMD_SNR_B 0x6
4002 #define MC_CMD_PMA_PMD_SNR_C 0x7
4004 #define MC_CMD_PMA_PMD_SNR_D 0x8
4006 #define MC_CMD_PCS_LINK_UP 0x9
4008 #define MC_CMD_PCS_RX_FAULT 0xa
4010 #define MC_CMD_PCS_TX_FAULT 0xb
4012 #define MC_CMD_PCS_BER 0xc
4014 #define MC_CMD_PCS_BLOCK_ERRORS 0xd
4016 #define MC_CMD_PHYXS_LINK_UP 0xe
4018 #define MC_CMD_PHYXS_RX_FAULT 0xf
4020 #define MC_CMD_PHYXS_TX_FAULT 0x10
4022 #define MC_CMD_PHYXS_ALIGN 0x11
4024 #define MC_CMD_PHYXS_SYNC 0x12
4026 #define MC_CMD_AN_LINK_UP 0x13
4028 #define MC_CMD_AN_COMPLETE 0x14
4030 #define MC_CMD_AN_10GBT_STATUS 0x15
4032 #define MC_CMD_CL22_LINK_UP 0x16
4034 #define MC_CMD_PHY_NSTATS 0x17
4041 * guarantee consistent results. If the DMA_ADDR is 0, then no DMA is
4043 * DMA_ADDR != 0, then the statistics are dmad to that (page-aligned location).
4045 * effect. Returns: 0, ETIME
4047 #define MC_CMD_MAC_STATS 0x2e
4055 #define MC_CMD_MAC_STATS_IN_DMA_ADDR_OFST 0
4057 #define MC_CMD_MAC_STATS_IN_DMA_ADDR_LO_OFST 0
4061 #define MC_CMD_MAC_STATS_IN_DMA_LBN 0
4087 #define MC_CMD_MAC_STATS_OUT_DMA_LEN 0
4091 #define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_OFST 0
4093 #define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_LO_OFST 0
4096 #define MC_CMD_MAC_GENERATION_START 0x0 /* enum */
4097 #define MC_CMD_MAC_DMABUF_START 0x1 /* enum */
4098 #define MC_CMD_MAC_TX_PKTS 0x1 /* enum */
4099 #define MC_CMD_MAC_TX_PAUSE_PKTS 0x2 /* enum */
4100 #define MC_CMD_MAC_TX_CONTROL_PKTS 0x3 /* enum */
4101 #define MC_CMD_MAC_TX_UNICAST_PKTS 0x4 /* enum */
4102 #define MC_CMD_MAC_TX_MULTICAST_PKTS 0x5 /* enum */
4103 #define MC_CMD_MAC_TX_BROADCAST_PKTS 0x6 /* enum */
4104 #define MC_CMD_MAC_TX_BYTES 0x7 /* enum */
4105 #define MC_CMD_MAC_TX_BAD_BYTES 0x8 /* enum */
4106 #define MC_CMD_MAC_TX_LT64_PKTS 0x9 /* enum */
4107 #define MC_CMD_MAC_TX_64_PKTS 0xa /* enum */
4108 #define MC_CMD_MAC_TX_65_TO_127_PKTS 0xb /* enum */
4109 #define MC_CMD_MAC_TX_128_TO_255_PKTS 0xc /* enum */
4110 #define MC_CMD_MAC_TX_256_TO_511_PKTS 0xd /* enum */
4111 #define MC_CMD_MAC_TX_512_TO_1023_PKTS 0xe /* enum */
4112 #define MC_CMD_MAC_TX_1024_TO_15XX_PKTS 0xf /* enum */
4113 #define MC_CMD_MAC_TX_15XX_TO_JUMBO_PKTS 0x10 /* enum */
4114 #define MC_CMD_MAC_TX_GTJUMBO_PKTS 0x11 /* enum */
4115 #define MC_CMD_MAC_TX_BAD_FCS_PKTS 0x12 /* enum */
4116 #define MC_CMD_MAC_TX_SINGLE_COLLISION_PKTS 0x13 /* enum */
4117 #define MC_CMD_MAC_TX_MULTIPLE_COLLISION_PKTS 0x14 /* enum */
4118 #define MC_CMD_MAC_TX_EXCESSIVE_COLLISION_PKTS 0x15 /* enum */
4119 #define MC_CMD_MAC_TX_LATE_COLLISION_PKTS 0x16 /* enum */
4120 #define MC_CMD_MAC_TX_DEFERRED_PKTS 0x17 /* enum */
4121 #define MC_CMD_MAC_TX_EXCESSIVE_DEFERRED_PKTS 0x18 /* enum */
4122 #define MC_CMD_MAC_TX_NON_TCPUDP_PKTS 0x19 /* enum */
4123 #define MC_CMD_MAC_TX_MAC_SRC_ERR_PKTS 0x1a /* enum */
4124 #define MC_CMD_MAC_TX_IP_SRC_ERR_PKTS 0x1b /* enum */
4125 #define MC_CMD_MAC_RX_PKTS 0x1c /* enum */
4126 #define MC_CMD_MAC_RX_PAUSE_PKTS 0x1d /* enum */
4127 #define MC_CMD_MAC_RX_GOOD_PKTS 0x1e /* enum */
4128 #define MC_CMD_MAC_RX_CONTROL_PKTS 0x1f /* enum */
4129 #define MC_CMD_MAC_RX_UNICAST_PKTS 0x20 /* enum */
4130 #define MC_CMD_MAC_RX_MULTICAST_PKTS 0x21 /* enum */
4131 #define MC_CMD_MAC_RX_BROADCAST_PKTS 0x22 /* enum */
4132 #define MC_CMD_MAC_RX_BYTES 0x23 /* enum */
4133 #define MC_CMD_MAC_RX_BAD_BYTES 0x24 /* enum */
4134 #define MC_CMD_MAC_RX_64_PKTS 0x25 /* enum */
4135 #define MC_CMD_MAC_RX_65_TO_127_PKTS 0x26 /* enum */
4136 #define MC_CMD_MAC_RX_128_TO_255_PKTS 0x27 /* enum */
4137 #define MC_CMD_MAC_RX_256_TO_511_PKTS 0x28 /* enum */
4138 #define MC_CMD_MAC_RX_512_TO_1023_PKTS 0x29 /* enum */
4139 #define MC_CMD_MAC_RX_1024_TO_15XX_PKTS 0x2a /* enum */
4140 #define MC_CMD_MAC_RX_15XX_TO_JUMBO_PKTS 0x2b /* enum */
4141 #define MC_CMD_MAC_RX_GTJUMBO_PKTS 0x2c /* enum */
4142 #define MC_CMD_MAC_RX_UNDERSIZE_PKTS 0x2d /* enum */
4143 #define MC_CMD_MAC_RX_BAD_FCS_PKTS 0x2e /* enum */
4144 #define MC_CMD_MAC_RX_OVERFLOW_PKTS 0x2f /* enum */
4145 #define MC_CMD_MAC_RX_FALSE_CARRIER_PKTS 0x30 /* enum */
4146 #define MC_CMD_MAC_RX_SYMBOL_ERROR_PKTS 0x31 /* enum */
4147 #define MC_CMD_MAC_RX_ALIGN_ERROR_PKTS 0x32 /* enum */
4148 #define MC_CMD_MAC_RX_LENGTH_ERROR_PKTS 0x33 /* enum */
4149 #define MC_CMD_MAC_RX_INTERNAL_ERROR_PKTS 0x34 /* enum */
4150 #define MC_CMD_MAC_RX_JABBER_PKTS 0x35 /* enum */
4151 #define MC_CMD_MAC_RX_NODESC_DROPS 0x36 /* enum */
4152 #define MC_CMD_MAC_RX_LANES01_CHAR_ERR 0x37 /* enum */
4153 #define MC_CMD_MAC_RX_LANES23_CHAR_ERR 0x38 /* enum */
4154 #define MC_CMD_MAC_RX_LANES01_DISP_ERR 0x39 /* enum */
4155 #define MC_CMD_MAC_RX_LANES23_DISP_ERR 0x3a /* enum */
4156 #define MC_CMD_MAC_RX_MATCH_FAULT 0x3b /* enum */
4160 #define MC_CMD_MAC_PM_TRUNC_BB_OVERFLOW 0x3c
4164 #define MC_CMD_MAC_PM_DISCARD_BB_OVERFLOW 0x3d
4168 #define MC_CMD_MAC_PM_TRUNC_VFIFO_FULL 0x3e
4172 #define MC_CMD_MAC_PM_DISCARD_VFIFO_FULL 0x3f
4176 #define MC_CMD_MAC_PM_TRUNC_QBB 0x40
4180 #define MC_CMD_MAC_PM_DISCARD_QBB 0x41
4184 #define MC_CMD_MAC_PM_DISCARD_MAPPING 0x42
4188 #define MC_CMD_MAC_RXDP_Q_DISABLED_PKTS 0x43
4192 #define MC_CMD_MAC_RXDP_DI_DROPPED_PKTS 0x45
4196 #define MC_CMD_MAC_RXDP_STREAMING_PKTS 0x46
4200 #define MC_CMD_MAC_RXDP_HLB_FETCH_CONDITIONS 0x47
4204 #define MC_CMD_MAC_RXDP_HLB_WAIT_CONDITIONS 0x48
4205 #define MC_CMD_MAC_VADAPTER_RX_DMABUF_START 0x4c /* enum */
4206 #define MC_CMD_MAC_VADAPTER_RX_UNICAST_PACKETS 0x4c /* enum */
4207 #define MC_CMD_MAC_VADAPTER_RX_UNICAST_BYTES 0x4d /* enum */
4208 #define MC_CMD_MAC_VADAPTER_RX_MULTICAST_PACKETS 0x4e /* enum */
4209 #define MC_CMD_MAC_VADAPTER_RX_MULTICAST_BYTES 0x4f /* enum */
4210 #define MC_CMD_MAC_VADAPTER_RX_BROADCAST_PACKETS 0x50 /* enum */
4211 #define MC_CMD_MAC_VADAPTER_RX_BROADCAST_BYTES 0x51 /* enum */
4212 #define MC_CMD_MAC_VADAPTER_RX_BAD_PACKETS 0x52 /* enum */
4213 #define MC_CMD_MAC_VADAPTER_RX_BAD_BYTES 0x53 /* enum */
4214 #define MC_CMD_MAC_VADAPTER_RX_OVERFLOW 0x54 /* enum */
4215 #define MC_CMD_MAC_VADAPTER_TX_DMABUF_START 0x57 /* enum */
4216 #define MC_CMD_MAC_VADAPTER_TX_UNICAST_PACKETS 0x57 /* enum */
4217 #define MC_CMD_MAC_VADAPTER_TX_UNICAST_BYTES 0x58 /* enum */
4218 #define MC_CMD_MAC_VADAPTER_TX_MULTICAST_PACKETS 0x59 /* enum */
4219 #define MC_CMD_MAC_VADAPTER_TX_MULTICAST_BYTES 0x5a /* enum */
4220 #define MC_CMD_MAC_VADAPTER_TX_BROADCAST_PACKETS 0x5b /* enum */
4221 #define MC_CMD_MAC_VADAPTER_TX_BROADCAST_BYTES 0x5c /* enum */
4222 #define MC_CMD_MAC_VADAPTER_TX_BAD_PACKETS 0x5d /* enum */
4223 #define MC_CMD_MAC_VADAPTER_TX_BAD_BYTES 0x5e /* enum */
4224 #define MC_CMD_MAC_VADAPTER_TX_OVERFLOW 0x5f /* enum */
4226 #define MC_CMD_GMAC_DMABUF_START 0x40
4228 #define MC_CMD_GMAC_DMABUF_END 0x5f
4239 #define MC_CMD_MAC_GENERATION_END 0x60
4240 #define MC_CMD_MAC_NSTATS 0x61 /* enum */
4243 #define MC_CMD_MAC_STATS_V2_OUT_DMA_LEN 0
4247 #define MC_CMD_MAC_STATS_V2_OUT_NO_DMA_STATISTICS_OFST 0
4249 #define MC_CMD_MAC_STATS_V2_OUT_NO_DMA_STATISTICS_LO_OFST 0
4253 #define MC_CMD_MAC_FEC_DMABUF_START 0x61
4256 #define MC_CMD_MAC_FEC_UNCORRECTED_ERRORS 0x61
4259 #define MC_CMD_MAC_FEC_CORRECTED_ERRORS 0x62
4260 /* enum: Number of corrected 10-bit symbol errors, lane 0 (RS-FEC only) */
4261 #define MC_CMD_MAC_FEC_CORRECTED_SYMBOLS_LANE0 0x63
4263 #define MC_CMD_MAC_FEC_CORRECTED_SYMBOLS_LANE1 0x64
4265 #define MC_CMD_MAC_FEC_CORRECTED_SYMBOLS_LANE2 0x65
4267 #define MC_CMD_MAC_FEC_CORRECTED_SYMBOLS_LANE3 0x66
4271 #define MC_CMD_MAC_NSTATS_V2 0x68
4276 #define MC_CMD_MAC_STATS_V3_OUT_DMA_LEN 0
4280 #define MC_CMD_MAC_STATS_V3_OUT_NO_DMA_STATISTICS_OFST 0
4282 #define MC_CMD_MAC_STATS_V3_OUT_NO_DMA_STATISTICS_LO_OFST 0
4286 #define MC_CMD_MAC_CTPIO_DMABUF_START 0x68
4290 #define MC_CMD_MAC_CTPIO_VI_BUSY_FALLBACK 0x68
4294 #define MC_CMD_MAC_CTPIO_LONG_WRITE_SUCCESS 0x69
4298 #define MC_CMD_MAC_CTPIO_MISSING_DBELL_FAIL 0x6a
4300 #define MC_CMD_MAC_CTPIO_OVERFLOW_FAIL 0x6b
4304 #define MC_CMD_MAC_CTPIO_UNDERFLOW_FAIL 0x6c
4308 #define MC_CMD_MAC_CTPIO_TIMEOUT_FAIL 0x6d
4312 #define MC_CMD_MAC_CTPIO_NONCONTIG_WR_FAIL 0x6e
4316 #define MC_CMD_MAC_CTPIO_FRM_CLOBBER_FAIL 0x6f
4320 #define MC_CMD_MAC_CTPIO_INVALID_WR_FAIL 0x70
4324 #define MC_CMD_MAC_CTPIO_VI_CLOBBER_FALLBACK 0x71
4327 #define MC_CMD_MAC_CTPIO_UNQUALIFIED_FALLBACK 0x72
4331 #define MC_CMD_MAC_CTPIO_RUNT_FALLBACK 0x73
4333 #define MC_CMD_MAC_CTPIO_SUCCESS 0x74
4335 #define MC_CMD_MAC_CTPIO_FALLBACK 0x75
4339 #define MC_CMD_MAC_CTPIO_POISON 0x76
4341 #define MC_CMD_MAC_CTPIO_ERASE 0x77
4345 #define MC_CMD_MAC_NSTATS_V3 0x79
4350 #define MC_CMD_MAC_STATS_V4_OUT_DMA_LEN 0
4354 #define MC_CMD_MAC_STATS_V4_OUT_NO_DMA_STATISTICS_OFST 0
4356 #define MC_CMD_MAC_STATS_V4_OUT_NO_DMA_STATISTICS_LO_OFST 0
4360 #define MC_CMD_MAC_V4_DMABUF_START 0x79
4364 #define MC_CMD_MAC_RXDP_SCATTER_DISABLED_TRUNC 0x79
4368 #define MC_CMD_MAC_RXDP_HLB_IDLE 0x7a
4372 #define MC_CMD_MAC_RXDP_HLB_TIMEOUT 0x7b
4376 #define MC_CMD_MAC_NSTATS_V4 0x7d
4384 #define MC_CMD_SRIOV 0x30
4388 #define MC_CMD_SRIOV_IN_ENABLE_OFST 0
4397 #define MC_CMD_SRIOV_OUT_VI_SCALE_OFST 0
4405 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_NUM_RECORDS_OFST 0
4407 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_NUM_RECORDS_LBN 0
4421 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_RID_INLINE 0x100 /* enum */
4448 * indicate this, the client sets FROM_RID=%RID_INLINE, ADDR_HI=0, and
4453 * Returns: 0, EINVAL (invalid RID)
4455 #define MC_CMD_MEMCPY 0x31
4460 #define MC_CMD_MEMCPY_IN_LEN(num) (0+32*(num))
4462 #define MC_CMD_MEMCPY_IN_RECORD_OFST 0
4468 #define MC_CMD_MEMCPY_OUT_LEN 0
4474 #define MC_CMD_WOL_FILTER_SET 0x32
4481 #define MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0
4483 #define MC_CMD_FILTER_MODE_SIMPLE 0x0 /* enum */
4484 #define MC_CMD_FILTER_MODE_STRUCTURED 0xffffffff /* enum */
4489 #define MC_CMD_WOL_TYPE_MAGIC 0x0
4491 #define MC_CMD_WOL_TYPE_WIN_MAGIC 0x2
4493 #define MC_CMD_WOL_TYPE_IPV4_SYN 0x3
4495 #define MC_CMD_WOL_TYPE_IPV6_SYN 0x4
4497 #define MC_CMD_WOL_TYPE_BITMAP 0x5
4499 #define MC_CMD_WOL_TYPE_LINK 0x6
4501 #define MC_CMD_WOL_TYPE_MAX 0x7
4508 /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */
4519 /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */
4534 /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */
4549 /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */
4566 /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */
4572 #define MC_CMD_WOL_FILTER_SET_IN_LINK_UP_LBN 0
4579 #define MC_CMD_WOL_FILTER_SET_OUT_FILTER_ID_OFST 0
4584 * Remove a WoL filter. Locks required: None. Returns: 0, EINVAL, ENOSYS
4586 #define MC_CMD_WOL_FILTER_REMOVE 0x33
4593 #define MC_CMD_WOL_FILTER_REMOVE_IN_FILTER_ID_OFST 0
4597 #define MC_CMD_WOL_FILTER_REMOVE_OUT_LEN 0
4601 * Reset (i.e. remove all) WoL filters. Locks required: None. Returns: 0,
4604 #define MC_CMD_WOL_FILTER_RESET 0x34
4611 #define MC_CMD_WOL_FILTER_RESET_IN_MASK_OFST 0
4613 #define MC_CMD_WOL_FILTER_RESET_IN_WAKE_FILTERS 0x1 /* enum */
4614 #define MC_CMD_WOL_FILTER_RESET_IN_LIGHTSOUT_OFFLOADS 0x2 /* enum */
4617 #define MC_CMD_WOL_FILTER_RESET_OUT_LEN 0
4623 #define MC_CMD_SET_MCAST_HASH 0x35
4627 #define MC_CMD_SET_MCAST_HASH_IN_HASH0_OFST 0
4633 #define MC_CMD_SET_MCAST_HASH_OUT_LEN 0
4638 * Locks required: none. Returns: 0
4640 #define MC_CMD_NVRAM_TYPES 0x36
4646 #define MC_CMD_NVRAM_TYPES_IN_LEN 0
4651 #define MC_CMD_NVRAM_TYPES_OUT_TYPES_OFST 0
4654 #define MC_CMD_NVRAM_TYPE_DISABLED_CALLISTO 0x0
4656 #define MC_CMD_NVRAM_TYPE_MC_FW 0x1
4658 #define MC_CMD_NVRAM_TYPE_MC_FW_BACKUP 0x2
4660 #define MC_CMD_NVRAM_TYPE_STATIC_CFG_PORT0 0x3
4662 #define MC_CMD_NVRAM_TYPE_STATIC_CFG_PORT1 0x4
4664 #define MC_CMD_NVRAM_TYPE_DYNAMIC_CFG_PORT0 0x5
4666 #define MC_CMD_NVRAM_TYPE_DYNAMIC_CFG_PORT1 0x6
4668 #define MC_CMD_NVRAM_TYPE_EXP_ROM 0x7
4670 #define MC_CMD_NVRAM_TYPE_EXP_ROM_CFG_PORT0 0x8
4672 #define MC_CMD_NVRAM_TYPE_EXP_ROM_CFG_PORT1 0x9
4674 #define MC_CMD_NVRAM_TYPE_PHY_PORT0 0xa
4676 #define MC_CMD_NVRAM_TYPE_PHY_PORT1 0xb
4678 #define MC_CMD_NVRAM_TYPE_LOG 0xc
4680 #define MC_CMD_NVRAM_TYPE_FPGA 0xd
4682 #define MC_CMD_NVRAM_TYPE_FPGA_BACKUP 0xe
4684 #define MC_CMD_NVRAM_TYPE_FC_FW 0xf
4686 #define MC_CMD_NVRAM_TYPE_FC_FW_BACKUP 0x10
4688 #define MC_CMD_NVRAM_TYPE_CPLD 0x11
4690 #define MC_CMD_NVRAM_TYPE_LICENSE 0x12
4692 #define MC_CMD_NVRAM_TYPE_FC_LOG 0x13
4694 #define MC_CMD_NVRAM_TYPE_FC_EXTRA 0x14
4698 * Read info about a virtual NVRAM partition. Locks required: none. Returns: 0,
4701 #define MC_CMD_NVRAM_INFO 0x37
4708 #define MC_CMD_NVRAM_INFO_IN_TYPE_OFST 0
4715 #define MC_CMD_NVRAM_INFO_OUT_TYPE_OFST 0
4725 #define MC_CMD_NVRAM_INFO_OUT_PROTECTED_LBN 0
4744 #define MC_CMD_NVRAM_INFO_V2_OUT_TYPE_OFST 0
4754 #define MC_CMD_NVRAM_INFO_V2_OUT_PROTECTED_LBN 0
4776 * required: PHY_LOCK if type==*PHY*. Returns: 0, EINVAL (bad type), EACCES (if
4783 #define MC_CMD_NVRAM_UPDATE_START 0x38
4792 #define MC_CMD_NVRAM_UPDATE_START_IN_TYPE_OFST 0
4803 #define MC_CMD_NVRAM_UPDATE_START_V2_IN_TYPE_OFST 0
4809 #define MC_CMD_NVRAM_UPDATE_START_V2_IN_FLAG_REPORT_VERIFY_RESULT_LBN 0
4813 #define MC_CMD_NVRAM_UPDATE_START_OUT_LEN 0
4818 * type==*PHY*. Returns: 0, EINVAL (bad type/offset/length), EACCES (if
4821 #define MC_CMD_NVRAM_READ 0x39
4828 #define MC_CMD_NVRAM_READ_IN_TYPE_OFST 0
4840 #define MC_CMD_NVRAM_READ_IN_V2_TYPE_OFST 0
4863 #define MC_CMD_NVRAM_READ_IN_V2_DEFAULT 0x0
4867 #define MC_CMD_NVRAM_READ_IN_V2_TARGET_CURRENT 0x1
4871 #define MC_CMD_NVRAM_READ_IN_V2_TARGET_BACKUP 0x2
4876 #define MC_CMD_NVRAM_READ_OUT_LEN(num) (0+1*(num))
4877 #define MC_CMD_NVRAM_READ_OUT_READ_BUFFER_OFST 0
4885 * type==*PHY*. Returns: 0, EINVAL (bad type/offset/length), EACCES (if
4888 #define MC_CMD_NVRAM_WRITE 0x3a
4897 #define MC_CMD_NVRAM_WRITE_IN_TYPE_OFST 0
4911 #define MC_CMD_NVRAM_WRITE_OUT_LEN 0
4916 * type==*PHY*. Returns: 0, EINVAL (bad type/offset/length), EACCES (if
4919 #define MC_CMD_NVRAM_ERASE 0x3b
4926 #define MC_CMD_NVRAM_ERASE_IN_TYPE_OFST 0
4936 #define MC_CMD_NVRAM_ERASE_OUT_LEN 0
4941 * required: PHY_LOCK if type==*PHY*. Returns: 0, EINVAL (bad type/offset/
4948 #define MC_CMD_NVRAM_UPDATE_FINISH 0x3c
4957 #define MC_CMD_NVRAM_UPDATE_FINISH_IN_TYPE_OFST 0
4970 #define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_TYPE_OFST 0
4978 #define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAG_REPORT_VERIFY_RESULT_LBN 0
4984 #define MC_CMD_NVRAM_UPDATE_FINISH_OUT_LEN 0
5003 #define MC_CMD_NVRAM_UPDATE_FINISH_V2_OUT_RESULT_CODE_OFST 0
5008 #define MC_CMD_NVRAM_VERIFY_RC_UNKNOWN 0x0
5010 #define MC_CMD_NVRAM_VERIFY_RC_SUCCESS 0x1
5012 #define MC_CMD_NVRAM_VERIFY_RC_CMS_CHECK_FAILED 0x2
5014 #define MC_CMD_NVRAM_VERIFY_RC_INVALID_CMS_FORMAT 0x3
5016 #define MC_CMD_NVRAM_VERIFY_RC_MESSAGE_DIGEST_CHECK_FAILED 0x4
5020 #define MC_CMD_NVRAM_VERIFY_RC_BAD_MESSAGE_DIGEST 0x5
5022 #define MC_CMD_NVRAM_VERIFY_RC_SIGNATURE_CHECK_FAILED 0x6
5024 #define MC_CMD_NVRAM_VERIFY_RC_NO_VALID_SIGNATURES 0x7
5026 #define MC_CMD_NVRAM_VERIFY_RC_TRUSTED_APPROVERS_CHECK_FAILED 0x8
5028 #define MC_CMD_NVRAM_VERIFY_RC_NO_TRUSTED_APPROVERS 0x9
5030 #define MC_CMD_NVRAM_VERIFY_RC_SIGNATURE_CHAIN_CHECK_FAILED 0xa
5034 #define MC_CMD_NVRAM_VERIFY_RC_NO_SIGNATURE_MATCH 0xb
5038 #define MC_CMD_NVRAM_VERIFY_RC_REJECT_TEST_SIGNED 0xc
5040 #define MC_CMD_NVRAM_VERIFY_RC_SECURITY_LEVEL_DOWNGRADE 0xd
5055 * REBOOT_ON_ASSERT=0.
5058 * DATALEN=0
5060 #define MC_CMD_REBOOT 0x3d
5067 #define MC_CMD_REBOOT_IN_FLAGS_OFST 0
5069 #define MC_CMD_REBOOT_FLAGS_AFTER_ASSERTION 0x1 /* enum */
5072 #define MC_CMD_REBOOT_OUT_LEN 0
5080 #define MC_CMD_SCHEDINFO 0x3e
5086 #define MC_CMD_SCHEDINFO_IN_LEN 0
5091 #define MC_CMD_SCHEDINFO_OUT_LEN(num) (0+4*(num))
5092 #define MC_CMD_SCHEDINFO_OUT_DATA_OFST 0
5102 #define MC_CMD_REBOOT_MODE 0x3f
5109 #define MC_CMD_REBOOT_MODE_IN_VALUE_OFST 0
5112 #define MC_CMD_REBOOT_MODE_NORMAL 0x0
5114 #define MC_CMD_REBOOT_MODE_POR 0x2
5116 #define MC_CMD_REBOOT_MODE_SNAPPER 0x3
5118 #define MC_CMD_REBOOT_MODE_SNAPPER_POR 0x4
5124 #define MC_CMD_REBOOT_MODE_OUT_VALUE_OFST 0
5145 * backward compatibility, older host software can only use sensors in page 0.
5150 * page 0 of sensor information, with bit 31 in the sensor mask cleared.
5156 * Locks required: None Returns: 0
5158 #define MC_CMD_SENSOR_INFO 0x41
5164 #define MC_CMD_SENSOR_INFO_IN_LEN 0
5170 * Page 0 contains sensors 0 to 30 (sensor 31 is the next page bit).
5174 #define MC_CMD_SENSOR_INFO_EXT_IN_PAGE_OFST 0
5181 #define MC_CMD_SENSOR_INFO_OUT_MASK_OFST 0
5184 #define MC_CMD_SENSOR_CONTROLLER_TEMP 0x0
5186 #define MC_CMD_SENSOR_PHY_COMMON_TEMP 0x1
5188 #define MC_CMD_SENSOR_CONTROLLER_COOLING 0x2
5189 /* enum: Phy 0 temperature: degC */
5190 #define MC_CMD_SENSOR_PHY0_TEMP 0x3
5191 /* enum: Phy 0 cooling: bool */
5192 #define MC_CMD_SENSOR_PHY0_COOLING 0x4
5194 #define MC_CMD_SENSOR_PHY1_TEMP 0x5
5196 #define MC_CMD_SENSOR_PHY1_COOLING 0x6
5198 #define MC_CMD_SENSOR_IN_1V0 0x7
5200 #define MC_CMD_SENSOR_IN_1V2 0x8
5202 #define MC_CMD_SENSOR_IN_1V8 0x9
5204 #define MC_CMD_SENSOR_IN_2V5 0xa
5206 #define MC_CMD_SENSOR_IN_3V3 0xb
5208 #define MC_CMD_SENSOR_IN_12V0 0xc
5210 #define MC_CMD_SENSOR_IN_1V2A 0xd
5212 #define MC_CMD_SENSOR_IN_VREF 0xe
5214 #define MC_CMD_SENSOR_OUT_VAOE 0xf
5216 #define MC_CMD_SENSOR_AOE_TEMP 0x10
5218 #define MC_CMD_SENSOR_PSU_AOE_TEMP 0x11
5220 #define MC_CMD_SENSOR_PSU_TEMP 0x12
5221 /* enum: Fan 0 speed: RPM */
5222 #define MC_CMD_SENSOR_FAN_0 0x13
5224 #define MC_CMD_SENSOR_FAN_1 0x14
5226 #define MC_CMD_SENSOR_FAN_2 0x15
5228 #define MC_CMD_SENSOR_FAN_3 0x16
5230 #define MC_CMD_SENSOR_FAN_4 0x17
5232 #define MC_CMD_SENSOR_IN_VAOE 0x18
5234 #define MC_CMD_SENSOR_OUT_IAOE 0x19
5236 #define MC_CMD_SENSOR_IN_IAOE 0x1a
5238 #define MC_CMD_SENSOR_NIC_POWER 0x1b
5240 #define MC_CMD_SENSOR_IN_0V9 0x1c
5242 #define MC_CMD_SENSOR_IN_I0V9 0x1d
5244 #define MC_CMD_SENSOR_IN_I1V2 0x1e
5246 #define MC_CMD_SENSOR_PAGE0_NEXT 0x1f
5248 #define MC_CMD_SENSOR_IN_0V9_ADC 0x20
5250 #define MC_CMD_SENSOR_CONTROLLER_2_TEMP 0x21
5252 #define MC_CMD_SENSOR_VREG_INTERNAL_TEMP 0x22
5254 #define MC_CMD_SENSOR_VREG_0V9_TEMP 0x23
5256 #define MC_CMD_SENSOR_VREG_1V2_TEMP 0x24
5258 #define MC_CMD_SENSOR_CONTROLLER_VPTAT 0x25
5260 #define MC_CMD_SENSOR_CONTROLLER_INTERNAL_TEMP 0x26
5262 #define MC_CMD_SENSOR_CONTROLLER_VPTAT_EXTADC 0x27
5264 #define MC_CMD_SENSOR_CONTROLLER_INTERNAL_TEMP_EXTADC 0x28
5266 #define MC_CMD_SENSOR_AMBIENT_TEMP 0x29
5268 #define MC_CMD_SENSOR_AIRFLOW 0x2a
5270 #define MC_CMD_SENSOR_VDD08D_VSS08D_CSR 0x2b
5272 #define MC_CMD_SENSOR_VDD08D_VSS08D_CSR_EXTADC 0x2c
5274 #define MC_CMD_SENSOR_HOTPOINT_TEMP 0x2d
5275 /* enum: Port 0 PHY power switch over-current: bool */
5276 #define MC_CMD_SENSOR_PHY_POWER_PORT0 0x2e
5278 #define MC_CMD_SENSOR_PHY_POWER_PORT1 0x2f
5280 #define MC_CMD_SENSOR_MUM_VCC 0x30
5282 #define MC_CMD_SENSOR_IN_0V9_A 0x31
5284 #define MC_CMD_SENSOR_IN_I0V9_A 0x32
5286 #define MC_CMD_SENSOR_VREG_0V9_A_TEMP 0x33
5288 #define MC_CMD_SENSOR_IN_0V9_B 0x34
5290 #define MC_CMD_SENSOR_IN_I0V9_B 0x35
5292 #define MC_CMD_SENSOR_VREG_0V9_B_TEMP 0x36
5294 #define MC_CMD_SENSOR_CCOM_AVREG_1V2_SUPPLY 0x37
5296 #define MC_CMD_SENSOR_CCOM_AVREG_1V2_SUPPLY_EXTADC 0x38
5298 #define MC_CMD_SENSOR_CCOM_AVREG_1V8_SUPPLY 0x39
5300 #define MC_CMD_SENSOR_CCOM_AVREG_1V8_SUPPLY_EXTADC 0x3a
5302 #define MC_CMD_SENSOR_CONTROLLER_RTS 0x3b
5304 #define MC_CMD_SENSOR_PAGE1_NEXT 0x3f
5308 #define MC_CMD_SENSOR_CONTROLLER_MASTER_VPTAT 0x40
5310 #define MC_CMD_SENSOR_CONTROLLER_MASTER_INTERNAL_TEMP 0x41
5314 #define MC_CMD_SENSOR_CONTROLLER_MASTER_VPTAT_EXTADC 0x42
5316 #define MC_CMD_SENSOR_CONTROLLER_MASTER_INTERNAL_TEMP_EXTADC 0x43
5320 #define MC_CMD_SENSOR_CONTROLLER_SLAVE_VPTAT 0x44
5322 #define MC_CMD_SENSOR_CONTROLLER_SLAVE_INTERNAL_TEMP 0x45
5326 #define MC_CMD_SENSOR_CONTROLLER_SLAVE_VPTAT_EXTADC 0x46
5328 #define MC_CMD_SENSOR_CONTROLLER_SLAVE_INTERNAL_TEMP_EXTADC 0x47
5330 #define MC_CMD_SENSOR_SODIMM_VOUT 0x49
5331 /* enum: Temperature of SODIMM 0 (if installed): degC */
5332 #define MC_CMD_SENSOR_SODIMM_0_TEMP 0x4a
5334 #define MC_CMD_SENSOR_SODIMM_1_TEMP 0x4b
5335 /* enum: Voltage supplied to the QSFP #0 from their power supply: mV */
5336 #define MC_CMD_SENSOR_PHY0_VCC 0x4c
5338 #define MC_CMD_SENSOR_PHY1_VCC 0x4d
5340 #define MC_CMD_SENSOR_CONTROLLER_TDIODE_TEMP 0x4e
5342 #define MC_CMD_SENSOR_BOARD_FRONT_TEMP 0x4f
5344 #define MC_CMD_SENSOR_BOARD_BACK_TEMP 0x50
5346 #define MC_CMD_SENSOR_IN_I1V8 0x51
5348 #define MC_CMD_SENSOR_IN_I2V5 0x52
5350 #define MC_CMD_SENSOR_IN_I3V3 0x53
5352 #define MC_CMD_SENSOR_IN_I12V0 0x54
5354 #define MC_CMD_SENSOR_IN_1V3 0x55
5356 #define MC_CMD_SENSOR_IN_I1V3 0x56
5358 #define MC_CMD_SENSOR_PAGE2_NEXT 0x5f
5364 #define MC_CMD_SENSOR_ENTRY_MINNUM 0
5371 #define MC_CMD_SENSOR_INFO_EXT_OUT_MASK_OFST 0
5382 /* MC_CMD_SENSOR_ENTRY_MINNUM 0 */
5387 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN1_OFST 0
5389 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN1_LBN 0
5411 * If the request does not contain the LENGTH field then only sensors 0 to 30
5421 #define MC_CMD_READ_SENSORS 0x42
5429 #define MC_CMD_READ_SENSORS_IN_DMA_ADDR_OFST 0
5431 #define MC_CMD_READ_SENSORS_IN_DMA_ADDR_LO_OFST 0
5437 #define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_OFST 0
5439 #define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_LO_OFST 0
5446 #define MC_CMD_READ_SENSORS_OUT_LEN 0
5449 #define MC_CMD_READ_SENSORS_EXT_OUT_LEN 0
5453 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_VALUE_OFST 0
5455 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_VALUE_LBN 0
5460 #define MC_CMD_SENSOR_STATE_OK 0x0
5462 #define MC_CMD_SENSOR_STATE_WARNING 0x1
5464 #define MC_CMD_SENSOR_STATE_FATAL 0x2
5466 #define MC_CMD_SENSOR_STATE_BROKEN 0x3
5468 #define MC_CMD_SENSOR_STATE_NO_READING 0x4
5470 #define MC_CMD_SENSOR_STATE_INIT_FAILED 0x5
5484 * code: 0
5486 #define MC_CMD_GET_PHY_STATE 0x43
5492 #define MC_CMD_GET_PHY_STATE_IN_LEN 0
5496 #define MC_CMD_GET_PHY_STATE_OUT_STATE_OFST 0
5499 #define MC_CMD_PHY_STATE_OK 0x1
5501 #define MC_CMD_PHY_STATE_ZOMBIE 0x2
5505 * 802.1Qbb control. 8 Tx queues that map to priorities 0 - 7. Use all 1s to
5508 #define MC_CMD_SETUP_8021QBB 0x44
5512 #define MC_CMD_SETUP_8021QBB_IN_TXQS_OFST 0
5516 #define MC_CMD_SETUP_8021QBB_OUT_LEN 0
5520 * Retrieve ID of any WoL filters. Locks required: None. Returns: 0, ENOSYS
5522 #define MC_CMD_WOL_FILTER_GET 0x45
5528 #define MC_CMD_WOL_FILTER_GET_IN_LEN 0
5532 #define MC_CMD_WOL_FILTER_GET_OUT_FILTER_ID_OFST 0
5538 * Returns: 0, ENOSYS
5540 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD 0x46
5549 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_OFST 0
5551 #define MC_CMD_LIGHTSOUT_OFFLOAD_PROTOCOL_ARP 0x1 /* enum */
5552 #define MC_CMD_LIGHTSOUT_OFFLOAD_PROTOCOL_NS 0x2 /* enum */
5560 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_OFST 0 */
5569 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_OFST 0 */
5580 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_OUT_FILTER_ID_OFST 0
5586 * None. Returns: 0, ENOSYS
5588 #define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD 0x47
5595 #define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_OFST 0
5601 #define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_OUT_LEN 0
5605 * Restore MAC after block reset. Locks required: None. Returns: 0.
5607 #define MC_CMD_MAC_RESET_RESTORE 0x48
5610 #define MC_CMD_MAC_RESET_RESTORE_IN_LEN 0
5613 #define MC_CMD_MAC_RESET_RESTORE_OUT_LEN 0
5619 * required: None Returns: 0
5621 #define MC_CMD_TESTASSERT 0x49
5627 #define MC_CMD_TESTASSERT_IN_LEN 0
5630 #define MC_CMD_TESTASSERT_OUT_LEN 0
5635 #define MC_CMD_TESTASSERT_V2_IN_TYPE_OFST 0
5640 #define MC_CMD_TESTASSERT_V2_IN_FAIL_ASSERTION_WITH_USEFUL_VALUES 0x0
5641 /* enum: Assert using assert(0); */
5642 #define MC_CMD_TESTASSERT_V2_IN_ASSERT_FALSE 0x1
5644 #define MC_CMD_TESTASSERT_V2_IN_WATCHDOG 0x2
5646 #define MC_CMD_TESTASSERT_V2_IN_LOAD_TRAP 0x3
5648 #define MC_CMD_TESTASSERT_V2_IN_STORE_TRAP 0x4
5650 #define MC_CMD_TESTASSERT_V2_IN_JUMP_TRAP 0x5
5653 #define MC_CMD_TESTASSERT_V2_OUT_LEN 0
5661 * basis. Locks required: None. Returns: 0, EINVAL .
5663 #define MC_CMD_WORKAROUND 0x4a
5671 #define MC_CMD_WORKAROUND_IN_TYPE_OFST 0
5674 #define MC_CMD_WORKAROUND_BUG17230 0x1
5676 #define MC_CMD_WORKAROUND_BUG35388 0x2
5678 #define MC_CMD_WORKAROUND_BUG35017 0x3
5680 #define MC_CMD_WORKAROUND_BUG41750 0x4
5686 #define MC_CMD_WORKAROUND_BUG42008 0x5
5694 #define MC_CMD_WORKAROUND_BUG26807 0x6
5696 #define MC_CMD_WORKAROUND_BUG61265 0x7
5697 /* 0 = disable the workaround indicated by TYPE; any non-zero value = enable
5704 #define MC_CMD_WORKAROUND_OUT_LEN 0
5710 #define MC_CMD_WORKAROUND_EXT_OUT_FLAGS_OFST 0
5712 #define MC_CMD_WORKAROUND_EXT_OUT_FLR_DONE_LBN 0
5720 * output data, are interpreted on a per-type basis. For SFP+: PAGE=0 or 1
5721 * returns a 128-byte block read from module I2C address 0xA0 offset 0 or 0x80.
5722 * Anything else: currently undefined. Locks required: None. Return code: 0.
5724 #define MC_CMD_GET_PHY_MEDIA_INFO 0x4b
5731 #define MC_CMD_GET_PHY_MEDIA_INFO_IN_PAGE_OFST 0
5739 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATALEN_OFST 0
5751 #define MC_CMD_NVRAM_TEST 0x4c
5758 #define MC_CMD_NVRAM_TEST_IN_TYPE_OFST 0
5765 #define MC_CMD_NVRAM_TEST_OUT_RESULT_OFST 0
5768 #define MC_CMD_NVRAM_TEST_PASS 0x0
5770 #define MC_CMD_NVRAM_TEST_FAIL 0x1
5772 #define MC_CMD_NVRAM_TEST_NOTSUPP 0x2
5778 * they are configured first. Locks required: None. Return code: 0, EINVAL.
5780 #define MC_CMD_MRSFP_TWEAK 0x4d
5784 /* 0-6 low->high de-emph. */
5785 #define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_TXEQ_LEVEL_OFST 0
5787 /* 0-8 low->high ref.V */
5790 /* 0-8 0-8 low->high boost */
5793 /* 0-8 low->high ref.V */
5798 #define MC_CMD_MRSFP_TWEAK_IN_READ_ONLY_LEN 0
5803 #define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_INPUTS_OFST 0
5812 #define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_DIRECTION_OUT 0x0
5814 #define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_DIRECTION_IN 0x1
5822 #define MC_CMD_SENSOR_SET_LIMS 0x4e
5829 #define MC_CMD_SENSOR_SET_LIMS_IN_SENSOR_OFST 0
5847 #define MC_CMD_SENSOR_SET_LIMS_OUT_LEN 0
5852 #define MC_CMD_GET_RESOURCE_LIMITS 0x4f
5855 #define MC_CMD_GET_RESOURCE_LIMITS_IN_LEN 0
5859 #define MC_CMD_GET_RESOURCE_LIMITS_OUT_BUFTBL_OFST 0
5871 * none. Returns: 0, EINVAL (bad type).
5873 #define MC_CMD_NVRAM_PARTITIONS 0x51
5879 #define MC_CMD_NVRAM_PARTITIONS_IN_LEN 0
5886 #define MC_CMD_NVRAM_PARTITIONS_OUT_NUM_PARTITIONS_OFST 0
5891 #define MC_CMD_NVRAM_PARTITIONS_OUT_TYPE_ID_MINNUM 0
5897 * none. Returns: 0, EINVAL (bad type).
5899 #define MC_CMD_NVRAM_METADATA 0x52
5907 #define MC_CMD_NVRAM_METADATA_IN_TYPE_OFST 0
5915 #define MC_CMD_NVRAM_METADATA_OUT_TYPE_OFST 0
5919 #define MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_VALID_LBN 0
5943 #define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_MINNUM 0
5950 #define MC_CMD_GET_MAC_ADDRESSES 0x55
5956 #define MC_CMD_GET_MAC_ADDRESSES_IN_LEN 0
5961 #define MC_CMD_GET_MAC_ADDRESSES_OUT_MAC_ADDR_BASE_OFST 0
5977 #define MC_CMD_CLP 0x56
5985 #define MC_CMD_CLP_IN_OP_OFST 0
5988 #define MC_CMD_CLP_OP_DEFAULT 0x1
5990 #define MC_CMD_CLP_OP_SET_MAC 0x2
5992 #define MC_CMD_CLP_OP_GET_MAC 0x3
5994 #define MC_CMD_CLP_OP_SET_BOOT 0x4
5996 #define MC_CMD_CLP_OP_GET_BOOT 0x5
5999 #define MC_CMD_CLP_OUT_LEN 0
6003 /* MC_CMD_CLP_IN_OP_OFST 0 */
6007 #define MC_CMD_CLP_OUT_DEFAULT_LEN 0
6011 /* MC_CMD_CLP_IN_OP_OFST 0 */
6021 #define MC_CMD_CLP_OUT_SET_MAC_LEN 0
6025 /* MC_CMD_CLP_IN_OP_OFST 0 */
6031 #define MC_CMD_CLP_OUT_GET_MAC_ADDR_OFST 0
6039 /* MC_CMD_CLP_IN_OP_OFST 0 */
6046 #define MC_CMD_CLP_OUT_SET_BOOT_LEN 0
6050 /* MC_CMD_CLP_IN_OP_OFST 0 */
6056 #define MC_CMD_CLP_OUT_GET_BOOT_FLAG_OFST 0
6066 #define MC_CMD_MUM 0x57
6073 #define MC_CMD_MUM_IN_OP_HDR_OFST 0
6075 #define MC_CMD_MUM_IN_OP_LBN 0
6078 #define MC_CMD_MUM_OP_NULL 0x1
6080 #define MC_CMD_MUM_OP_GET_VERSION 0x2
6082 #define MC_CMD_MUM_OP_RAW_CMD 0x3
6084 #define MC_CMD_MUM_OP_READ 0x4
6086 #define MC_CMD_MUM_OP_WRITE 0x5
6088 #define MC_CMD_MUM_OP_LOG 0x6
6090 #define MC_CMD_MUM_OP_GPIO 0x7
6092 #define MC_CMD_MUM_OP_READ_SENSORS 0x8
6094 #define MC_CMD_MUM_OP_PROGRAM_CLOCKS 0x9
6096 #define MC_CMD_MUM_OP_FPGA_LOAD 0xa
6100 #define MC_CMD_MUM_OP_READ_ATB_SENSOR 0xb
6104 #define MC_CMD_MUM_OP_QSFP 0xc
6108 #define MC_CMD_MUM_OP_READ_DDR_INFO 0xd
6113 #define MC_CMD_MUM_IN_CMD_OFST 0
6119 /* MC_CMD_MUM_IN_CMD_OFST 0 */
6125 /* MC_CMD_MUM_IN_CMD_OFST 0 */
6131 #define MC_CMD_MUM_DEV_HITTITE 0x1
6133 #define MC_CMD_MUM_DEV_HITTITE_NIC 0x2
6146 /* MC_CMD_MUM_IN_CMD_OFST 0 */
6152 /* MC_CMD_MUM_DEV_HITTITE 0x1 */
6167 /* MC_CMD_MUM_IN_CMD_OFST 0 */
6187 /* MC_CMD_MUM_IN_CMD_OFST 0 */
6191 #define MC_CMD_MUM_IN_LOG_OP_UART 0x1 /* enum */
6195 /* MC_CMD_MUM_IN_CMD_OFST 0 */
6206 /* MC_CMD_MUM_IN_CMD_OFST 0 */
6210 #define MC_CMD_MUM_IN_GPIO_OPCODE_LBN 0
6212 #define MC_CMD_MUM_IN_GPIO_IN_READ 0x0 /* enum */
6213 #define MC_CMD_MUM_IN_GPIO_OUT_WRITE 0x1 /* enum */
6214 #define MC_CMD_MUM_IN_GPIO_OUT_READ 0x2 /* enum */
6215 #define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE 0x3 /* enum */
6216 #define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_READ 0x4 /* enum */
6217 #define MC_CMD_MUM_IN_GPIO_OP 0x5 /* enum */
6221 /* MC_CMD_MUM_IN_CMD_OFST 0 */
6228 /* MC_CMD_MUM_IN_CMD_OFST 0 */
6241 /* MC_CMD_MUM_IN_CMD_OFST 0 */
6248 /* MC_CMD_MUM_IN_CMD_OFST 0 */
6261 /* MC_CMD_MUM_IN_CMD_OFST 0 */
6268 /* MC_CMD_MUM_IN_CMD_OFST 0 */
6274 #define MC_CMD_MUM_IN_GPIO_OP_OUT_READ 0x0 /* enum */
6275 #define MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE 0x1 /* enum */
6276 #define MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG 0x2 /* enum */
6277 #define MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE 0x3 /* enum */
6283 /* MC_CMD_MUM_IN_CMD_OFST 0 */
6290 /* MC_CMD_MUM_IN_CMD_OFST 0 */
6299 /* MC_CMD_MUM_IN_CMD_OFST 0 */
6308 /* MC_CMD_MUM_IN_CMD_OFST 0 */
6318 /* MC_CMD_MUM_IN_CMD_OFST 0 */
6322 #define MC_CMD_MUM_IN_READ_SENSORS_SENSOR_ID_LBN 0
6330 /* MC_CMD_MUM_IN_CMD_OFST 0 */
6335 #define MC_CMD_MUM_CLOCK_ID_FPGA 0x0 /* enum */
6336 #define MC_CMD_MUM_CLOCK_ID_DDR 0x1 /* enum */
6337 #define MC_CMD_MUM_CLOCK_ID_NIC 0x2 /* enum */
6341 #define MC_CMD_MUM_IN_PROGRAM_CLOCKS_OVERCLOCK_110_LBN 0
6351 /* MC_CMD_MUM_IN_CMD_OFST 0 */
6360 /* MC_CMD_MUM_IN_CMD_OFST 0 */
6366 /* MC_CMD_MUM_IN_CMD_OFST 0 */
6370 #define MC_CMD_MUM_IN_QSFP_OPCODE_LBN 0
6372 #define MC_CMD_MUM_IN_QSFP_INIT 0x0 /* enum */
6373 #define MC_CMD_MUM_IN_QSFP_RECONFIGURE 0x1 /* enum */
6374 #define MC_CMD_MUM_IN_QSFP_GET_SUPPORTED_CAP 0x2 /* enum */
6375 #define MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO 0x3 /* enum */
6376 #define MC_CMD_MUM_IN_QSFP_FILL_STATS 0x4 /* enum */
6377 #define MC_CMD_MUM_IN_QSFP_POLL_BIST 0x5 /* enum */
6383 /* MC_CMD_MUM_IN_CMD_OFST 0 */
6394 /* MC_CMD_MUM_IN_CMD_OFST 0 */
6409 /* MC_CMD_MUM_IN_CMD_OFST 0 */
6418 /* MC_CMD_MUM_IN_CMD_OFST 0 */
6429 /* MC_CMD_MUM_IN_CMD_OFST 0 */
6438 /* MC_CMD_MUM_IN_CMD_OFST 0 */
6448 /* MC_CMD_MUM_IN_CMD_OFST 0 */
6452 #define MC_CMD_MUM_OUT_LEN 0
6455 #define MC_CMD_MUM_OUT_NULL_LEN 0
6459 #define MC_CMD_MUM_OUT_GET_VERSION_FIRMWARE_OFST 0
6469 #define MC_CMD_MUM_OUT_RAW_CMD_LEN(num) (0+1*(num))
6471 #define MC_CMD_MUM_OUT_RAW_CMD_DATA_OFST 0
6479 #define MC_CMD_MUM_OUT_READ_LEN(num) (0+4*(num))
6480 #define MC_CMD_MUM_OUT_READ_BUFFER_OFST 0
6486 #define MC_CMD_MUM_OUT_WRITE_LEN 0
6489 #define MC_CMD_MUM_OUT_LOG_LEN 0
6492 #define MC_CMD_MUM_OUT_LOG_OP_UART_LEN 0
6497 #define MC_CMD_MUM_OUT_GPIO_IN_READ_GPIOMASK1_OFST 0
6504 #define MC_CMD_MUM_OUT_GPIO_OUT_WRITE_LEN 0
6509 #define MC_CMD_MUM_OUT_GPIO_OUT_READ_GPIOMASK1_OFST 0
6516 #define MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_WRITE_LEN 0
6520 #define MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_READ_GPIOMASK1_OFST 0
6527 #define MC_CMD_MUM_OUT_GPIO_OP_OUT_READ_BIT_READ_OFST 0
6531 #define MC_CMD_MUM_OUT_GPIO_OP_OUT_WRITE_LEN 0
6534 #define MC_CMD_MUM_OUT_GPIO_OP_OUT_CONFIG_LEN 0
6537 #define MC_CMD_MUM_OUT_GPIO_OP_OUT_ENABLE_LEN 0
6542 #define MC_CMD_MUM_OUT_READ_SENSORS_LEN(num) (0+4*(num))
6543 #define MC_CMD_MUM_OUT_READ_SENSORS_DATA_OFST 0
6547 #define MC_CMD_MUM_OUT_READ_SENSORS_READING_LBN 0
6556 #define MC_CMD_MUM_OUT_PROGRAM_CLOCKS_OK_MASK_OFST 0
6560 #define MC_CMD_MUM_OUT_FPGA_LOAD_LEN 0
6564 #define MC_CMD_MUM_OUT_READ_ATB_SENSOR_RESULT_OFST 0
6568 #define MC_CMD_MUM_OUT_QSFP_INIT_LEN 0
6572 #define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_LP_CAP_OFST 0
6576 #define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_READY_LBN 0
6583 #define MC_CMD_MUM_OUT_QSFP_GET_SUPPORTED_CAP_PORT_PHY_LP_CAP_OFST 0
6591 #define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_DATALEN_OFST 0
6600 #define MC_CMD_MUM_OUT_QSFP_FILL_STATS_PORT_PHY_STATS_PMA_PMD_LINK_UP_OFST 0
6607 #define MC_CMD_MUM_OUT_QSFP_POLL_BIST_TEST_OFST 0
6615 #define MC_CMD_MUM_OUT_READ_DDR_INFO_DISCRETE_DDR_INFO_OFST 0
6617 #define MC_CMD_MUM_OUT_READ_DDR_INFO_VRATIO_LBN 0
6631 #define MC_CMD_MUM_OUT_READ_DDR_INFO_BANK_ID_LBN 0
6634 #define MC_CMD_MUM_OUT_READ_DDR_INFO_BANK1 0x0
6636 #define MC_CMD_MUM_OUT_READ_DDR_INFO_BANK2 0x1
6638 #define MC_CMD_MUM_OUT_READ_DDR_INFO_NUM_BANKS 0x2
6645 #define MC_CMD_MUM_OUT_READ_DDR_INFO_NOT_POWERED 0x0 /* enum */
6646 #define MC_CMD_MUM_OUT_READ_DDR_INFO_1V25 0x1 /* enum */
6647 #define MC_CMD_MUM_OUT_READ_DDR_INFO_1V35 0x2 /* enum */
6648 #define MC_CMD_MUM_OUT_READ_DDR_INFO_1V5 0x3 /* enum */
6650 #define MC_CMD_MUM_OUT_READ_DDR_INFO_1V8 0x4
6658 #define MC_CMD_MUM_OUT_READ_DDR_INFO_ABSENT 0x0
6660 #define MC_CMD_MUM_OUT_READ_DDR_INFO_PRESENT_POWERED 0x1
6662 #define MC_CMD_MUM_OUT_READ_DDR_INFO_PRESENT_BAD_TYPE 0x2
6664 #define MC_CMD_MUM_OUT_READ_DDR_INFO_PRESENT_BAD_VOLTAGE 0x3
6666 #define MC_CMD_MUM_OUT_READ_DDR_INFO_PRESENT_BAD_SPD 0x4
6668 #define MC_CMD_MUM_OUT_READ_DDR_INFO_PRESENT_BAD_SLOT 0x5
6671 #define MC_CMD_MUM_OUT_READ_DDR_INFO_NOT_REACHABLE 0x6
6677 #define MC_CMD_RESOURCE_INSTANCE_ANY 0xffffffff
6679 #define MC_CMD_RESOURCE_INSTANCE_NONE 0xfffffffe
6683 #define EVB_PORT_ID_PORT_ID_OFST 0
6686 #define EVB_PORT_ID_NULL 0x0
6688 #define EVB_PORT_ID_ASSIGNED 0x1000000
6689 /* enum: External network port 0 */
6690 #define EVB_PORT_ID_MAC0 0x2000000
6692 #define EVB_PORT_ID_MAC1 0x2000001
6694 #define EVB_PORT_ID_MAC2 0x2000002
6696 #define EVB_PORT_ID_MAC3 0x2000003
6697 #define EVB_PORT_ID_PORT_ID_LBN 0
6703 #define EVB_VLAN_TAG_VLAN_ID_LBN 0
6708 #define EVB_VLAN_TAG_INSERT 0x0
6710 #define EVB_VLAN_TAG_REPLACE 0x1
6715 #define BUFTBL_ENTRY_OID_OFST 0
6717 #define BUFTBL_ENTRY_OID_LBN 0
6734 #define NVRAM_PARTITION_TYPE_ID_OFST 0
6737 #define NVRAM_PARTITION_TYPE_MC_FIRMWARE 0x100
6739 #define NVRAM_PARTITION_TYPE_MC_FIRMWARE_BACKUP 0x200
6741 #define NVRAM_PARTITION_TYPE_EXPANSION_ROM 0x300
6743 #define NVRAM_PARTITION_TYPE_STATIC_CONFIG 0x400
6745 #define NVRAM_PARTITION_TYPE_DYNAMIC_CONFIG 0x500
6746 /* enum: Expansion ROM configuration data for port 0 */
6747 #define NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT0 0x600
6749 #define NVRAM_PARTITION_TYPE_EXPROM_CONFIG 0x600
6751 #define NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT1 0x601
6753 #define NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT2 0x602
6755 #define NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT3 0x603
6757 #define NVRAM_PARTITION_TYPE_LOG 0x700
6759 #define NVRAM_PARTITION_TYPE_LOG_SLAVE 0x701
6761 #define NVRAM_PARTITION_TYPE_DUMP 0x800
6763 #define NVRAM_PARTITION_TYPE_LICENSE 0x900
6765 #define NVRAM_PARTITION_TYPE_PHY_MIN 0xa00
6767 #define NVRAM_PARTITION_TYPE_PHY_MAX 0xaff
6769 #define NVRAM_PARTITION_TYPE_FPGA 0xb00
6771 #define NVRAM_PARTITION_TYPE_FPGA_BACKUP 0xb01
6773 #define NVRAM_PARTITION_TYPE_FC_FIRMWARE 0xb02
6775 #define NVRAM_PARTITION_TYPE_FC_LICENSE 0xb03
6777 #define NVRAM_PARTITION_TYPE_FC_LOG 0xb04
6779 #define NVRAM_PARTITION_TYPE_MUM_FIRMWARE 0xc00
6783 #define NVRAM_PARTITION_TYPE_SUC_FIRMWARE 0xc00
6785 #define NVRAM_PARTITION_TYPE_MUM_LOG 0xc01
6787 #define NVRAM_PARTITION_TYPE_MUM_APPTABLE 0xc02
6789 #define NVRAM_PARTITION_TYPE_MUM_BOOT_ROM 0xc03
6791 #define NVRAM_PARTITION_TYPE_MUM_PROD_ROM 0xc04
6793 #define NVRAM_PARTITION_TYPE_MUM_USER_ROM 0xc05
6795 #define NVRAM_PARTITION_TYPE_MUM_FUSELOCK 0xc06
6797 #define NVRAM_PARTITION_TYPE_EXPANSION_UEFI 0xd00
6799 #define NVRAM_PARTITION_TYPE_PXE_LOG 0x1000
6801 #define NVRAM_PARTITION_TYPE_XIP_SCRATCH 0x1100
6803 #define NVRAM_PARTITION_TYPE_SPARE_2 0x1200
6807 #define NVRAM_PARTITION_TYPE_MANUFACTURING 0x1300
6809 #define NVRAM_PARTITION_TYPE_SPARE_4 0x1400
6811 #define NVRAM_PARTITION_TYPE_SPARE_5 0x1500
6815 #define NVRAM_PARTITION_TYPE_STATUS 0x1600
6817 #define NVRAM_PARTITION_TYPE_SPARE_13 0x1700
6819 #define NVRAM_PARTITION_TYPE_SPARE_14 0x1800
6821 #define NVRAM_PARTITION_TYPE_SPARE_15 0x1900
6823 #define NVRAM_PARTITION_TYPE_SPARE_16 0x1a00
6825 #define NVRAM_PARTITION_TYPE_DYNCONFIG_DEFAULTS 0x1b00
6827 #define NVRAM_PARTITION_TYPE_ROMCONFIG_DEFAULTS 0x1c00
6832 #define NVRAM_PARTITION_TYPE_FRU_INFORMATION 0x1d00
6834 #define NVRAM_PARTITION_TYPE_RESERVED_VALUES_MIN 0xff00
6836 #define NVRAM_PARTITION_TYPE_RESERVED_VALUES_MAX 0xfffd
6838 #define NVRAM_PARTITION_TYPE_RECOVERY_MAP 0xfffe
6840 #define NVRAM_PARTITION_TYPE_PARTITION_MAP 0xffff
6841 #define NVRAM_PARTITION_TYPE_ID_LBN 0
6846 #define LICENSED_APP_ID_ID_OFST 0
6849 #define LICENSED_APP_ID_ONLOAD 0x1
6851 #define LICENSED_APP_ID_PTP 0x2
6853 #define LICENSED_APP_ID_SOLARCAPTURE_PRO 0x4
6855 #define LICENSED_APP_ID_SOLARSECURE 0x8
6857 #define LICENSED_APP_ID_PERF_MONITOR 0x10
6859 #define LICENSED_APP_ID_SOLARCAPTURE_LIVE 0x20
6861 #define LICENSED_APP_ID_CAPTURE_SOLARSYSTEM 0x40
6863 #define LICENSED_APP_ID_NETWORK_ACCESS_CONTROL 0x80
6865 #define LICENSED_APP_ID_TCP_DIRECT 0x100
6867 #define LICENSED_APP_ID_LOW_LATENCY 0x200
6869 #define LICENSED_APP_ID_SOLARCAPTURE_TAP 0x400
6871 #define LICENSED_APP_ID_CAPTURE_SOLARSYSTEM_40G 0x800
6873 #define LICENSED_APP_ID_CAPTURE_SOLARSYSTEM_1G 0x1000
6875 #define LICENSED_APP_ID_SCALEOUT_ONLOAD 0x2000
6877 #define LICENSED_APP_ID_DSHBRD 0x4000
6879 #define LICENSED_APP_ID_SCATRD 0x8000
6880 #define LICENSED_APP_ID_ID_LBN 0
6886 #define LICENSED_FEATURES_MASK_OFST 0
6888 #define LICENSED_FEATURES_MASK_LO_OFST 0
6890 #define LICENSED_FEATURES_RX_CUT_THROUGH_LBN 0
6910 #define LICENSED_FEATURES_MASK_LBN 0
6916 #define LICENSED_V3_APPS_MASK_OFST 0
6918 #define LICENSED_V3_APPS_MASK_LO_OFST 0
6920 #define LICENSED_V3_APPS_ONLOAD_LBN 0
6952 #define LICENSED_V3_APPS_MASK_LBN 0
6958 #define LICENSED_V3_FEATURES_MASK_OFST 0
6960 #define LICENSED_V3_FEATURES_MASK_LO_OFST 0
6962 #define LICENSED_V3_FEATURES_RX_CUT_THROUGH_LBN 0
6982 #define LICENSED_V3_FEATURES_MASK_LBN 0
6988 #define TX_TIMESTAMP_EVENT_TSTAMP_DATA_LO_OFST 0
6990 #define TX_TIMESTAMP_EVENT_TSTAMP_DATA_LO_LBN 0
6997 #define TX_TIMESTAMP_EVENT_TX_EV_COMPLETION 0x0
7001 #define TX_TIMESTAMP_EVENT_TX_EV_CTPIO_COMPLETION 0x11
7005 #define TX_TIMESTAMP_EVENT_TX_EV_CTPIO_TS_LO 0x12
7009 #define TX_TIMESTAMP_EVENT_TX_EV_CTPIO_TS_HI 0x13
7011 #define TX_TIMESTAMP_EVENT_TX_EV_TSTAMP_LO 0x51
7013 #define TX_TIMESTAMP_EVENT_TX_EV_TSTAMP_HI 0x52
7024 /* The RSS mode for a particular packet type is a value from 0 - 15 which can
7026 * value 0 effectively disables RSS spreading for the packet type.) The YAML
7030 #define RSS_MODE_HASH_SELECTOR_OFST 0
7032 #define RSS_MODE_HASH_SRC_ADDR_LBN 0
7040 #define RSS_MODE_HASH_SELECTOR_LBN 0
7046 #define CTPIO_STATS_MAP_VI_OFST 0
7048 #define CTPIO_STATS_MAP_VI_LBN 0
7065 #define MESSAGE_TYPE_MESSAGE_TYPE_OFST 0
7067 #define MESSAGE_TYPE_UNUSED 0x0 /* enum */
7074 #define MESSAGE_TYPE_TSA_SECURE_UNBIND 0x1
7081 #define MESSAGE_TYPE_TSA_SECURE_DECOMMISSION 0x2
7088 #define MESSAGE_TYPE_SECURE_NIC_INFO_STATUS 0xdb4
7089 #define MESSAGE_TYPE_MESSAGE_TYPE_LBN 0
7096 #define MC_CMD_READ_REGS 0x50
7102 #define MC_CMD_READ_REGS_IN_LEN 0
7107 #define MC_CMD_READ_REGS_OUT_MASK_OFST 0
7121 #define MC_CMD_INIT_EVQ 0x80
7131 #define MC_CMD_INIT_EVQ_IN_SIZE_OFST 0
7148 #define MC_CMD_INIT_EVQ_IN_FLAG_INTERRUPTING_LBN 0
7165 #define MC_CMD_INIT_EVQ_IN_TMR_MODE_DIS 0x0
7167 #define MC_CMD_INIT_EVQ_IN_TMR_IMMED_START 0x1
7169 #define MC_CMD_INIT_EVQ_IN_TMR_TRIG_START 0x2
7171 #define MC_CMD_INIT_EVQ_IN_TMR_INT_HLDOFF 0x3
7185 #define MC_CMD_INIT_EVQ_IN_COUNT_MODE_DIS 0x0
7187 #define MC_CMD_INIT_EVQ_IN_COUNT_MODE_RX 0x1
7189 #define MC_CMD_INIT_EVQ_IN_COUNT_MODE_TX 0x2
7191 #define MC_CMD_INIT_EVQ_IN_COUNT_MODE_RXTX 0x3
7206 #define MC_CMD_INIT_EVQ_OUT_IRQ_OFST 0
7214 #define MC_CMD_INIT_EVQ_V2_IN_SIZE_OFST 0
7231 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_INTERRUPTING_LBN 0
7248 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_MANUAL 0x0
7254 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_LOW_LATENCY 0x1
7260 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_THROUGHPUT 0x2
7265 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_AUTO 0x3
7269 #define MC_CMD_INIT_EVQ_V2_IN_TMR_MODE_DIS 0x0
7271 #define MC_CMD_INIT_EVQ_V2_IN_TMR_IMMED_START 0x1
7273 #define MC_CMD_INIT_EVQ_V2_IN_TMR_TRIG_START 0x2
7275 #define MC_CMD_INIT_EVQ_V2_IN_TMR_INT_HLDOFF 0x3
7289 #define MC_CMD_INIT_EVQ_V2_IN_COUNT_MODE_DIS 0x0
7291 #define MC_CMD_INIT_EVQ_V2_IN_COUNT_MODE_RX 0x1
7293 #define MC_CMD_INIT_EVQ_V2_IN_COUNT_MODE_TX 0x2
7295 #define MC_CMD_INIT_EVQ_V2_IN_COUNT_MODE_RXTX 0x3
7310 #define MC_CMD_INIT_EVQ_V2_OUT_IRQ_OFST 0
7315 #define MC_CMD_INIT_EVQ_V2_OUT_FLAG_CUT_THRU_LBN 0
7326 #define QUEUE_CRC_MODE_MODE_LBN 0
7329 #define QUEUE_CRC_MODE_NONE 0x0
7331 #define QUEUE_CRC_MODE_FCOE 0x1
7333 #define QUEUE_CRC_MODE_ISCSI_HDR 0x2
7335 #define QUEUE_CRC_MODE_ISCSI 0x3
7337 #define QUEUE_CRC_MODE_FCOIPOE 0x4
7339 #define QUEUE_CRC_MODE_MPA 0x5
7349 #define MC_CMD_INIT_RXQ 0x81
7361 #define MC_CMD_INIT_RXQ_IN_SIZE_OFST 0
7378 #define MC_CMD_INIT_RXQ_IN_FLAG_BUFF_MODE_LBN 0
7413 #define MC_CMD_INIT_RXQ_EXT_IN_SIZE_OFST 0
7434 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_BUFF_MODE_LBN 0
7451 #define MC_CMD_INIT_RXQ_EXT_IN_SINGLE_PACKET 0x0
7453 #define MC_CMD_INIT_RXQ_EXT_IN_PACKED_STREAM 0x1
7460 #define MC_CMD_INIT_RXQ_EXT_IN_EQUAL_STRIDE_SUPER_BUFFER 0x2
7462 #define MC_CMD_INIT_RXQ_EXT_IN_EQUAL_STRIDE_PACKED_STREAM 0x2
7467 #define MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_1M 0x0 /* enum */
7468 #define MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_512K 0x1 /* enum */
7469 #define MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_256K 0x2 /* enum */
7470 #define MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_128K 0x3 /* enum */
7471 #define MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_64K 0x4 /* enum */
7495 #define MC_CMD_INIT_RXQ_V3_IN_SIZE_OFST 0
7516 #define MC_CMD_INIT_RXQ_V3_IN_FLAG_BUFF_MODE_LBN 0
7533 #define MC_CMD_INIT_RXQ_V3_IN_SINGLE_PACKET 0x0
7535 #define MC_CMD_INIT_RXQ_V3_IN_PACKED_STREAM 0x1
7542 #define MC_CMD_INIT_RXQ_V3_IN_EQUAL_STRIDE_SUPER_BUFFER 0x2
7544 #define MC_CMD_INIT_RXQ_V3_IN_EQUAL_STRIDE_PACKED_STREAM 0x2
7549 #define MC_CMD_INIT_RXQ_V3_IN_PS_BUFF_1M 0x0 /* enum */
7550 #define MC_CMD_INIT_RXQ_V3_IN_PS_BUFF_512K 0x1 /* enum */
7551 #define MC_CMD_INIT_RXQ_V3_IN_PS_BUFF_256K 0x2 /* enum */
7552 #define MC_CMD_INIT_RXQ_V3_IN_PS_BUFF_128K 0x3 /* enum */
7553 #define MC_CMD_INIT_RXQ_V3_IN_PS_BUFF_64K 0x4 /* enum */
7594 * are still no descriptors then the packet will be dropped. A timeout of 0
7602 #define MC_CMD_INIT_RXQ_OUT_LEN 0
7605 #define MC_CMD_INIT_RXQ_EXT_OUT_LEN 0
7608 #define MC_CMD_INIT_RXQ_V3_OUT_LEN 0
7613 #define MC_CMD_INIT_TXQ 0x82
7625 #define MC_CMD_INIT_TXQ_IN_SIZE_OFST 0
7643 #define MC_CMD_INIT_TXQ_IN_FLAG_BUFF_MODE_LBN 0
7680 #define MC_CMD_INIT_TXQ_EXT_IN_SIZE_OFST 0
7698 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_BUFF_MODE_LBN 0
7738 #define MC_CMD_INIT_TXQ_EXT_IN_QBB_ENABLE_LBN 0
7744 #define MC_CMD_INIT_TXQ_OUT_LEN 0
7753 #define MC_CMD_FINI_EVQ 0x83
7763 #define MC_CMD_FINI_EVQ_IN_INSTANCE_OFST 0
7767 #define MC_CMD_FINI_EVQ_OUT_LEN 0
7773 #define MC_CMD_FINI_RXQ 0x84
7781 #define MC_CMD_FINI_RXQ_IN_INSTANCE_OFST 0
7785 #define MC_CMD_FINI_RXQ_OUT_LEN 0
7791 #define MC_CMD_FINI_TXQ 0x85
7799 #define MC_CMD_FINI_TXQ_IN_INSTANCE_OFST 0
7803 #define MC_CMD_FINI_TXQ_OUT_LEN 0
7809 #define MC_CMD_DRIVER_EVENT 0x86
7817 #define MC_CMD_DRIVER_EVENT_IN_EVQ_OFST 0
7819 /* Bits 0 - 63 of event */
7826 #define MC_CMD_DRIVER_EVENT_OUT_LEN 0
7835 #define MC_CMD_PROXY_CMD 0x5b
7843 #define MC_CMD_PROXY_CMD_IN_TARGET_OFST 0
7845 #define MC_CMD_PROXY_CMD_IN_TARGET_PF_LBN 0
7849 #define MC_CMD_PROXY_CMD_IN_VF_NULL 0xffff /* enum */
7852 #define MC_CMD_PROXY_CMD_OUT_LEN 0
7859 #define MC_PROXY_STATUS_BUFFER_HANDLE_OFST 0
7862 #define MC_PROXY_STATUS_BUFFER_HANDLE_INVALID 0x0
7863 #define MC_PROXY_STATUS_BUFFER_HANDLE_LBN 0
7900 #define MC_CMD_PROXY_CONFIGURE 0x58
7907 #define MC_CMD_PROXY_CONFIGURE_IN_FLAGS_OFST 0
7909 #define MC_CMD_PROXY_CONFIGURE_IN_ENABLE_LBN 0
7951 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_FLAGS_OFST 0
7953 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_ENABLE_LBN 0
7996 #define MC_CMD_PROXY_CONFIGURE_OUT_LEN 0
8005 #define MC_CMD_PROXY_COMPLETE 0x5f
8012 #define MC_CMD_PROXY_COMPLETE_IN_BLOCK_INDEX_OFST 0
8019 #define MC_CMD_PROXY_COMPLETE_IN_COMPLETE 0x0
8023 #define MC_CMD_PROXY_COMPLETE_IN_AUTHORIZED 0x1
8025 #define MC_CMD_PROXY_COMPLETE_IN_DECLINED 0x2
8029 #define MC_CMD_PROXY_COMPLETE_IN_TIMEDOUT 0x3
8034 #define MC_CMD_PROXY_COMPLETE_OUT_LEN 0
8042 #define MC_CMD_ALLOC_BUFTBL_CHUNK 0x87
8050 #define MC_CMD_ALLOC_BUFTBL_CHUNK_IN_OWNER_OFST 0
8060 #define MC_CMD_ALLOC_BUFTBL_CHUNK_OUT_HANDLE_OFST 0
8072 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES 0x88
8081 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_HANDLE_OFST 0
8098 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_OUT_LEN 0
8103 #define MC_CMD_FREE_BUFTBL_CHUNK 0x89
8110 #define MC_CMD_FREE_BUFTBL_CHUNK_IN_HANDLE_OFST 0
8114 #define MC_CMD_FREE_BUFTBL_CHUNK_OUT_LEN 0
8120 #define MC_CMD_FILTER_OP 0x8a
8128 #define MC_CMD_FILTER_OP_IN_OP_OFST 0
8131 #define MC_CMD_FILTER_OP_IN_OP_INSERT 0x0
8133 #define MC_CMD_FILTER_OP_IN_OP_REMOVE 0x1
8135 #define MC_CMD_FILTER_OP_IN_OP_SUBSCRIBE 0x2
8137 #define MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE 0x3
8141 #define MC_CMD_FILTER_OP_IN_OP_REPLACE 0x4
8154 #define MC_CMD_FILTER_OP_IN_MATCH_SRC_IP_LBN 0
8186 #define MC_CMD_FILTER_OP_IN_RX_DEST_DROP 0x0
8188 #define MC_CMD_FILTER_OP_IN_RX_DEST_HOST 0x1
8190 #define MC_CMD_FILTER_OP_IN_RX_DEST_MC 0x2
8191 /* enum: loop back to TXDP 0 */
8192 #define MC_CMD_FILTER_OP_IN_RX_DEST_TX0 0x3
8194 #define MC_CMD_FILTER_OP_IN_RX_DEST_TX1 0x4
8202 #define MC_CMD_FILTER_OP_IN_RX_MODE_SIMPLE 0x0
8204 #define MC_CMD_FILTER_OP_IN_RX_MODE_RSS 0x1
8206 #define MC_CMD_FILTER_OP_IN_RX_MODE_DOT1P_MAPPING 0x2
8209 #define MC_CMD_FILTER_OP_IN_RX_MODE_TEST_NEVER_MATCH 0x80000000
8216 /* transmit domain (reserved; set to 0) */
8226 #define MC_CMD_FILTER_OP_IN_TX_DEST_DEFAULT 0xffffffff
8227 #define MC_CMD_FILTER_OP_IN_TX_DEST_MAC_LBN 0
8252 /* IP protocol to match (in low byte; set high byte to 0) */
8255 /* Firmware defined register 0 to match (reserved; set to 0) */
8258 /* Firmware defined register 1 to match (reserved; set to 0) */
8262 * 0 for IPv4 address)
8267 * bytes to 0 for IPv4 address)
8278 #define MC_CMD_FILTER_OP_EXT_IN_OP_OFST 0
8294 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_IP_LBN 0
8354 #define MC_CMD_FILTER_OP_EXT_IN_RX_DEST_DROP 0x0
8356 #define MC_CMD_FILTER_OP_EXT_IN_RX_DEST_HOST 0x1
8358 #define MC_CMD_FILTER_OP_EXT_IN_RX_DEST_MC 0x2
8359 /* enum: loop back to TXDP 0 */
8360 #define MC_CMD_FILTER_OP_EXT_IN_RX_DEST_TX0 0x3
8362 #define MC_CMD_FILTER_OP_EXT_IN_RX_DEST_TX1 0x4
8370 #define MC_CMD_FILTER_OP_EXT_IN_RX_MODE_SIMPLE 0x0
8372 #define MC_CMD_FILTER_OP_EXT_IN_RX_MODE_RSS 0x1
8374 #define MC_CMD_FILTER_OP_EXT_IN_RX_MODE_DOT1P_MAPPING 0x2
8377 #define MC_CMD_FILTER_OP_EXT_IN_RX_MODE_TEST_NEVER_MATCH 0x80000000
8384 /* transmit domain (reserved; set to 0) */
8394 #define MC_CMD_FILTER_OP_EXT_IN_TX_DEST_DEFAULT 0xffffffff
8395 #define MC_CMD_FILTER_OP_EXT_IN_TX_DEST_MAC_LBN 0
8420 /* IP protocol to match (in low byte; set high byte to 0) */
8423 /* Firmware defined register 0 to match (reserved; set to 0) */
8427 * protocol is GRE) to match (as bytes in network order; set last byte to 0 for
8432 #define MC_CMD_FILTER_OP_EXT_IN_VNI_VALUE_LBN 0
8437 #define MC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_VXLAN 0x0
8439 #define MC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_GENEVE 0x1
8441 #define MC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_EXPERIMENTAL 0xfe
8442 #define MC_CMD_FILTER_OP_EXT_IN_VSID_VALUE_LBN 0
8447 #define MC_CMD_FILTER_OP_EXT_IN_VSID_TYPE_NVGRE 0x0
8449 * 0 for IPv4 address)
8454 * bytes to 0 for IPv4 address)
8489 * 0)
8493 /* VXLAN/NVGRE inner frame Firmware defined register 0 to match (reserved; set
8494 * to 0)
8499 * to 0)
8504 * order; set last 12 bytes to 0 for IPv4 address)
8509 * order; set last 12 bytes to 0 for IPv4 address)
8522 #define MC_CMD_FILTER_OP_V3_IN_OP_OFST 0
8538 #define MC_CMD_FILTER_OP_V3_IN_MATCH_SRC_IP_LBN 0
8598 #define MC_CMD_FILTER_OP_V3_IN_RX_DEST_DROP 0x0
8600 #define MC_CMD_FILTER_OP_V3_IN_RX_DEST_HOST 0x1
8602 #define MC_CMD_FILTER_OP_V3_IN_RX_DEST_MC 0x2
8603 /* enum: loop back to TXDP 0 */
8604 #define MC_CMD_FILTER_OP_V3_IN_RX_DEST_TX0 0x3
8606 #define MC_CMD_FILTER_OP_V3_IN_RX_DEST_TX1 0x4
8614 #define MC_CMD_FILTER_OP_V3_IN_RX_MODE_SIMPLE 0x0
8616 #define MC_CMD_FILTER_OP_V3_IN_RX_MODE_RSS 0x1
8618 #define MC_CMD_FILTER_OP_V3_IN_RX_MODE_DOT1P_MAPPING 0x2
8621 #define MC_CMD_FILTER_OP_V3_IN_RX_MODE_TEST_NEVER_MATCH 0x80000000
8628 /* transmit domain (reserved; set to 0) */
8638 #define MC_CMD_FILTER_OP_V3_IN_TX_DEST_DEFAULT 0xffffffff
8639 #define MC_CMD_FILTER_OP_V3_IN_TX_DEST_MAC_LBN 0
8664 /* IP protocol to match (in low byte; set high byte to 0) */
8667 /* Firmware defined register 0 to match (reserved; set to 0) */
8671 * protocol is GRE) to match (as bytes in network order; set last byte to 0 for
8676 #define MC_CMD_FILTER_OP_V3_IN_VNI_VALUE_LBN 0
8681 #define MC_CMD_FILTER_OP_V3_IN_VNI_TYPE_VXLAN 0x0
8683 #define MC_CMD_FILTER_OP_V3_IN_VNI_TYPE_GENEVE 0x1
8685 #define MC_CMD_FILTER_OP_V3_IN_VNI_TYPE_EXPERIMENTAL 0xfe
8686 #define MC_CMD_FILTER_OP_V3_IN_VSID_VALUE_LBN 0
8691 #define MC_CMD_FILTER_OP_V3_IN_VSID_TYPE_NVGRE 0x0
8693 * 0 for IPv4 address)
8698 * bytes to 0 for IPv4 address)
8733 * 0)
8737 /* VXLAN/NVGRE inner frame Firmware defined register 0 to match (reserved; set
8738 * to 0)
8743 * to 0)
8748 * order; set last 12 bytes to 0 for IPv4 address)
8753 * order; set last 12 bytes to 0 for IPv4 address)
8766 #define MC_CMD_FILTER_OP_V3_IN_MATCH_ACTION_NONE 0x0
8771 #define MC_CMD_FILTER_OP_V3_IN_MATCH_ACTION_FLAG 0x1
8776 #define MC_CMD_FILTER_OP_V3_IN_MATCH_ACTION_MARK 0x2
8787 #define MC_CMD_FILTER_OP_OUT_OP_OFST 0
8793 * 0xFFFFFFFF_FFFFFFFF is guaranteed never to be a valid handle.
8800 #define MC_CMD_FILTER_OP_OUT_HANDLE_LO_INVALID 0xffffffff
8802 #define MC_CMD_FILTER_OP_OUT_HANDLE_HI_INVALID 0xffffffff
8807 #define MC_CMD_FILTER_OP_EXT_OUT_OP_OFST 0
8813 * 0xFFFFFFFF_FFFFFFFF is guaranteed never to be a valid handle.
8826 #define MC_CMD_GET_PARSER_DISP_INFO 0xe4
8834 #define MC_CMD_GET_PARSER_DISP_INFO_IN_OP_OFST 0
8837 #define MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SUPPORTED_RX_MATCHES 0x1
8841 #define MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_RESTRICTIONS 0x2
8845 #define MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SECURITY_RULE_INFO 0x3
8850 #define MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SUPPORTED_ENCAP_RX_MATCHES 0x4
8857 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_OP_OFST 0
8869 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_MINNUM 0
8875 #define MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_OP_OFST 0
8882 #define MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_DST_IP_MCAST_ONLY_LBN 0
8894 #define MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_OP_OFST 0
8904 #define MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_RULES_VERSION_SF_114946_SW_C 0x0
8936 #define MC_CMD_PARSER_DISP_RW 0xe5
8944 #define MC_CMD_PARSER_DISP_RW_IN_TARGET_OFST 0
8947 #define MC_CMD_PARSER_DISP_RW_IN_RX_DICPU 0x0
8949 #define MC_CMD_PARSER_DISP_RW_IN_TX_DICPU 0x1
8955 #define MC_CMD_PARSER_DISP_RW_IN_LUE 0x2
8957 #define MC_CMD_PARSER_DISP_RW_IN_LUE_VERSIONED_METADATA 0x3
8959 #define MC_CMD_PARSER_DISP_RW_IN_RX0_DICPU 0x0
8961 #define MC_CMD_PARSER_DISP_RW_IN_RX1_DICPU 0x4
8963 #define MC_CMD_PARSER_DISP_RW_IN_MISC_STATE 0x5
8968 #define MC_CMD_PARSER_DISP_RW_IN_READ 0x0
8972 #define MC_CMD_PARSER_DISP_RW_IN_WRITE 0x1
8976 #define MC_CMD_PARSER_DISP_RW_IN_RMW 0x2
8984 #define MC_CMD_PARSER_DISP_RW_IN_PORT_DP_MAPPING 0x1
9004 #define MC_CMD_PARSER_DISP_RW_OUT_DMEM_READ_VALUE_OFST 0
9007 #define MC_CMD_PARSER_DISP_RW_OUT_LUE_READ_VALUE_OFST 0
9015 #define MC_CMD_PARSER_DISP_RW_OUT_PORT_DP_MAPPING_OFST 0
9018 #define MC_CMD_PARSER_DISP_RW_OUT_DP0 0x1 /* enum */
9019 #define MC_CMD_PARSER_DISP_RW_OUT_DP1 0x2 /* enum */
9025 #define MC_CMD_GET_PF_COUNT 0xb6
9031 #define MC_CMD_GET_PF_COUNT_IN_LEN 0
9036 #define MC_CMD_GET_PF_COUNT_OUT_PF_COUNT_OFST 0
9043 #define MC_CMD_SET_PF_COUNT 0xb7
9048 #define MC_CMD_SET_PF_COUNT_IN_PF_COUNT_OFST 0
9052 #define MC_CMD_SET_PF_COUNT_OUT_LEN 0
9058 #define MC_CMD_GET_PORT_ASSIGNMENT 0xb8
9064 #define MC_CMD_GET_PORT_ASSIGNMENT_IN_LEN 0
9069 #define MC_CMD_GET_PORT_ASSIGNMENT_OUT_PORT_OFST 0
9076 #define MC_CMD_SET_PORT_ASSIGNMENT 0xb9
9084 #define MC_CMD_SET_PORT_ASSIGNMENT_IN_PORT_OFST 0
9088 #define MC_CMD_SET_PORT_ASSIGNMENT_OUT_LEN 0
9094 #define MC_CMD_ALLOC_VIS 0x8b
9102 #define MC_CMD_ALLOC_VIS_IN_MIN_VI_COUNT_OFST 0
9113 #define MC_CMD_ALLOC_VIS_OUT_VI_COUNT_OFST 0
9124 #define MC_CMD_ALLOC_VIS_EXT_OUT_VI_COUNT_OFST 0
9131 /* Function's port vi_shift value (always 0 on Huntington) */
9140 #define MC_CMD_FREE_VIS 0x8c
9146 #define MC_CMD_FREE_VIS_IN_LEN 0
9149 #define MC_CMD_FREE_VIS_OUT_LEN 0
9155 #define MC_CMD_GET_SRIOV_CFG 0xba
9161 #define MC_CMD_GET_SRIOV_CFG_IN_LEN 0
9166 #define MC_CMD_GET_SRIOV_CFG_OUT_VF_CURRENT_OFST 0
9173 #define MC_CMD_GET_SRIOV_CFG_OUT_VF_ENABLED_LBN 0
9186 #define MC_CMD_SET_SRIOV_CFG 0xbb
9194 #define MC_CMD_SET_SRIOV_CFG_IN_VF_CURRENT_OFST 0
9201 #define MC_CMD_SET_SRIOV_CFG_IN_VF_ENABLED_LBN 0
9203 /* RID offset of first VF from PF, or 0 for no change, or
9208 /* RID offset of each subsequent VF from the previous, 0 for no change, or
9215 #define MC_CMD_SET_SRIOV_CFG_OUT_LEN 0
9222 #define MC_CMD_GET_VI_ALLOC_INFO 0x8d
9228 #define MC_CMD_GET_VI_ALLOC_INFO_IN_LEN 0
9233 #define MC_CMD_GET_VI_ALLOC_INFO_OUT_VI_COUNT_OFST 0
9240 /* Function's port vi_shift value (always 0 on Huntington) */
9248 #define MC_CMD_DUMP_VI_STATE 0x8e
9256 #define MC_CMD_DUMP_VI_STATE_IN_VI_NUMBER_OFST 0
9262 #define MC_CMD_DUMP_VI_STATE_OUT_OWNER_PF_OFST 0
9292 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_BUFS_BASE_LBN 0
9318 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_BUFS_BASE_LBN 0
9338 /* Reserved, currently 0. */
9348 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_BUFS_BASE_LBN 0
9361 #define MC_CMD_ALLOC_PIOBUF 0x8f
9367 #define MC_CMD_ALLOC_PIOBUF_IN_LEN 0
9372 #define MC_CMD_ALLOC_PIOBUF_OUT_PIOBUF_HANDLE_OFST 0
9379 #define MC_CMD_FREE_PIOBUF 0x90
9387 #define MC_CMD_FREE_PIOBUF_IN_PIOBUF_HANDLE_OFST 0
9391 #define MC_CMD_FREE_PIOBUF_OUT_LEN 0
9397 #define MC_CMD_GET_VI_TLP_PROCESSING 0xb0
9405 #define MC_CMD_GET_VI_TLP_PROCESSING_IN_INSTANCE_OFST 0
9411 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_TPH_TAG1_RX_OFST 0
9428 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_DATA_OFST 0
9435 #define MC_CMD_SET_VI_TLP_PROCESSING 0xb1
9443 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_INSTANCE_OFST 0
9467 #define MC_CMD_SET_VI_TLP_PROCESSING_OUT_LEN 0
9473 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS 0xbc
9480 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_OFST 0
9483 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_MISC 0x0
9485 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_IDO 0x1
9487 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_RO 0x2
9489 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_TPH_TYPE 0x3
9493 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_GLOBAL_CATEGORY_OFST 0
9500 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_MISC_WTAG_EN_LBN 0
9504 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_DL_EN_LBN 0
9514 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_RXDMA_EN_LBN 0
9522 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_MSIX_LBN 0
9539 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS 0xbd
9546 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_OFST 0
9553 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_MISC_WTAG_EN_LBN 0
9555 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_DL_EN_LBN 0
9563 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_RXDMA_EN_LBN 0
9569 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_MSIX_LBN 0
9583 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_OUT_LEN 0
9589 #define MC_CMD_SATELLITE_DOWNLOAD 0x91
9597 * 1) PHASE_RESET with a target of TARGET_ALL and chunk ID/length of 0.
9599 * 2) PHASE_IMEMS for each of the IMEM targets (target IDs 0-11). Each download
9607 * 4) PHASE_READY with a target of TARGET_ALL and chunk ID/length of 0.
9618 #define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_OFST 0
9620 #define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_IDLE 0x0 /* enum */
9621 #define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_RESET 0x1 /* enum */
9622 #define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_IMEMS 0x2 /* enum */
9623 #define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_VECTORS 0x3 /* enum */
9624 #define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_READY 0x4 /* enum */
9631 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXDI_TEXT 0x0
9633 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXDI_TEXT 0x1
9635 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXDP_TEXT 0x2
9637 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXDP_TEXT 0x3
9639 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXHRSL_HR_LUT 0x4
9641 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXHRSL_HR_LUT_CFG 0x5
9643 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXHRSL_HR_LUT 0x6
9645 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXHRSL_HR_LUT_CFG 0x7
9647 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXHRSL_HR_PGM 0x8
9649 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXHRSL_SL_PGM 0x9
9651 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXHRSL_HR_PGM 0xa
9653 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXHRSL_SL_PGM 0xb
9655 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXDI_VTBL0 0xc
9657 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXDI_VTBL0 0xd
9659 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXDI_VTBL1 0xe
9661 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXDI_VTBL1 0xf
9663 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_ALL 0xffffffff
9668 #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_ID_LAST 0xffffffff
9670 #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_ID_ABORT 0xfffffffe
9682 /* Same as MC_CMD_ERR field, but included as 0 in success cases */
9683 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_RESULT_OFST 0
9689 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_OK_COMPLETE 0x0
9691 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_OK_ABORTED 0x1
9693 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_OK_NEXT_CHUNK 0x2
9695 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_ERR_BAD_PHASE 0x100
9697 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_ERR_BAD_TARGET 0x101
9699 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_ERR_BAD_CHUNK_ID 0x200
9701 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_ERR_BAD_CHUNK_LEN 0x201
9703 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_ERR_BAD_CHECKSUM 0x300
9712 #define MC_CMD_GET_CAPABILITIES 0xbe
9718 #define MC_CMD_GET_CAPABILITIES_IN_LEN 0
9723 #define MC_CMD_GET_CAPABILITIES_OUT_FLAGS1_OFST 0
9787 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP 0x0
9789 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_LOW_LATENCY 0x1
9791 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_PACKED_STREAM 0x2
9793 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_RULES_ENGINE 0x5
9795 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_DPDK 0x6
9797 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_BIST 0x10a
9799 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH 0x101
9801 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD 0x102
9803 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST 0x103
9805 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE 0x104
9807 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_BACKPRESSURE 0x105
9809 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_PACKET_EDITS 0x106
9811 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_RX_HDR_SPLIT 0x107
9813 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_DISABLE_DL 0x108
9815 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_DOORBELL_DELAY 0x10b
9817 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_SLOW 0x10c
9822 #define MC_CMD_GET_CAPABILITIES_OUT_TXDP 0x0
9824 #define MC_CMD_GET_CAPABILITIES_OUT_TXDP_LOW_LATENCY 0x1
9826 #define MC_CMD_GET_CAPABILITIES_OUT_TXDP_HIGH_PACKET_RATE 0x3
9828 #define MC_CMD_GET_CAPABILITIES_OUT_TXDP_RULES_ENGINE 0x5
9830 #define MC_CMD_GET_CAPABILITIES_OUT_TXDP_DPDK 0x6
9832 #define MC_CMD_GET_CAPABILITIES_OUT_TXDP_BIST 0x12d
9834 #define MC_CMD_GET_CAPABILITIES_OUT_TXDP_TEST_FW_TSO_EDIT 0x101
9836 #define MC_CMD_GET_CAPABILITIES_OUT_TXDP_TEST_FW_PACKET_EDITS 0x102
9838 #define MC_CMD_GET_CAPABILITIES_OUT_TXDP_TEST_FW_CSR 0x103
9841 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_REV_LBN 0
9848 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_RESERVED 0x0
9852 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_FIRST_PKT 0x1
9856 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_SIENA_COMPAT 0x2
9858 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_FULL_FEATURED 0x3
9860 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_VSWITCH 0x3
9864 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
9866 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_LOW_LATENCY 0x5
9868 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_PACKED_STREAM 0x6
9872 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_LAYER2_PERF 0x7
9874 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_RULES_ENGINE 0x8
9876 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_L3XUDP 0x9
9878 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_DPDK 0xa
9880 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
9884 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf
9887 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_REV_LBN 0
9894 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_RESERVED 0x0
9898 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_FIRST_PKT 0x1
9902 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_SIENA_COMPAT 0x2
9904 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_FULL_FEATURED 0x3
9906 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_VSWITCH 0x3
9910 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
9911 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */
9915 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_LAYER2_PERF 0x7
9917 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_RULES_ENGINE 0x8
9919 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_L3XUDP 0x9
9921 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_DPDK 0xa
9923 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
9932 #define MC_CMD_GET_CAPABILITIES_V2_IN_LEN 0
9937 #define MC_CMD_GET_CAPABILITIES_V2_OUT_FLAGS1_OFST 0
10001 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP 0x0
10003 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_LOW_LATENCY 0x1
10005 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_PACKED_STREAM 0x2
10007 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_RULES_ENGINE 0x5
10009 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_DPDK 0x6
10011 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_BIST 0x10a
10013 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH 0x101
10015 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD 0x102
10017 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST 0x103
10019 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE 0x104
10021 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_BACKPRESSURE 0x105
10023 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_PACKET_EDITS 0x106
10025 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_RX_HDR_SPLIT 0x107
10027 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_DISABLE_DL 0x108
10029 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_DOORBELL_DELAY 0x10b
10031 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_SLOW 0x10c
10036 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP 0x0
10038 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_LOW_LATENCY 0x1
10040 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_HIGH_PACKET_RATE 0x3
10042 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_RULES_ENGINE 0x5
10044 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_DPDK 0x6
10046 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_BIST 0x12d
10048 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_TEST_FW_TSO_EDIT 0x101
10050 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_TEST_FW_PACKET_EDITS 0x102
10052 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_TEST_FW_CSR 0x103
10055 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_VERSION_REV_LBN 0
10062 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_RESERVED 0x0
10066 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_FIRST_PKT 0x1
10070 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_SIENA_COMPAT 0x2
10072 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_FULL_FEATURED 0x3
10074 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_VSWITCH 0x3
10078 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
10080 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_LOW_LATENCY 0x5
10082 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_PACKED_STREAM 0x6
10086 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_LAYER2_PERF 0x7
10088 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_RULES_ENGINE 0x8
10090 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_L3XUDP 0x9
10092 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_DPDK 0xa
10094 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
10098 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf
10101 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_VERSION_REV_LBN 0
10108 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_RESERVED 0x0
10112 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_FIRST_PKT 0x1
10116 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_SIENA_COMPAT 0x2
10118 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_FULL_FEATURED 0x3
10120 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_VSWITCH 0x3
10124 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
10125 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */
10129 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_LAYER2_PERF 0x7
10131 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_RULES_ENGINE 0x8
10133 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_L3XUDP 0x9
10135 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_DPDK 0xa
10137 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
10147 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_LBN 0
10214 #define MC_CMD_GET_CAPABILITIES_V2_OUT_ACCESS_NOT_PERMITTED 0xff
10216 #define MC_CMD_GET_CAPABILITIES_V2_OUT_PF_NOT_PRESENT 0xfe
10218 #define MC_CMD_GET_CAPABILITIES_V2_OUT_PF_NOT_ASSIGNED 0xfd
10225 #define MC_CMD_GET_CAPABILITIES_V2_OUT_INCOMPATIBLE_ASSIGNMENT 0xfc
10233 /* MC_CMD_GET_CAPABILITIES_V2_OUT_ACCESS_NOT_PERMITTED 0xff */
10235 /* MC_CMD_GET_CAPABILITIES_V2_OUT_PF_NOT_PRESENT 0xfe */
10260 #define MC_CMD_GET_CAPABILITIES_V3_OUT_FLAGS1_OFST 0
10324 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP 0x0
10326 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_LOW_LATENCY 0x1
10328 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_PACKED_STREAM 0x2
10330 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_RULES_ENGINE 0x5
10332 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_DPDK 0x6
10334 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_BIST 0x10a
10336 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH 0x101
10338 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD 0x102
10340 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST 0x103
10342 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE 0x104
10344 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_BACKPRESSURE 0x105
10346 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_PACKET_EDITS 0x106
10348 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_RX_HDR_SPLIT 0x107
10350 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_DISABLE_DL 0x108
10352 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_DOORBELL_DELAY 0x10b
10354 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_SLOW 0x10c
10359 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP 0x0
10361 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_LOW_LATENCY 0x1
10363 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_HIGH_PACKET_RATE 0x3
10365 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_RULES_ENGINE 0x5
10367 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_DPDK 0x6
10369 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_BIST 0x12d
10371 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_TEST_FW_TSO_EDIT 0x101
10373 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_TEST_FW_PACKET_EDITS 0x102
10375 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_TEST_FW_CSR 0x103
10378 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_VERSION_REV_LBN 0
10385 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_RESERVED 0x0
10389 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_FIRST_PKT 0x1
10393 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_SIENA_COMPAT 0x2
10395 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_FULL_FEATURED 0x3
10397 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_VSWITCH 0x3
10401 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
10403 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_LOW_LATENCY 0x5
10405 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_PACKED_STREAM 0x6
10409 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_LAYER2_PERF 0x7
10411 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_RULES_ENGINE 0x8
10413 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_L3XUDP 0x9
10415 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_DPDK 0xa
10417 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
10421 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf
10424 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_VERSION_REV_LBN 0
10431 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_RESERVED 0x0
10435 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_FIRST_PKT 0x1
10439 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_SIENA_COMPAT 0x2
10441 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_FULL_FEATURED 0x3
10443 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_VSWITCH 0x3
10447 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
10448 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */
10452 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_LAYER2_PERF 0x7
10454 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_RULES_ENGINE 0x8
10456 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_L3XUDP 0x9
10458 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_DPDK 0xa
10460 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
10470 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_V2_LBN 0
10537 #define MC_CMD_GET_CAPABILITIES_V3_OUT_ACCESS_NOT_PERMITTED 0xff
10539 #define MC_CMD_GET_CAPABILITIES_V3_OUT_PF_NOT_PRESENT 0xfe
10541 #define MC_CMD_GET_CAPABILITIES_V3_OUT_PF_NOT_ASSIGNED 0xfd
10548 #define MC_CMD_GET_CAPABILITIES_V3_OUT_INCOMPATIBLE_ASSIGNMENT 0xfc
10556 /* MC_CMD_GET_CAPABILITIES_V3_OUT_ACCESS_NOT_PERMITTED 0xff */
10558 /* MC_CMD_GET_CAPABILITIES_V3_OUT_PF_NOT_PRESENT 0xfe */
10589 #define MC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_8K 0x0
10591 #define MC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_16K 0x1
10593 #define MC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_64K 0x2
10608 #define MC_CMD_GET_CAPABILITIES_V4_OUT_FLAGS1_OFST 0
10672 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP 0x0
10674 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_LOW_LATENCY 0x1
10676 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_PACKED_STREAM 0x2
10678 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_RULES_ENGINE 0x5
10680 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_DPDK 0x6
10682 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_BIST 0x10a
10684 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH 0x101
10686 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD 0x102
10688 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST 0x103
10690 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE 0x104
10692 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_BACKPRESSURE 0x105
10694 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_FW_PACKET_EDITS 0x106
10696 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_FW_RX_HDR_SPLIT 0x107
10698 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_FW_DISABLE_DL 0x108
10700 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_FW_DOORBELL_DELAY 0x10b
10702 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_FW_SLOW 0x10c
10707 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXDP 0x0
10709 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXDP_LOW_LATENCY 0x1
10711 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXDP_HIGH_PACKET_RATE 0x3
10713 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXDP_RULES_ENGINE 0x5
10715 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXDP_DPDK 0x6
10717 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXDP_BIST 0x12d
10719 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXDP_TEST_FW_TSO_EDIT 0x101
10721 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXDP_TEST_FW_PACKET_EDITS 0x102
10723 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXDP_TEST_FW_CSR 0x103
10726 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_VERSION_REV_LBN 0
10733 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_RESERVED 0x0
10737 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_FIRST_PKT 0x1
10741 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_SIENA_COMPAT 0x2
10743 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_FULL_FEATURED 0x3
10745 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_VSWITCH 0x3
10749 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
10751 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_LOW_LATENCY 0x5
10753 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_PACKED_STREAM 0x6
10757 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_LAYER2_PERF 0x7
10759 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_RULES_ENGINE 0x8
10761 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_L3XUDP 0x9
10763 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_DPDK 0xa
10765 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
10769 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf
10772 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_VERSION_REV_LBN 0
10779 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_RESERVED 0x0
10783 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_FIRST_PKT 0x1
10787 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_SIENA_COMPAT 0x2
10789 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_FULL_FEATURED 0x3
10791 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_VSWITCH 0x3
10795 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
10796 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */
10800 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_LAYER2_PERF 0x7
10802 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_RULES_ENGINE 0x8
10804 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_L3XUDP 0x9
10806 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_DPDK 0xa
10808 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
10818 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_V2_LBN 0
10885 #define MC_CMD_GET_CAPABILITIES_V4_OUT_ACCESS_NOT_PERMITTED 0xff
10887 #define MC_CMD_GET_CAPABILITIES_V4_OUT_PF_NOT_PRESENT 0xfe
10889 #define MC_CMD_GET_CAPABILITIES_V4_OUT_PF_NOT_ASSIGNED 0xfd
10896 #define MC_CMD_GET_CAPABILITIES_V4_OUT_INCOMPATIBLE_ASSIGNMENT 0xfc
10904 /* MC_CMD_GET_CAPABILITIES_V4_OUT_ACCESS_NOT_PERMITTED 0xff */
10906 /* MC_CMD_GET_CAPABILITIES_V4_OUT_PF_NOT_PRESENT 0xfe */
10937 #define MC_CMD_GET_CAPABILITIES_V4_OUT_VI_WINDOW_MODE_8K 0x0
10939 #define MC_CMD_GET_CAPABILITIES_V4_OUT_VI_WINDOW_MODE_16K 0x1
10941 #define MC_CMD_GET_CAPABILITIES_V4_OUT_VI_WINDOW_MODE_64K 0x2
10964 #define MC_CMD_GET_CAPABILITIES_V5_OUT_FLAGS1_OFST 0
11028 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP 0x0
11030 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_LOW_LATENCY 0x1
11032 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_PACKED_STREAM 0x2
11034 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_RULES_ENGINE 0x5
11036 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_DPDK 0x6
11038 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_BIST 0x10a
11040 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH 0x101
11042 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD 0x102
11044 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST 0x103
11046 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE 0x104
11048 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_TEST_BACKPRESSURE 0x105
11050 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_TEST_FW_PACKET_EDITS 0x106
11052 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_TEST_FW_RX_HDR_SPLIT 0x107
11054 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_TEST_FW_DISABLE_DL 0x108
11056 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_TEST_FW_DOORBELL_DELAY 0x10b
11058 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_TEST_FW_SLOW 0x10c
11063 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TXDP 0x0
11065 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TXDP_LOW_LATENCY 0x1
11067 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TXDP_HIGH_PACKET_RATE 0x3
11069 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TXDP_RULES_ENGINE 0x5
11071 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TXDP_DPDK 0x6
11073 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TXDP_BIST 0x12d
11075 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TXDP_TEST_FW_TSO_EDIT 0x101
11077 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TXDP_TEST_FW_PACKET_EDITS 0x102
11079 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TXDP_TEST_FW_CSR 0x103
11082 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_VERSION_REV_LBN 0
11089 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_RESERVED 0x0
11093 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_FIRST_PKT 0x1
11097 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_SIENA_COMPAT 0x2
11099 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_FULL_FEATURED 0x3
11101 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_VSWITCH 0x3
11105 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
11107 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_LOW_LATENCY 0x5
11109 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_PACKED_STREAM 0x6
11113 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_LAYER2_PERF 0x7
11115 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_RULES_ENGINE 0x8
11117 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_L3XUDP 0x9
11119 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_DPDK 0xa
11121 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
11125 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf
11128 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_VERSION_REV_LBN 0
11135 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_TYPE_RESERVED 0x0
11139 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_TYPE_FIRST_PKT 0x1
11143 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_TYPE_SIENA_COMPAT 0x2
11145 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_TYPE_FULL_FEATURED 0x3
11147 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_TYPE_VSWITCH 0x3
11151 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
11152 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */
11156 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_TYPE_LAYER2_PERF 0x7
11158 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_TYPE_RULES_ENGINE 0x8
11160 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_TYPE_L3XUDP 0x9
11162 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_TYPE_DPDK 0xa
11164 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
11174 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_TSO_V2_LBN 0
11241 #define MC_CMD_GET_CAPABILITIES_V5_OUT_ACCESS_NOT_PERMITTED 0xff
11243 #define MC_CMD_GET_CAPABILITIES_V5_OUT_PF_NOT_PRESENT 0xfe
11245 #define MC_CMD_GET_CAPABILITIES_V5_OUT_PF_NOT_ASSIGNED 0xfd
11252 #define MC_CMD_GET_CAPABILITIES_V5_OUT_INCOMPATIBLE_ASSIGNMENT 0xfc
11260 /* MC_CMD_GET_CAPABILITIES_V5_OUT_ACCESS_NOT_PERMITTED 0xff */
11262 /* MC_CMD_GET_CAPABILITIES_V5_OUT_PF_NOT_PRESENT 0xfe */
11293 #define MC_CMD_GET_CAPABILITIES_V5_OUT_VI_WINDOW_MODE_8K 0x0
11295 #define MC_CMD_GET_CAPABILITIES_V5_OUT_VI_WINDOW_MODE_16K 0x1
11297 #define MC_CMD_GET_CAPABILITIES_V5_OUT_VI_WINDOW_MODE_64K 0x2
11326 #define MC_CMD_V2_EXTN 0x7f
11331 #define MC_CMD_V2_EXTN_IN_EXTENDED_CMD_LBN 0
11346 #define MC_CMD_V2_EXTN_IN_MCDI_MESSAGE_TYPE_MC 0x0
11350 #define MC_CMD_V2_EXTN_IN_MCDI_MESSAGE_TYPE_TSA 0x1
11356 #define MC_CMD_TCM_BUCKET_ALLOC 0xb2
11362 #define MC_CMD_TCM_BUCKET_ALLOC_IN_LEN 0
11367 #define MC_CMD_TCM_BUCKET_ALLOC_OUT_BUCKET_OFST 0
11374 #define MC_CMD_TCM_BUCKET_FREE 0xb3
11382 #define MC_CMD_TCM_BUCKET_FREE_IN_BUCKET_OFST 0
11386 #define MC_CMD_TCM_BUCKET_FREE_OUT_LEN 0
11392 #define MC_CMD_TCM_BUCKET_INIT 0xb4
11400 #define MC_CMD_TCM_BUCKET_INIT_IN_BUCKET_OFST 0
11409 #define MC_CMD_TCM_BUCKET_INIT_EXT_IN_BUCKET_OFST 0
11419 #define MC_CMD_TCM_BUCKET_INIT_OUT_LEN 0
11425 #define MC_CMD_TCM_TXQ_INIT 0xb5
11433 #define MC_CMD_TCM_TXQ_INIT_IN_QID_OFST 0
11441 #define MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAG_GUARANTEED_LBN 0
11467 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_QID_OFST 0
11475 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAG_GUARANTEED_LBN 0
11502 #define MC_CMD_TCM_TXQ_INIT_OUT_LEN 0
11508 #define MC_CMD_LINK_PIOBUF 0x92
11516 #define MC_CMD_LINK_PIOBUF_IN_PIOBUF_HANDLE_OFST 0
11523 #define MC_CMD_LINK_PIOBUF_OUT_LEN 0
11529 #define MC_CMD_UNLINK_PIOBUF 0x93
11537 #define MC_CMD_UNLINK_PIOBUF_IN_TXQ_INSTANCE_OFST 0
11541 #define MC_CMD_UNLINK_PIOBUF_OUT_LEN 0
11547 #define MC_CMD_VSWITCH_ALLOC 0x94
11555 #define MC_CMD_VSWITCH_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0
11561 #define MC_CMD_VSWITCH_ALLOC_IN_VSWITCH_TYPE_VLAN 0x1
11563 #define MC_CMD_VSWITCH_ALLOC_IN_VSWITCH_TYPE_VEB 0x2
11565 #define MC_CMD_VSWITCH_ALLOC_IN_VSWITCH_TYPE_VEPA 0x3
11567 #define MC_CMD_VSWITCH_ALLOC_IN_VSWITCH_TYPE_MUX 0x4
11569 #define MC_CMD_VSWITCH_ALLOC_IN_VSWITCH_TYPE_TEST 0x5
11573 #define MC_CMD_VSWITCH_ALLOC_IN_FLAG_AUTO_PORT_LBN 0
11586 #define MC_CMD_VSWITCH_ALLOC_OUT_LEN 0
11592 #define MC_CMD_VSWITCH_FREE 0x95
11600 #define MC_CMD_VSWITCH_FREE_IN_UPSTREAM_PORT_ID_OFST 0
11604 #define MC_CMD_VSWITCH_FREE_OUT_LEN 0
11612 #define MC_CMD_VSWITCH_QUERY 0x63
11620 #define MC_CMD_VSWITCH_QUERY_IN_UPSTREAM_PORT_ID_OFST 0
11624 #define MC_CMD_VSWITCH_QUERY_OUT_LEN 0
11630 #define MC_CMD_VPORT_ALLOC 0x96
11638 #define MC_CMD_VPORT_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0
11644 #define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_VLAN 0x1
11646 #define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_VEB 0x2
11648 #define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_VEPA 0x3
11652 #define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_NORMAL 0x4
11656 #define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_EXPANSION 0x5
11660 #define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_TEST 0x6
11664 #define MC_CMD_VPORT_ALLOC_IN_FLAG_AUTO_PORT_LBN 0
11677 #define MC_CMD_VPORT_ALLOC_IN_VLAN_TAG_0_LBN 0
11685 #define MC_CMD_VPORT_ALLOC_OUT_VPORT_ID_OFST 0
11692 #define MC_CMD_VPORT_FREE 0x97
11700 #define MC_CMD_VPORT_FREE_IN_VPORT_ID_OFST 0
11704 #define MC_CMD_VPORT_FREE_OUT_LEN 0
11710 #define MC_CMD_VADAPTOR_ALLOC 0x98
11718 #define MC_CMD_VADAPTOR_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0
11723 #define MC_CMD_VADAPTOR_ALLOC_IN_FLAG_AUTO_VADAPTOR_LBN 0
11736 #define MC_CMD_VADAPTOR_ALLOC_IN_VLAN_TAG_0_LBN 0
11744 #define MC_CMD_VADAPTOR_ALLOC_IN_AUTO_MAC 0x0
11747 #define MC_CMD_VADAPTOR_ALLOC_OUT_LEN 0
11753 #define MC_CMD_VADAPTOR_FREE 0x99
11761 #define MC_CMD_VADAPTOR_FREE_IN_UPSTREAM_PORT_ID_OFST 0
11765 #define MC_CMD_VADAPTOR_FREE_OUT_LEN 0
11771 #define MC_CMD_VADAPTOR_SET_MAC 0x5d
11779 #define MC_CMD_VADAPTOR_SET_MAC_IN_UPSTREAM_PORT_ID_OFST 0
11786 #define MC_CMD_VADAPTOR_SET_MAC_OUT_LEN 0
11792 #define MC_CMD_VADAPTOR_GET_MAC 0x5e
11800 #define MC_CMD_VADAPTOR_GET_MAC_IN_UPSTREAM_PORT_ID_OFST 0
11806 #define MC_CMD_VADAPTOR_GET_MAC_OUT_MACADDR_OFST 0
11813 #define MC_CMD_VADAPTOR_QUERY 0x61
11821 #define MC_CMD_VADAPTOR_QUERY_IN_UPSTREAM_PORT_ID_OFST 0
11827 #define MC_CMD_VADAPTOR_QUERY_OUT_PORT_FLAGS_OFST 0
11840 #define MC_CMD_EVB_PORT_ASSIGN 0x9a
11848 #define MC_CMD_EVB_PORT_ASSIGN_IN_PORT_ID_OFST 0
11853 #define MC_CMD_EVB_PORT_ASSIGN_IN_PF_LBN 0
11859 #define MC_CMD_EVB_PORT_ASSIGN_OUT_LEN 0
11865 #define MC_CMD_RDWR_A64_REGIONS 0x9b
11872 #define MC_CMD_RDWR_A64_REGIONS_IN_REGION0_OFST 0
11880 /* Write enable bits 0-3, set to write, clear to read. */
11890 #define MC_CMD_RDWR_A64_REGIONS_OUT_REGION0_OFST 0
11903 #define MC_CMD_ONLOAD_STACK_ALLOC 0x9c
11911 #define MC_CMD_ONLOAD_STACK_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0
11917 #define MC_CMD_ONLOAD_STACK_ALLOC_OUT_ONLOAD_STACK_ID_OFST 0
11924 #define MC_CMD_ONLOAD_STACK_FREE 0x9d
11932 #define MC_CMD_ONLOAD_STACK_FREE_IN_ONLOAD_STACK_ID_OFST 0
11936 #define MC_CMD_ONLOAD_STACK_FREE_OUT_LEN 0
11942 #define MC_CMD_RSS_CONTEXT_ALLOC 0x9e
11950 #define MC_CMD_RSS_CONTEXT_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0
11958 #define MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_EXCLUSIVE 0x0
11963 #define MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_SHARED 0x1
11965 * in the indirection table will be in the range 0 to NUM_QUEUES-1.
11973 * host, although a value of 0xFFFFFFFF is guaranteed never to be a valid
11976 #define MC_CMD_RSS_CONTEXT_ALLOC_OUT_RSS_CONTEXT_ID_OFST 0
11979 #define MC_CMD_RSS_CONTEXT_ALLOC_OUT_RSS_CONTEXT_ID_INVALID 0xffffffff
11985 #define MC_CMD_RSS_CONTEXT_FREE 0x9f
11993 #define MC_CMD_RSS_CONTEXT_FREE_IN_RSS_CONTEXT_ID_OFST 0
11997 #define MC_CMD_RSS_CONTEXT_FREE_OUT_LEN 0
12003 #define MC_CMD_RSS_CONTEXT_SET_KEY 0xa0
12011 #define MC_CMD_RSS_CONTEXT_SET_KEY_IN_RSS_CONTEXT_ID_OFST 0
12018 #define MC_CMD_RSS_CONTEXT_SET_KEY_OUT_LEN 0
12024 #define MC_CMD_RSS_CONTEXT_GET_KEY 0xa1
12032 #define MC_CMD_RSS_CONTEXT_GET_KEY_IN_RSS_CONTEXT_ID_OFST 0
12045 #define MC_CMD_RSS_CONTEXT_SET_TABLE 0xa2
12053 #define MC_CMD_RSS_CONTEXT_SET_TABLE_IN_RSS_CONTEXT_ID_OFST 0
12060 #define MC_CMD_RSS_CONTEXT_SET_TABLE_OUT_LEN 0
12066 #define MC_CMD_RSS_CONTEXT_GET_TABLE 0xa3
12074 #define MC_CMD_RSS_CONTEXT_GET_TABLE_IN_RSS_CONTEXT_ID_OFST 0
12087 #define MC_CMD_RSS_CONTEXT_SET_FLAGS 0xe1
12095 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_RSS_CONTEXT_ID_OFST 0
12103 * reject any attempt to set the FLAGS field to a value > 0xff with EINVAL. In
12111 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_IPV4_EN_LBN 0
12135 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_OUT_LEN 0
12141 #define MC_CMD_RSS_CONTEXT_GET_FLAGS 0xe2
12149 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_IN_RSS_CONTEXT_ID_OFST 0
12169 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV4_EN_LBN 0
12196 #define MC_CMD_DOT1P_MAPPING_ALLOC 0xa4
12204 #define MC_CMD_DOT1P_MAPPING_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0
12207 * offsets in the mapping table will be in the range 0 to NUM_QUEUES-1, and
12216 * host, although a value of 0xFFFFFFFF is guaranteed never to be a valid
12219 #define MC_CMD_DOT1P_MAPPING_ALLOC_OUT_DOT1P_MAPPING_ID_OFST 0
12222 #define MC_CMD_DOT1P_MAPPING_ALLOC_OUT_DOT1P_MAPPING_ID_INVALID 0xffffffff
12228 #define MC_CMD_DOT1P_MAPPING_FREE 0xa5
12236 #define MC_CMD_DOT1P_MAPPING_FREE_IN_DOT1P_MAPPING_ID_OFST 0
12240 #define MC_CMD_DOT1P_MAPPING_FREE_OUT_LEN 0
12246 #define MC_CMD_DOT1P_MAPPING_SET_TABLE 0xa6
12254 #define MC_CMD_DOT1P_MAPPING_SET_TABLE_IN_DOT1P_MAPPING_ID_OFST 0
12263 #define MC_CMD_DOT1P_MAPPING_SET_TABLE_OUT_LEN 0
12269 #define MC_CMD_DOT1P_MAPPING_GET_TABLE 0xa7
12277 #define MC_CMD_DOT1P_MAPPING_GET_TABLE_IN_DOT1P_MAPPING_ID_OFST 0
12292 #define MC_CMD_GET_VECTOR_CFG 0xbf
12298 #define MC_CMD_GET_VECTOR_CFG_IN_LEN 0
12303 #define MC_CMD_GET_VECTOR_CFG_OUT_VEC_BASE_OFST 0
12316 #define MC_CMD_SET_VECTOR_CFG 0xc0
12326 #define MC_CMD_SET_VECTOR_CFG_IN_VEC_BASE_OFST 0
12336 #define MC_CMD_SET_VECTOR_CFG_OUT_LEN 0
12342 #define MC_CMD_VPORT_ADD_MAC_ADDRESS 0xa8
12350 #define MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_VPORT_ID_OFST 0
12357 #define MC_CMD_VPORT_ADD_MAC_ADDRESS_OUT_LEN 0
12363 #define MC_CMD_VPORT_DEL_MAC_ADDRESS 0xa9
12371 #define MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_VPORT_ID_OFST 0
12378 #define MC_CMD_VPORT_DEL_MAC_ADDRESS_OUT_LEN 0
12384 #define MC_CMD_VPORT_GET_MAC_ADDRESSES 0xaa
12392 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_VPORT_ID_OFST 0
12400 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_COUNT_OFST 0
12405 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_MINNUM 0
12414 #define MC_CMD_VPORT_RECONFIGURE 0xeb
12422 #define MC_CMD_VPORT_RECONFIGURE_IN_VPORT_ID_OFST 0
12427 #define MC_CMD_VPORT_RECONFIGURE_IN_REPLACE_VLAN_TAGS_LBN 0
12440 #define MC_CMD_VPORT_RECONFIGURE_IN_VLAN_TAG_0_LBN 0
12454 #define MC_CMD_VPORT_RECONFIGURE_OUT_FLAGS_OFST 0
12456 #define MC_CMD_VPORT_RECONFIGURE_OUT_RESET_DONE_LBN 0
12463 #define MC_CMD_EVB_PORT_QUERY 0x62
12471 #define MC_CMD_EVB_PORT_QUERY_IN_PORT_ID_OFST 0
12477 #define MC_CMD_EVB_PORT_QUERY_OUT_PORT_FLAGS_OFST 0
12492 #define MC_CMD_DUMP_BUFTBL_ENTRIES 0xab
12500 #define MC_CMD_DUMP_BUFTBL_ENTRIES_IN_FIRSTID_OFST 0
12509 #define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_LEN(num) (0+12*(num))
12511 #define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_ENTRY_OFST 0
12520 #define MC_CMD_SET_RXDP_CONFIG 0xc1
12527 #define MC_CMD_SET_RXDP_CONFIG_IN_DATA_OFST 0
12529 #define MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_DMA_LBN 0
12534 #define MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_64 0x0
12536 #define MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_128 0x1
12538 #define MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_256 0x2
12541 #define MC_CMD_SET_RXDP_CONFIG_OUT_LEN 0
12547 #define MC_CMD_GET_RXDP_CONFIG 0xc2
12553 #define MC_CMD_GET_RXDP_CONFIG_IN_LEN 0
12557 #define MC_CMD_GET_RXDP_CONFIG_OUT_DATA_OFST 0
12559 #define MC_CMD_GET_RXDP_CONFIG_OUT_PAD_HOST_DMA_LBN 0
12570 #define MC_CMD_GET_CLOCK 0xac
12576 #define MC_CMD_GET_CLOCK_IN_LEN 0
12581 #define MC_CMD_GET_CLOCK_OUT_SYS_FREQ_OFST 0
12591 #define MC_CMD_SET_CLOCK 0xad
12599 #define MC_CMD_SET_CLOCK_IN_SYS_FREQ_OFST 0
12602 #define MC_CMD_SET_CLOCK_IN_SYS_DOMAIN_DONT_CHANGE 0x0
12607 #define MC_CMD_SET_CLOCK_IN_ICORE_DOMAIN_DONT_CHANGE 0x0
12612 #define MC_CMD_SET_CLOCK_IN_DPCPU_DOMAIN_DONT_CHANGE 0x0
12617 #define MC_CMD_SET_CLOCK_IN_PCS_DOMAIN_DONT_CHANGE 0x0
12622 #define MC_CMD_SET_CLOCK_IN_MC_DOMAIN_DONT_CHANGE 0x0
12627 #define MC_CMD_SET_CLOCK_IN_RMON_DOMAIN_DONT_CHANGE 0x0
12632 #define MC_CMD_SET_CLOCK_IN_VSWITCH_DOMAIN_DONT_CHANGE 0x0
12637 #define MC_CMD_SET_CLOCK_OUT_SYS_FREQ_OFST 0
12640 #define MC_CMD_SET_CLOCK_OUT_SYS_DOMAIN_UNSUPPORTED 0x0
12645 #define MC_CMD_SET_CLOCK_OUT_ICORE_DOMAIN_UNSUPPORTED 0x0
12650 #define MC_CMD_SET_CLOCK_OUT_DPCPU_DOMAIN_UNSUPPORTED 0x0
12655 #define MC_CMD_SET_CLOCK_OUT_PCS_DOMAIN_UNSUPPORTED 0x0
12660 #define MC_CMD_SET_CLOCK_OUT_MC_DOMAIN_UNSUPPORTED 0x0
12665 #define MC_CMD_SET_CLOCK_OUT_RMON_DOMAIN_UNSUPPORTED 0x0
12670 #define MC_CMD_SET_CLOCK_OUT_VSWITCH_DOMAIN_UNSUPPORTED 0x0
12676 #define MC_CMD_DPCPU_RPC 0xae
12683 #define MC_CMD_DPCPU_RPC_IN_CPU_OFST 0
12686 #define MC_CMD_DPCPU_RPC_IN_DPCPU_RX0 0x0
12688 #define MC_CMD_DPCPU_RPC_IN_DPCPU_TX0 0x1
12690 #define MC_CMD_DPCPU_RPC_IN_DPCPU_TX1 0x2
12692 #define MC_CMD_DPCPU_RPC_IN_DPCPU_RX1 0x3
12696 #define MC_CMD_DPCPU_RPC_IN_DPCPU_RX 0x80
12700 #define MC_CMD_DPCPU_RPC_IN_DPCPU_TX 0x81
12708 #define MC_CMD_DPCPU_RPC_IN_CMDNUM_TXDPCPU_READ 0x6 /* enum */
12709 #define MC_CMD_DPCPU_RPC_IN_CMDNUM_TXDPCPU_WRITE 0x7 /* enum */
12710 #define MC_CMD_DPCPU_RPC_IN_CMDNUM_TXDPCPU_SELF_TEST 0xc /* enum */
12711 #define MC_CMD_DPCPU_RPC_IN_CMDNUM_TXDPCPU_CSR_ACCESS 0xe /* enum */
12712 #define MC_CMD_DPCPU_RPC_IN_CMDNUM_RXDPCPU_READ 0x46 /* enum */
12713 #define MC_CMD_DPCPU_RPC_IN_CMDNUM_RXDPCPU_WRITE 0x47 /* enum */
12714 #define MC_CMD_DPCPU_RPC_IN_CMDNUM_RXDPCPU_SELF_TEST 0x4a /* enum */
12715 #define MC_CMD_DPCPU_RPC_IN_CMDNUM_RXDPCPU_CSR_ACCESS 0x4c /* enum */
12716 #define MC_CMD_DPCPU_RPC_IN_CMDNUM_RXDPCPU_SET_MC_REPLAY_CNTXT 0x4d /* enum */
12727 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_STOP_RETURN_RESULT 0x0 /* enum */
12728 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_START_READ 0x1 /* enum */
12729 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_START_WRITE 0x2 /* enum */
12730 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_START_WRITE_READ 0x3 /* enum */
12731 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_START_PIPELINED_READ 0x4 /* enum */
12740 #define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_MODE_CUT_THROUGH 0x1 /* enum */
12741 #define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_MODE_STORE_FORWARD 0x2 /* enum */
12742 #define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_MODE_STORE_FORWARD_FIRST 0x3 /* enum */
12756 #define MC_CMD_DPCPU_RPC_OUT_RC_OFST 0
12780 #define MC_CMD_TRIGGER_INTERRUPT 0xe3
12788 #define MC_CMD_TRIGGER_INTERRUPT_IN_INTR_LEVEL_OFST 0
12792 #define MC_CMD_TRIGGER_INTERRUPT_OUT_LEN 0
12798 #define MC_CMD_SHMBOOT_OP 0xe6
12806 #define MC_CMD_SHMBOOT_OP_IN_SHMBOOT_OP_OFST 0
12809 #define MC_CMD_SHMBOOT_OP_IN_PUSH_SLAVE_DATA 0x0
12812 #define MC_CMD_SHMBOOT_OP_OUT_LEN 0
12818 #define MC_CMD_CAP_BLK_READ 0xe7
12825 #define MC_CMD_CAP_BLK_READ_IN_CAP_REG_OFST 0
12835 #define MC_CMD_CAP_BLK_READ_OUT_LEN(num) (0+8*(num))
12836 #define MC_CMD_CAP_BLK_READ_OUT_BUFFER_OFST 0
12838 #define MC_CMD_CAP_BLK_READ_OUT_BUFFER_LO_OFST 0
12847 #define MC_CMD_DUMP_DO 0xe8
12854 #define MC_CMD_DUMP_DO_IN_PADDING_OFST 0
12858 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM 0x0 /* enum */
12859 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_DEFAULT 0x1 /* enum */
12862 #define MC_CMD_DUMP_DO_IN_DUMP_LOCATION_NVRAM 0x1 /* enum */
12863 #define MC_CMD_DUMP_DO_IN_DUMP_LOCATION_HOST_MEMORY 0x2 /* enum */
12864 #define MC_CMD_DUMP_DO_IN_DUMP_LOCATION_HOST_MEMORY_MLI 0x3 /* enum */
12865 #define MC_CMD_DUMP_DO_IN_DUMP_LOCATION_UART 0x4 /* enum */
12876 #define MC_CMD_DUMP_DO_IN_HOST_MEMORY_MLI_PAGE_SIZE 0x1000 /* enum */
12881 #define MC_CMD_DUMP_DO_IN_HOST_MEMORY_MLI_MAX_DEPTH 0x2 /* enum */
12887 #define MC_CMD_DUMP_DO_IN_UART_PORT_SRC 0xff
12892 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM 0x0 /* enum */
12893 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_NVRAM_DUMP_PARTITION 0x1 /* enum */
12919 #define MC_CMD_DUMP_DO_OUT_DUMPFILE_SIZE_OFST 0
12926 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED 0xe9
12933 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_ENABLE_OFST 0
12994 #define MC_CMD_SET_PSU 0xea
13001 #define MC_CMD_SET_PSU_IN_PARAM_OFST 0
13003 #define MC_CMD_SET_PSU_IN_PARAM_SUPPLY_VOLTAGE 0x0 /* enum */
13006 #define MC_CMD_SET_PSU_IN_RAIL_0V9 0x0 /* enum */
13007 #define MC_CMD_SET_PSU_IN_RAIL_1V2 0x1 /* enum */
13013 #define MC_CMD_SET_PSU_OUT_LEN 0
13019 #define MC_CMD_GET_FUNCTION_INFO 0xec
13025 #define MC_CMD_GET_FUNCTION_INFO_IN_LEN 0
13029 #define MC_CMD_GET_FUNCTION_INFO_OUT_PF_OFST 0
13040 #define MC_CMD_ENABLE_OFFLINE_BIST 0xed
13046 #define MC_CMD_ENABLE_OFFLINE_BIST_IN_LEN 0
13049 #define MC_CMD_ENABLE_OFFLINE_BIST_OUT_LEN 0
13057 #define MC_CMD_UART_SEND_DATA 0xee
13067 #define MC_CMD_UART_SEND_DATA_OUT_CHECKSUM_OFST 0
13080 #define MC_CMD_UART_SEND_DATA_OUT_DATA_MINNUM 0
13084 #define MC_CMD_UART_SEND_DATA_IN_LEN 0
13091 #define MC_CMD_UART_RECV_DATA 0xef
13099 #define MC_CMD_UART_RECV_DATA_OUT_CHECKSUM_OFST 0
13116 #define MC_CMD_UART_RECV_DATA_IN_CHECKSUM_OFST 0
13129 #define MC_CMD_UART_RECV_DATA_IN_DATA_MINNUM 0
13136 #define MC_CMD_READ_FUSES 0xf0
13144 #define MC_CMD_READ_FUSES_IN_OFFSET_OFST 0
13155 #define MC_CMD_READ_FUSES_OUT_LENGTH_OFST 0
13160 #define MC_CMD_READ_FUSES_OUT_DATA_MINNUM 0
13167 #define MC_CMD_KR_TUNE 0xf1
13177 #define MC_CMD_KR_TUNE_IN_KR_TUNE_OP_OFST 0
13180 #define MC_CMD_KR_TUNE_IN_RXEQ_GET 0x0
13182 #define MC_CMD_KR_TUNE_IN_RXEQ_SET 0x1
13184 #define MC_CMD_KR_TUNE_IN_TXEQ_GET 0x2
13186 #define MC_CMD_KR_TUNE_IN_TXEQ_SET 0x3
13188 #define MC_CMD_KR_TUNE_IN_RECAL 0x4
13192 #define MC_CMD_KR_TUNE_IN_START_EYE_PLOT 0x5
13197 #define MC_CMD_KR_TUNE_IN_POLL_EYE_PLOT 0x6
13199 #define MC_CMD_KR_TUNE_IN_READ_FOM 0x7
13201 #define MC_CMD_KR_TUNE_IN_LINK_TRAIN_RUN 0x8
13203 #define MC_CMD_KR_TUNE_IN_LINK_TRAIN_CMD 0x9
13210 #define MC_CMD_KR_TUNE_IN_KR_TUNE_ARGS_MINNUM 0
13214 #define MC_CMD_KR_TUNE_OUT_LEN 0
13219 #define MC_CMD_KR_TUNE_RXEQ_GET_IN_KR_TUNE_OP_OFST 0
13228 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LEN(num) (0+4*(num))
13230 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_OFST 0
13234 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_ID_LBN 0
13236 /* enum: Attenuation (0-15, Huntington) */
13237 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_ATT 0x0
13238 /* enum: CTLE Boost (0-15, Huntington) */
13239 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_BOOST 0x1
13240 /* enum: Edge DFE Tap1 (Huntington - 0 - max negative, 64 - zero, 127 - max
13241 * positive, Medford - 0-31)
13243 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_TAP1 0x2
13244 /* enum: Edge DFE Tap2 (Huntington - 0 - max negative, 32 - zero, 63 - max
13245 * positive, Medford - 0-31)
13247 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_TAP2 0x3
13248 /* enum: Edge DFE Tap3 (Huntington - 0 - max negative, 32 - zero, 63 - max
13249 * positive, Medford - 0-16)
13251 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_TAP3 0x4
13252 /* enum: Edge DFE Tap4 (Huntington - 0 - max negative, 32 - zero, 63 - max
13253 * positive, Medford - 0-16)
13255 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_TAP4 0x5
13256 /* enum: Edge DFE Tap5 (Huntington - 0 - max negative, 32 - zero, 63 - max
13257 * positive, Medford - 0-16)
13259 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_TAP5 0x6
13260 /* enum: Edge DFE DLEV (0-128 for Medford) */
13261 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_DLEV 0x7
13262 /* enum: Variable Gain Amplifier (0-15, Medford) */
13263 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_VGA 0x8
13264 /* enum: CTLE EQ Capacitor (0-15, Medford) */
13265 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_CTLE_EQC 0x9
13266 /* enum: CTLE EQ Resistor (0-7, Medford) */
13267 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_CTLE_EQRES 0xa
13268 /* enum: CTLE gain (0-31, Medford2) */
13269 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_CTLE_GAIN 0xb
13270 /* enum: CTLE pole (0-31, Medford2) */
13271 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_CTLE_POLE 0xc
13272 /* enum: CTLE peaking (0-31, Medford2) */
13273 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_CTLE_PEAK 0xd
13275 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP1_EVEN 0xe
13277 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP1_ODD 0xf
13279 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP2 0x10
13281 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP3 0x11
13283 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP4 0x12
13285 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP5 0x13
13287 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP6 0x14
13289 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP7 0x15
13291 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP8 0x16
13293 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP9 0x17
13295 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP10 0x18
13297 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP11 0x19
13299 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP12 0x1a
13301 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_IQ_OFF 0x1b
13305 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_H1N_OFF_EVEN 0x1c
13309 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_H1N_OFF_ODD 0x1d
13313 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_H1P_OFF_EVEN 0x1e
13317 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_H1P_OFF_ODD 0x1f
13319 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_CDR_PVT 0x20
13321 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_CDR_INTEG 0x21
13324 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LANE_0 0x0 /* enum */
13325 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LANE_1 0x1 /* enum */
13326 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LANE_2 0x2 /* enum */
13327 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LANE_3 0x3 /* enum */
13328 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LANE_ALL 0x4 /* enum */
13343 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_KR_TUNE_OP_OFST 0
13353 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_ID_LBN 0
13371 #define MC_CMD_KR_TUNE_RXEQ_SET_OUT_LEN 0
13376 #define MC_CMD_KR_TUNE_TXEQ_GET_IN_KR_TUNE_OP_OFST 0
13385 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LEN(num) (0+4*(num))
13387 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_OFST 0
13391 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_ID_LBN 0
13394 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_LEV 0x0
13395 /* enum: De-Emphasis Tap1 Magnitude (0-7) (Huntington) */
13396 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_MODE 0x1
13398 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_DTLEV 0x2
13399 /* enum: De-Emphasis Tap2 Magnitude (0-6) (Huntington) */
13400 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_D2 0x3
13402 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_D2TLEV 0x4
13404 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_E 0x5
13406 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_ETLEV 0x6
13408 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_PREDRV_DLY 0x7
13410 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_SR_SET 0x8
13412 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_RT_SET 0x9
13414 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_LEV_FINE 0xa
13416 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TAP_ADV 0xb
13418 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TAP_DLY 0xc
13421 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LANE_0 0x0 /* enum */
13422 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LANE_1 0x1 /* enum */
13423 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LANE_2 0x2 /* enum */
13424 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LANE_3 0x3 /* enum */
13425 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LANE_ALL 0x4 /* enum */
13438 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_KR_TUNE_OP_OFST 0
13448 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_ID_LBN 0
13464 #define MC_CMD_KR_TUNE_TXEQ_SET_OUT_LEN 0
13469 #define MC_CMD_KR_TUNE_RECAL_IN_KR_TUNE_OP_OFST 0
13476 #define MC_CMD_KR_TUNE_RECAL_OUT_LEN 0
13481 #define MC_CMD_KR_TUNE_START_EYE_PLOT_IN_KR_TUNE_OP_OFST 0
13493 #define MC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_KR_TUNE_OP_OFST 0
13500 #define MC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_LANE_NUM_LBN 0
13509 #define MC_CMD_KR_TUNE_START_EYE_PLOT_OUT_LEN 0
13514 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_IN_KR_TUNE_OP_OFST 0
13521 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_LENMIN 0
13523 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_LEN(num) (0+2*(num))
13524 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_OFST 0
13526 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_MINNUM 0
13532 #define MC_CMD_KR_TUNE_READ_FOM_IN_KR_TUNE_OP_OFST 0
13539 #define MC_CMD_KR_TUNE_READ_FOM_IN_LANE_NUM_LBN 0
13546 #define MC_CMD_KR_TUNE_READ_FOM_OUT_FOM_OFST 0
13552 #define MC_CMD_KR_TUNE_LINK_TRAIN_RUN_IN_KR_TUNE_OP_OFST 0
13559 #define MC_CMD_KR_TUNE_LINK_TRAIN_RUN_IN_STOP 0x0 /* enum */
13560 #define MC_CMD_KR_TUNE_LINK_TRAIN_RUN_IN_START 0x1 /* enum */
13565 #define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_KR_TUNE_OP_OFST 0
13581 #define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_REQ_HOLD 0x0 /* enum */
13582 #define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_REQ_INCREMENT 0x1 /* enum */
13583 #define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_REQ_DECREMENT 0x2 /* enum */
13584 /* C(0) request */
13598 #define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_CM1_STATUS_OFST 0
13600 #define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_STATUS_NOT_UPDATED 0x0 /* enum */
13601 #define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_STATUS_UPDATED 0x1 /* enum */
13602 #define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_STATUS_MINIMUM 0x2 /* enum */
13603 #define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_STATUS_MAXIMUM 0x3 /* enum */
13604 /* C(0) status */
13617 /* C(0) value */
13628 #define MC_CMD_PCIE_TUNE 0xf2
13638 #define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_OP_OFST 0
13641 #define MC_CMD_PCIE_TUNE_IN_RXEQ_GET 0x0
13643 #define MC_CMD_PCIE_TUNE_IN_RXEQ_SET 0x1
13645 #define MC_CMD_PCIE_TUNE_IN_TXEQ_GET 0x2
13647 #define MC_CMD_PCIE_TUNE_IN_TXEQ_SET 0x3
13649 #define MC_CMD_PCIE_TUNE_IN_START_EYE_PLOT 0x5
13654 #define MC_CMD_PCIE_TUNE_IN_POLL_EYE_PLOT 0x6
13656 #define MC_CMD_PCIE_TUNE_IN_BIST_SQUARE_WAVE 0x7
13663 #define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_ARGS_MINNUM 0
13667 #define MC_CMD_PCIE_TUNE_OUT_LEN 0
13672 #define MC_CMD_PCIE_TUNE_RXEQ_GET_IN_PCIE_TUNE_OP_OFST 0
13681 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LEN(num) (0+4*(num))
13683 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_OFST 0
13687 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_ID_LBN 0
13689 /* enum: Attenuation (0-15) */
13690 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_ATT 0x0
13691 /* enum: CTLE Boost (0-15) */
13692 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_BOOST 0x1
13693 /* enum: DFE Tap1 (0 - max negative, 64 - zero, 127 - max positive) */
13694 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_DFE_TAP1 0x2
13695 /* enum: DFE Tap2 (0 - max negative, 32 - zero, 63 - max positive) */
13696 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_DFE_TAP2 0x3
13697 /* enum: DFE Tap3 (0 - max negative, 32 - zero, 63 - max positive) */
13698 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_DFE_TAP3 0x4
13699 /* enum: DFE Tap4 (0 - max negative, 32 - zero, 63 - max positive) */
13700 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_DFE_TAP4 0x5
13701 /* enum: DFE Tap5 (0 - max negative, 32 - zero, 63 - max positive) */
13702 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_DFE_TAP5 0x6
13704 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_DFE_DLEV 0x7
13706 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_FOM 0x8
13708 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_CTLE_EQC 0x9
13710 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_CTLE_EQRES 0xa
13713 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_0 0x0 /* enum */
13714 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_1 0x1 /* enum */
13715 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_2 0x2 /* enum */
13716 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_3 0x3 /* enum */
13717 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_4 0x4 /* enum */
13718 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_5 0x5 /* enum */
13719 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_6 0x6 /* enum */
13720 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_7 0x7 /* enum */
13721 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_8 0x8 /* enum */
13722 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_9 0x9 /* enum */
13723 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_10 0xa /* enum */
13724 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_11 0xb /* enum */
13725 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_12 0xc /* enum */
13726 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_13 0xd /* enum */
13727 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_14 0xe /* enum */
13728 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_15 0xf /* enum */
13729 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_ALL 0x10 /* enum */
13742 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PCIE_TUNE_OP_OFST 0
13752 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_ID_LBN 0
13770 #define MC_CMD_PCIE_TUNE_RXEQ_SET_OUT_LEN 0
13775 #define MC_CMD_PCIE_TUNE_TXEQ_GET_IN_PCIE_TUNE_OP_OFST 0
13784 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_LEN(num) (0+4*(num))
13786 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_OFST 0
13790 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_ID_LBN 0
13793 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_TXMARGIN 0x0
13795 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_TXSWING 0x1
13797 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_CM1 0x2
13798 /* enum: De-emphasis coefficient C(0) (PIPE) */
13799 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_C0 0x3
13801 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_CP1 0x4
13814 #define MC_CMD_PCIE_TUNE_START_EYE_PLOT_IN_PCIE_TUNE_OP_OFST 0
13823 #define MC_CMD_PCIE_TUNE_START_EYE_PLOT_OUT_LEN 0
13828 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_IN_PCIE_TUNE_OP_OFST 0
13835 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_LENMIN 0
13837 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_LEN(num) (0+2*(num))
13838 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_OFST 0
13840 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_MINNUM 0
13844 #define MC_CMD_PCIE_TUNE_BIST_SQUARE_WAVE_IN_LEN 0
13847 #define MC_CMD_PCIE_TUNE_BIST_SQUARE_WAVE_OUT_LEN 0
13854 #define MC_CMD_LICENSING 0xf3
13862 #define MC_CMD_LICENSING_IN_OP_OFST 0
13867 #define MC_CMD_LICENSING_IN_OP_UPDATE_LICENSE 0x0
13869 #define MC_CMD_LICENSING_IN_OP_GET_KEY_STATS 0x1
13874 #define MC_CMD_LICENSING_OUT_VALID_APP_KEYS_OFST 0
13900 #define MC_CMD_LICENSING_OUT_SELF_TEST_FAIL 0x0
13902 #define MC_CMD_LICENSING_OUT_SELF_TEST_PASS 0x1
13909 #define MC_CMD_LICENSING_V3 0xd0
13917 #define MC_CMD_LICENSING_V3_IN_OP_OFST 0
13922 #define MC_CMD_LICENSING_V3_IN_OP_UPDATE_LICENSE 0x0
13926 #define MC_CMD_LICENSING_V3_IN_OP_REPORT_LICENSE 0x1
13931 #define MC_CMD_LICENSING_V3_OUT_VALID_KEYS_OFST 0
13953 #define MC_CMD_LICENSING_V3_OUT_SELF_TEST_FAIL 0x0
13955 #define MC_CMD_LICENSING_V3_OUT_SELF_TEST_PASS 0x1
13978 #define MC_CMD_LICENSING_GET_ID_V3 0xd1
13984 #define MC_CMD_LICENSING_GET_ID_V3_IN_LEN 0
13991 #define MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_TYPE_OFST 0
13999 #define MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_ID_MINNUM 0
14007 #define MC_CMD_MC2MC_PROXY 0xf4
14013 #define MC_CMD_MC2MC_PROXY_IN_LEN 0
14016 #define MC_CMD_MC2MC_PROXY_OUT_LEN 0
14024 #define MC_CMD_GET_LICENSED_APP_STATE 0xf5
14032 #define MC_CMD_GET_LICENSED_APP_STATE_IN_APP_ID_OFST 0
14038 #define MC_CMD_GET_LICENSED_APP_STATE_OUT_STATE_OFST 0
14041 #define MC_CMD_GET_LICENSED_APP_STATE_OUT_NOT_LICENSED 0x0
14043 #define MC_CMD_GET_LICENSED_APP_STATE_OUT_LICENSED 0x1
14051 #define MC_CMD_GET_LICENSED_V3_APP_STATE 0xd2
14061 #define MC_CMD_GET_LICENSED_V3_APP_STATE_IN_APP_ID_OFST 0
14063 #define MC_CMD_GET_LICENSED_V3_APP_STATE_IN_APP_ID_LO_OFST 0
14069 #define MC_CMD_GET_LICENSED_V3_APP_STATE_OUT_STATE_OFST 0
14072 #define MC_CMD_GET_LICENSED_V3_APP_STATE_OUT_NOT_LICENSED 0x0
14074 #define MC_CMD_GET_LICENSED_V3_APP_STATE_OUT_LICENSED 0x1
14082 #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES 0xd3
14092 #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN_FEATURES_OFST 0
14094 #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN_FEATURES_LO_OFST 0
14100 #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT_STATES_OFST 0
14102 #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT_STATES_LO_OFST 0
14110 #define MC_CMD_LICENSED_APP_OP 0xf6
14120 #define MC_CMD_LICENSED_APP_OP_IN_APP_ID_OFST 0
14126 #define MC_CMD_LICENSED_APP_OP_IN_OP_VALIDATE 0x0
14128 #define MC_CMD_LICENSED_APP_OP_IN_OP_MASK 0x1
14132 #define MC_CMD_LICENSED_APP_OP_IN_ARGS_MINNUM 0
14136 #define MC_CMD_LICENSED_APP_OP_OUT_LENMIN 0
14138 #define MC_CMD_LICENSED_APP_OP_OUT_LEN(num) (0+4*(num))
14140 #define MC_CMD_LICENSED_APP_OP_OUT_RESULT_OFST 0
14142 #define MC_CMD_LICENSED_APP_OP_OUT_RESULT_MINNUM 0
14148 #define MC_CMD_LICENSED_APP_OP_VALIDATE_IN_APP_ID_OFST 0
14160 #define MC_CMD_LICENSED_APP_OP_VALIDATE_OUT_EXPIRY_OFST 0
14169 #define MC_CMD_LICENSED_APP_OP_MASK_IN_APP_ID_OFST 0
14179 #define MC_CMD_LICENSED_APP_OP_MASK_OUT_LEN 0
14186 #define MC_CMD_LICENSED_V3_VALIDATE_APP 0xd4
14194 #define MC_CMD_LICENSED_V3_VALIDATE_APP_IN_CHALLENGE_OFST 0
14210 #define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_RESPONSE_OFST 0
14219 #define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_EXPIRY_UNIT_ACC 0x0
14221 #define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_EXPIRY_UNIT_DAYS 0x1
14229 * exists, then the field is filled with 0xFF.
14238 #define MC_CMD_LICENSED_V3_MASK_FEATURES 0xd5
14246 #define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_MASK_OFST 0
14248 #define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_MASK_LO_OFST 0
14254 #define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_OFF 0x0
14256 #define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_ON 0x1
14259 #define MC_CMD_LICENSED_V3_MASK_FEATURES_OUT_LEN 0
14269 #define MC_CMD_LICENSING_V3_TEMPORARY 0xd6
14277 #define MC_CMD_LICENSING_V3_TEMPORARY_IN_OP_OFST 0
14283 #define MC_CMD_LICENSING_V3_TEMPORARY_SET 0x0
14287 #define MC_CMD_LICENSING_V3_TEMPORARY_CLEAR 0x1
14291 #define MC_CMD_LICENSING_V3_TEMPORARY_STATUS 0x2
14295 #define MC_CMD_LICENSING_V3_TEMPORARY_IN_SET_OP_OFST 0
14303 #define MC_CMD_LICENSING_V3_TEMPORARY_IN_CLEAR_OP_OFST 0
14308 #define MC_CMD_LICENSING_V3_TEMPORARY_IN_STATUS_OP_OFST 0
14314 #define MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_STATUS_OFST 0
14317 #define MC_CMD_LICENSING_V3_TEMPORARY_STATUS_OK 0x0
14319 #define MC_CMD_LICENSING_V3_TEMPORARY_STATUS_IN_PROGRESS 0x1
14323 #define MC_CMD_LICENSING_V3_TEMPORARY_STATUS_ERROR 0x2
14338 #define MC_CMD_SET_PORT_SNIFF_CONFIG 0xf7
14346 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_FLAGS_OFST 0
14348 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_ENABLE_LBN 0
14359 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_RX_MODE_SIMPLE 0x0
14361 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_RX_MODE_RSS 0x1
14364 * of 0xFFFFFFFF is guaranteed never to be a valid handle.
14370 #define MC_CMD_SET_PORT_SNIFF_CONFIG_OUT_LEN 0
14378 #define MC_CMD_GET_PORT_SNIFF_CONFIG 0xf8
14384 #define MC_CMD_GET_PORT_SNIFF_CONFIG_IN_LEN 0
14389 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_FLAGS_OFST 0
14391 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_ENABLE_LBN 0
14402 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_RX_MODE_SIMPLE 0x0
14404 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_RX_MODE_RSS 0x1
14413 #define MC_CMD_SET_PARSER_DISP_CONFIG 0xf9
14423 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_TYPE_OFST 0
14428 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_TXQ_MCAST_UDP_DST_LOOKUP_EN 0x0
14433 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_VADAPTOR_SUPPRESS_SELF_TX 0x1
14448 #define MC_CMD_SET_PARSER_DISP_CONFIG_OUT_LEN 0
14454 #define MC_CMD_GET_PARSER_DISP_CONFIG 0xfa
14462 #define MC_CMD_GET_PARSER_DISP_CONFIG_IN_TYPE_OFST 0
14475 #define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_LEN(num) (0+4*(num))
14479 #define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_VALUE_OFST 0
14494 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG 0xfb
14502 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_FLAGS_OFST 0
14504 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_ENABLE_LBN 0
14513 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_RX_MODE_SIMPLE 0x0
14515 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_RX_MODE_RSS 0x1
14518 * of 0xFFFFFFFF is guaranteed never to be a valid handle.
14524 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_OUT_LEN 0
14532 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG 0xfc
14538 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_IN_LEN 0
14543 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_FLAGS_OFST 0
14545 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_ENABLE_LBN 0
14554 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_RX_MODE_SIMPLE 0x0
14556 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_RX_MODE_RSS 0x1
14565 #define MC_CMD_RMON_STATS_RX_ERRORS 0xfe
14573 #define MC_CMD_RMON_STATS_RX_ERRORS_IN_RX_QUEUE_OFST 0
14577 #define MC_CMD_RMON_STATS_RX_ERRORS_IN_RST_LBN 0
14582 #define MC_CMD_RMON_STATS_RX_ERRORS_OUT_CRC_ERRORS_OFST 0
14595 #define MC_CMD_GET_PCIE_RESOURCE_INFO 0xfd
14601 #define MC_CMD_GET_PCIE_RESOURCE_INFO_IN_LEN 0
14606 #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_MAX_PFS_OFST 0
14633 #define MC_CMD_GET_PORT_MODES 0xff
14639 #define MC_CMD_GET_PORT_MODES_IN_LEN 0
14644 #define MC_CMD_GET_PORT_MODES_OUT_MODES_OFST 0
14657 #define MC_CMD_READ_ATB 0x100
14664 #define MC_CMD_READ_ATB_IN_SIGNAL_BUS_OFST 0
14666 #define MC_CMD_READ_ATB_IN_BUS_CCOM 0x0 /* enum */
14667 #define MC_CMD_READ_ATB_IN_BUS_CKR 0x1 /* enum */
14668 #define MC_CMD_READ_ATB_IN_BUS_CPCIE 0x8 /* enum */
14678 #define MC_CMD_READ_ATB_OUT_SAMPLE_MV_OFST 0
14686 #define MC_CMD_GET_WORKAROUNDS 0x59
14695 #define MC_CMD_GET_WORKAROUNDS_OUT_IMPLEMENTED_OFST 0
14700 #define MC_CMD_GET_WORKAROUNDS_OUT_BUG17230 0x2
14702 #define MC_CMD_GET_WORKAROUNDS_OUT_BUG35388 0x4
14704 #define MC_CMD_GET_WORKAROUNDS_OUT_BUG35017 0x8
14706 #define MC_CMD_GET_WORKAROUNDS_OUT_BUG41750 0x10
14712 #define MC_CMD_GET_WORKAROUNDS_OUT_BUG42008 0x20
14714 #define MC_CMD_GET_WORKAROUNDS_OUT_BUG26807 0x40
14716 #define MC_CMD_GET_WORKAROUNDS_OUT_BUG61265 0x80
14722 #define MC_CMD_PRIVILEGE_MASK 0x5a
14729 /* The target function to have its mask read or set e.g. PF 0 = 0xFFFF0000, VF
14730 * 1,3 = 0x00030001
14732 #define MC_CMD_PRIVILEGE_MASK_IN_FUNCTION_OFST 0
14734 #define MC_CMD_PRIVILEGE_MASK_IN_FUNCTION_PF_LBN 0
14738 #define MC_CMD_PRIVILEGE_MASK_IN_VF_NULL 0xffff /* enum */
14744 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_ADMIN 0x1 /* enum */
14745 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_LINK 0x2 /* enum */
14746 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_ONLOAD 0x4 /* enum */
14747 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_PTP 0x8 /* enum */
14748 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_INSECURE_FILTERS 0x10 /* enum */
14750 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_MAC_SPOOFING 0x20
14751 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_UNICAST 0x40 /* enum */
14752 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_MULTICAST 0x80 /* enum */
14753 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_BROADCAST 0x100 /* enum */
14754 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_ALL_MULTICAST 0x200 /* enum */
14755 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_PROMISCUOUS 0x400 /* enum */
14759 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_MAC_SPOOFING_TX 0x800
14763 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_CHANGE_MAC 0x1000
14769 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_UNRESTRICTED_VLAN 0x2000
14773 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_INSECURE 0x4000
14779 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_ADMIN_TSA_UNBOUND 0x8000
14783 #define MC_CMD_PRIVILEGE_MASK_IN_DO_CHANGE 0x80000000
14788 #define MC_CMD_PRIVILEGE_MASK_OUT_OLD_MASK_OFST 0
14795 #define MC_CMD_LINK_STATE_MODE 0x5c
14803 * e.g. VF 1,3 = 0x00030001
14805 #define MC_CMD_LINK_STATE_MODE_IN_FUNCTION_OFST 0
14807 #define MC_CMD_LINK_STATE_MODE_IN_FUNCTION_PF_LBN 0
14814 #define MC_CMD_LINK_STATE_MODE_IN_LINK_STATE_AUTO 0x0 /* enum */
14815 #define MC_CMD_LINK_STATE_MODE_IN_LINK_STATE_UP 0x1 /* enum */
14816 #define MC_CMD_LINK_STATE_MODE_IN_LINK_STATE_DOWN 0x2 /* enum */
14819 #define MC_CMD_LINK_STATE_MODE_IN_DO_NOT_CHANGE 0xffffffff
14823 #define MC_CMD_LINK_STATE_MODE_OUT_OLD_MODE_OFST 0
14831 #define MC_CMD_GET_SNAPSHOT_LENGTH 0x101
14837 #define MC_CMD_GET_SNAPSHOT_LENGTH_IN_LEN 0
14842 #define MC_CMD_GET_SNAPSHOT_LENGTH_OUT_RX_SNAPLEN_MIN_OFST 0
14852 #define MC_CMD_FUSE_DIAGS 0x102
14858 #define MC_CMD_FUSE_DIAGS_IN_LEN 0
14862 /* Total number of mismatched bits between pairs in area 0 */
14863 #define MC_CMD_FUSE_DIAGS_OUT_AREA0_MISMATCH_BITS_OFST 0
14865 /* Total number of unexpectedly clear (set in B but not A) bits in area 0 */
14868 /* Total number of unexpectedly clear (set in A but not B) bits in area 0 */
14871 /* Checksum of data after logical OR of pairs in area 0 */
14905 #define MC_CMD_PRIVILEGE_MODIFY 0x60
14913 #define MC_CMD_PRIVILEGE_MODIFY_IN_FN_GROUP_OFST 0
14915 #define MC_CMD_PRIVILEGE_MODIFY_IN_NONE 0x0 /* enum */
14916 #define MC_CMD_PRIVILEGE_MODIFY_IN_ALL 0x1 /* enum */
14917 #define MC_CMD_PRIVILEGE_MODIFY_IN_PFS_ONLY 0x2 /* enum */
14918 #define MC_CMD_PRIVILEGE_MODIFY_IN_VFS_ONLY 0x3 /* enum */
14919 #define MC_CMD_PRIVILEGE_MODIFY_IN_VFS_OF_PF 0x4 /* enum */
14920 #define MC_CMD_PRIVILEGE_MODIFY_IN_ONE 0x5 /* enum */
14924 #define MC_CMD_PRIVILEGE_MODIFY_IN_FUNCTION_PF_LBN 0
14940 #define MC_CMD_PRIVILEGE_MODIFY_OUT_LEN 0
14946 #define MC_CMD_XPM_READ_BYTES 0x103
14954 #define MC_CMD_XPM_READ_BYTES_IN_ADDR_OFST 0
14961 #define MC_CMD_XPM_READ_BYTES_OUT_LENMIN 0
14963 #define MC_CMD_XPM_READ_BYTES_OUT_LEN(num) (0+1*(num))
14965 #define MC_CMD_XPM_READ_BYTES_OUT_DATA_OFST 0
14967 #define MC_CMD_XPM_READ_BYTES_OUT_DATA_MINNUM 0
14974 #define MC_CMD_XPM_WRITE_BYTES 0x104
14984 #define MC_CMD_XPM_WRITE_BYTES_IN_ADDR_OFST 0
14992 #define MC_CMD_XPM_WRITE_BYTES_IN_DATA_MINNUM 0
14996 #define MC_CMD_XPM_WRITE_BYTES_OUT_LEN 0
15002 #define MC_CMD_XPM_READ_SECTOR 0x105
15010 #define MC_CMD_XPM_READ_SECTOR_IN_INDEX_OFST 0
15021 #define MC_CMD_XPM_READ_SECTOR_OUT_TYPE_OFST 0
15023 #define MC_CMD_XPM_READ_SECTOR_OUT_BLANK 0x0 /* enum */
15024 #define MC_CMD_XPM_READ_SECTOR_OUT_CRYPTO_KEY_128 0x1 /* enum */
15025 #define MC_CMD_XPM_READ_SECTOR_OUT_CRYPTO_KEY_256 0x2 /* enum */
15026 #define MC_CMD_XPM_READ_SECTOR_OUT_CRYPTO_DATA 0x3 /* enum */
15027 #define MC_CMD_XPM_READ_SECTOR_OUT_INVALID 0xff /* enum */
15031 #define MC_CMD_XPM_READ_SECTOR_OUT_DATA_MINNUM 0
15038 #define MC_CMD_XPM_WRITE_SECTOR 0x106
15048 * sectors (or until no more space available). If 0, only one write attempt is
15052 #define MC_CMD_XPM_WRITE_SECTOR_IN_RETRIES_OFST 0
15067 #define MC_CMD_XPM_WRITE_SECTOR_IN_DATA_MINNUM 0
15073 #define MC_CMD_XPM_WRITE_SECTOR_OUT_INDEX_OFST 0
15080 #define MC_CMD_XPM_INVALIDATE_SECTOR 0x107
15088 #define MC_CMD_XPM_INVALIDATE_SECTOR_IN_INDEX_OFST 0
15092 #define MC_CMD_XPM_INVALIDATE_SECTOR_OUT_LEN 0
15098 #define MC_CMD_XPM_BLANK_CHECK 0x108
15106 #define MC_CMD_XPM_BLANK_CHECK_IN_ADDR_OFST 0
15117 #define MC_CMD_XPM_BLANK_CHECK_OUT_BAD_COUNT_OFST 0
15124 #define MC_CMD_XPM_BLANK_CHECK_OUT_BAD_ADDR_MINNUM 0
15131 #define MC_CMD_XPM_REPAIR 0x109
15139 #define MC_CMD_XPM_REPAIR_IN_ADDR_OFST 0
15146 #define MC_CMD_XPM_REPAIR_OUT_LEN 0
15153 #define MC_CMD_XPM_DECODER_TEST 0x10a
15159 #define MC_CMD_XPM_DECODER_TEST_IN_LEN 0
15162 #define MC_CMD_XPM_DECODER_TEST_OUT_LEN 0
15172 #define MC_CMD_XPM_WRITE_TEST 0x10b
15178 #define MC_CMD_XPM_WRITE_TEST_IN_LEN 0
15181 #define MC_CMD_XPM_WRITE_TEST_OUT_LEN 0
15192 #define MC_CMD_EXEC_SIGNED 0x10c
15200 #define MC_CMD_EXEC_SIGNED_IN_CODELEN_OFST 0
15213 #define MC_CMD_EXEC_SIGNED_OUT_LEN 0
15221 #define MC_CMD_PREPARE_SIGNED 0x10d
15229 #define MC_CMD_PREPARE_SIGNED_IN_DATALEN_OFST 0
15233 #define MC_CMD_PREPARE_SIGNED_OUT_LEN 0
15243 #define MC_CMD_SET_SECURITY_RULE 0x10f
15251 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_FIELDS_OFST 0
15253 #define MC_CMD_SET_SECURITY_RULE_IN_MATCH_REMOTE_IP_LBN 0
15304 /* IP protocol to match (in low byte; set high byte to 0) */
15310 /* Reserved; set to 0 */
15314 * 0 for IPv4 address)
15318 /* local IP address to match (as bytes in network order; set last 12 bytes to 0
15348 #define MC_CMD_SET_SECURITY_RULE_IN_TX_ACTION_NONE 0x0
15350 #define MC_CMD_SET_SECURITY_RULE_IN_TX_ACTION_WHITELIST 0x1
15352 #define MC_CMD_SET_SECURITY_RULE_IN_TX_ACTION_BLACKLIST 0x2
15357 #define MC_CMD_SET_SECURITY_RULE_IN_TX_ACTION_SAMPLE 0x4
15359 #define MC_CMD_SET_SECURITY_RULE_IN_TX_ACTION_UNCHANGED 0xffffffff
15364 #define MC_CMD_SET_SECURITY_RULE_IN_RX_ACTION_NONE 0x0
15366 #define MC_CMD_SET_SECURITY_RULE_IN_RX_ACTION_WHITELIST 0x1
15368 #define MC_CMD_SET_SECURITY_RULE_IN_RX_ACTION_BLACKLIST 0x2
15373 #define MC_CMD_SET_SECURITY_RULE_IN_RX_ACTION_SAMPLE 0x4
15375 #define MC_CMD_SET_SECURITY_RULE_IN_RX_ACTION_UNCHANGED 0xffffffff
15382 #define MC_CMD_SET_SECURITY_RULE_IN_COUNTER_ID_NONE 0x0
15384 #define MC_CMD_SET_SECURITY_RULE_IN_COUNTER_ID_SW_AUTO 0xeeeeeeee
15386 #define MC_CMD_SET_SECURITY_RULE_IN_COUNTER_ID_HW 0xffffffff
15391 #define MC_CMD_SET_SECURITY_RULE_OUT_COUNTER_REFCNT_OFST 0
15417 #define MC_CMD_RESET_SECURITY_RULES 0x110
15425 #define MC_CMD_RESET_SECURITY_RULES_IN_PHYSICAL_PORT_OFST 0
15428 #define MC_CMD_RESET_SECURITY_RULES_IN_ALL_PHYSICAL_PORTS 0xffffffff
15431 #define MC_CMD_RESET_SECURITY_RULES_OUT_LEN 0
15442 #define MC_CMD_GET_SECURITY_RULESET_VERSION 0x111
15448 #define MC_CMD_GET_SECURITY_RULESET_VERSION_IN_LEN 0
15453 #define MC_CMD_GET_SECURITY_RULESET_VERSION_OUT_LEN(num) (0+1*(num))
15455 #define MC_CMD_GET_SECURITY_RULESET_VERSION_OUT_VERSION_OFST 0
15468 #define MC_CMD_SECURITY_RULE_COUNTER_ALLOC 0x112
15476 #define MC_CMD_SECURITY_RULE_COUNTER_ALLOC_IN_NUM_COUNTERS_OFST 0
15486 #define MC_CMD_SECURITY_RULE_COUNTER_ALLOC_OUT_NUM_COUNTERS_OFST 0
15491 #define MC_CMD_SECURITY_RULE_COUNTER_ALLOC_OUT_COUNTER_ID_MINNUM 0
15502 #define MC_CMD_SECURITY_RULE_COUNTER_FREE 0x113
15512 #define MC_CMD_SECURITY_RULE_COUNTER_FREE_IN_NUM_COUNTERS_OFST 0
15517 #define MC_CMD_SECURITY_RULE_COUNTER_FREE_IN_COUNTER_ID_MINNUM 0
15521 #define MC_CMD_SECURITY_RULE_COUNTER_FREE_OUT_LEN 0
15533 #define MC_CMD_SUBNET_MAP_SET_NODE 0x114
15542 /* node to update in the range 0 .. SUBNET_MAP_NUM_NODES-1 */
15543 #define MC_CMD_SUBNET_MAP_SET_NODE_IN_NODE_ID_OFST 0
15556 #define MC_CMD_SUBNET_MAP_SET_NODE_OUT_LEN 0
15563 #define PORTRANGE_TREE_ENTRY_BRANCH_KEY_OFST 0
15565 #define PORTRANGE_TREE_ENTRY_LEAF_NODE_KEY 0xffff /* enum */
15566 #define PORTRANGE_TREE_ENTRY_BRANCH_KEY_LBN 0
15584 #define MC_CMD_REMOTE_PORTRANGE_MAP_SET_TREE 0x115
15592 #define MC_CMD_REMOTE_PORTRANGE_MAP_SET_TREE_IN_LEN(num) (0+4*(num))
15596 #define MC_CMD_REMOTE_PORTRANGE_MAP_SET_TREE_IN_ENTRIES_OFST 0
15602 #define MC_CMD_REMOTE_PORTRANGE_MAP_SET_TREE_OUT_LEN 0
15614 #define MC_CMD_LOCAL_PORTRANGE_MAP_SET_TREE 0x116
15622 #define MC_CMD_LOCAL_PORTRANGE_MAP_SET_TREE_IN_LEN(num) (0+4*(num))
15626 #define MC_CMD_LOCAL_PORTRANGE_MAP_SET_TREE_IN_ENTRIES_OFST 0
15632 #define MC_CMD_LOCAL_PORTRANGE_MAP_SET_TREE_OUT_LEN 0
15637 #define TUNNEL_ENCAP_UDP_PORT_ENTRY_UDP_PORT_OFST 0
15640 #define TUNNEL_ENCAP_UDP_PORT_ENTRY_IANA_VXLAN_UDP_PORT 0x12b5
15642 #define TUNNEL_ENCAP_UDP_PORT_ENTRY_IANA_GENEVE_UDP_PORT 0x17c1
15643 #define TUNNEL_ENCAP_UDP_PORT_ENTRY_UDP_PORT_LBN 0
15649 #define TUNNEL_ENCAP_UDP_PORT_ENTRY_VXLAN 0x0
15651 #define TUNNEL_ENCAP_UDP_PORT_ENTRY_GENEVE 0x1
15663 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS 0x117
15673 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_FLAGS_OFST 0
15675 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_UNLOADING_LBN 0
15685 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_ENTRIES_MINNUM 0
15691 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT_FLAGS_OFST 0
15693 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT_RESETTING_LBN 0
15703 #define MC_CMD_RX_BALANCING 0x118
15711 #define MC_CMD_RX_BALANCING_IN_PORT_OFST 0
15724 #define MC_CMD_RX_BALANCING_OUT_LEN 0
15731 #define MC_CMD_TSA_BIND 0x119
15738 #define MC_CMD_TSA_BIND_IN_OP_OFST 0
15741 #define MC_CMD_TSA_BIND_OP_GET_ID 0x1
15747 #define MC_CMD_TSA_BIND_OP_GET_TICKET 0x2
15756 #define MC_CMD_TSA_BIND_OP_SET_KEY 0x3
15760 #define MC_CMD_TSA_BIND_OP_UNBIND 0x4
15762 #define MC_CMD_TSA_BIND_OP_UNBIND_EXT 0x5
15768 #define MC_CMD_TSA_BIND_OP_SET_UNBINDTOKEN 0x6
15770 #define MC_CMD_TSA_BIND_OP_DECOMMISSION 0x7
15772 #define MC_CMD_TSA_BIND_OP_GET_CERTIFICATE 0x8
15776 #define MC_CMD_TSA_BIND_OP_SECURE_UNBIND 0x9
15780 #define MC_CMD_TSA_BIND_OP_SECURE_DECOMMISSION 0xa
15785 #define MC_CMD_TSA_BIND_OP_TEST_MCDI 0xb
15792 #define MC_CMD_TSA_BIND_IN_GET_ID_OP_OFST 0
15805 #define MC_CMD_TSA_BIND_IN_GET_TICKET_OP_OFST 0
15813 #define MC_CMD_TSA_BIND_IN_SET_KEY_OP_OFST 0
15831 #define MC_CMD_TSA_BIND_IN_UNBIND_OP_OFST 0
15844 #define MC_CMD_TSA_BIND_IN_UNBIND_EXT_OP_OFST 0
15883 #define MC_CMD_TSA_BIND_IN_SET_UNBINDTOKEN_OP_OFST 0
15896 #define MC_CMD_TSA_BIND_IN_SET_UNBINDTOKEN_ADAPTER_BINDING_FAILURE 0x1
15916 #define MC_CMD_TSA_BIND_IN_DECOMMISSION_OP_OFST 0
15947 #define MC_CMD_TSA_BIND_IN_GET_CERTIFICATE_OP_OFST 0
15952 #define MC_CMD_TSA_BIND_IN_GET_CERTIFICATE_UNUSED 0x0 /* enum */
15956 #define MC_CMD_TSA_BIND_IN_GET_CERTIFICATE_AAC 0x1
15960 #define MC_CMD_TSA_BIND_IN_GET_CERTIFICATE_AASC 0x2
15969 #define MC_CMD_TSA_BIND_IN_SECURE_UNBIND_OP_OFST 0
16010 #define MC_CMD_TSA_BIND_IN_SECURE_DECOMMISSION_OP_OFST 0
16040 #define MC_CMD_TSA_BIND_IN_SECURE_DECOMMISSION_ADAPTER_BINDING_FAILURE 0x1
16055 #define MC_CMD_TSA_BIND_IN_TEST_MCDI_OP_OFST 0
16060 #define MC_CMD_TSA_BIND_IN_TEST_MCDI_DISABLE 0x0 /* enum */
16061 #define MC_CMD_TSA_BIND_IN_TEST_MCDI_ENABLE 0x1 /* enum */
16072 #define MC_CMD_TSA_BIND_OUT_GET_ID_OP_OFST 0
16082 #define MC_CMD_TSA_BIND_OUT_GET_ID_RULE_ENGINE_TSAN 0x1
16084 #define MC_CMD_TSA_BIND_OUT_GET_ID_RULE_ENGINE_NEMU 0x2
16086 #define MC_CMD_TSA_BIND_OUT_GET_ID_RULE_ENGINE_SSFE 0x3
16107 #define MC_CMD_TSA_BIND_OUT_GET_TICKET_OP_OFST 0
16123 #define MC_CMD_TSA_BIND_OUT_SET_KEY_OP_OFST 0
16129 /* Same as MC_CMD_ERR field, but included as 0 in success cases */
16130 #define MC_CMD_TSA_BIND_OUT_UNBIND_RESULT_OFST 0
16136 #define MC_CMD_TSA_BIND_OUT_UNBIND_OK_UNBOUND 0x0
16138 #define MC_CMD_TSA_BIND_OUT_UNBIND_ERR_BAD_TSANID 0x1
16140 #define MC_CMD_TSA_BIND_OUT_UNBIND_ERR_REMOVE_TICKET 0x2
16142 #define MC_CMD_TSA_BIND_OUT_UNBIND_ERR_NOT_BOUND 0x3
16148 /* Same as MC_CMD_ERR field, but included as 0 in success cases */
16149 #define MC_CMD_TSA_BIND_OUT_UNBIND_EXT_RESULT_OFST 0
16155 #define MC_CMD_TSA_BIND_OUT_UNBIND_EXT_OK_UNBOUND 0x0
16157 #define MC_CMD_TSA_BIND_OUT_UNBIND_EXT_ERR_BAD_TSANID 0x1
16159 #define MC_CMD_TSA_BIND_OUT_UNBIND_EXT_ERR_REMOVE_TICKET 0x2
16161 #define MC_CMD_TSA_BIND_OUT_UNBIND_EXT_ERR_NOT_BOUND 0x3
16163 #define MC_CMD_TSA_BIND_OUT_UNBIND_EXT_ERR_BAD_TOKEN 0x4
16165 #define MC_CMD_TSA_BIND_OUT_UNBIND_EXT_ERR_BAD_SIGNATURE 0x5
16172 #define MC_CMD_TSA_BIND_OUT_SET_UNBINDTOKEN_OP_OFST 0
16182 #define MC_CMD_TSA_BIND_OUT_DECOMMISSION_OP_OFST 0
16192 #define MC_CMD_TSA_BIND_OUT_GET_CERTIFICATE_OP_OFST 0
16210 #define MC_CMD_TSA_BIND_OUT_SECURE_UNBIND_OP_OFST 0
16215 #define MC_CMD_TSA_BIND_OUT_SECURE_UNBIND_OK_UNBOUND 0x0
16217 #define MC_CMD_TSA_BIND_OUT_SECURE_UNBIND_ERR_BAD_TSANID 0x1
16219 #define MC_CMD_TSA_BIND_OUT_SECURE_UNBIND_ERR_REMOVE_TICKET 0x2
16221 #define MC_CMD_TSA_BIND_OUT_SECURE_UNBIND_ERR_NOT_BOUND 0x3
16223 #define MC_CMD_TSA_BIND_OUT_SECURE_UNBIND_ERR_BAD_TOKEN 0x4
16225 #define MC_CMD_TSA_BIND_OUT_SECURE_UNBIND_ERR_BAD_SIGNATURE 0x5
16232 #define MC_CMD_TSA_BIND_OUT_SECURE_DECOMMISSION_OP_OFST 0
16237 #define MC_CMD_TSA_BIND_OUT_SECURE_DECOMMISSION_OK_UNBOUND 0x0
16239 #define MC_CMD_TSA_BIND_OUT_SECURE_DECOMMISSION_ERR_BAD_TSANID 0x1
16241 #define MC_CMD_TSA_BIND_OUT_SECURE_DECOMMISSION_ERR_REMOVE_TICKET 0x2
16243 #define MC_CMD_TSA_BIND_OUT_SECURE_DECOMMISSION_ERR_NOT_BOUND 0x3
16245 #define MC_CMD_TSA_BIND_OUT_SECURE_DECOMMISSION_ERR_BAD_TOKEN 0x4
16247 #define MC_CMD_TSA_BIND_OUT_SECURE_DECOMMISSION_ERR_BAD_SIGNATURE 0x5
16254 #define MC_CMD_TSA_BIND_OUT_TEST_MCDI_OP_OFST 0
16271 #define MC_CMD_MANAGE_SECURITY_RULESET_CACHE 0x11a
16279 #define MC_CMD_MANAGE_SECURITY_RULESET_CACHE_IN_OP_OFST 0
16284 #define MC_CMD_MANAGE_SECURITY_RULESET_CACHE_IN_OP_GET_CACHED_VERSION 0x0
16288 #define MC_CMD_MANAGE_SECURITY_RULESET_CACHE_IN_OP_ROLLBACK 0x1
16290 #define MC_CMD_MANAGE_SECURITY_RULESET_CACHE_IN_OP_COMMIT 0x2
16292 #define MC_CMD_MANAGE_SECURITY_RULESET_CACHE_IN_OP_INVALIDATE 0x3
16301 #define MC_CMD_MANAGE_SECURITY_RULESET_CACHE_OUT_STATE_OFST 0
16306 #define MC_CMD_MANAGE_SECURITY_RULESET_CACHE_OUT_STATE_INVALID 0x0
16308 #define MC_CMD_MANAGE_SECURITY_RULESET_CACHE_OUT_STATE_VALID 0x1
16323 #define MC_CMD_NVRAM_PRIVATE_APPEND 0x11c
16333 #define MC_CMD_NVRAM_PRIVATE_APPEND_IN_TAG_OFST 0
16345 #define MC_CMD_NVRAM_PRIVATE_APPEND_OUT_LEN 0
16353 #define MC_CMD_XPM_VERIFY_CONTENTS 0x11b
16361 #define MC_CMD_XPM_VERIFY_CONTENTS_IN_DATA_TYPE_OFST 0
16369 #define MC_CMD_XPM_VERIFY_CONTENTS_OUT_NUM_SECTORS_OFST 0
16380 #define MC_CMD_XPM_VERIFY_CONTENTS_OUT_SIGNATURE_MINNUM 0
16392 #define MC_CMD_SET_EVQ_TMR 0x120
16400 #define MC_CMD_SET_EVQ_TMR_IN_INSTANCE_OFST 0
16411 #define MC_CMD_SET_EVQ_TMR_IN_TIMER_MODE_DIS 0x0 /* enum */
16412 #define MC_CMD_SET_EVQ_TMR_IN_TIMER_MODE_IMMED_START 0x1 /* enum */
16413 #define MC_CMD_SET_EVQ_TMR_IN_TIMER_MODE_TRIG_START 0x2 /* enum */
16414 #define MC_CMD_SET_EVQ_TMR_IN_TIMER_MODE_INT_HLDOFF 0x3 /* enum */
16419 #define MC_CMD_SET_EVQ_TMR_OUT_TMR_LOAD_ACT_NS_OFST 0
16429 #define MC_CMD_GET_EVQ_TMR_PROPERTIES 0x122
16435 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_IN_LEN 0
16440 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_FLAGS_OFST 0
16497 #define MC_CMD_ALLOCATE_TX_VFIFO_CP 0x11d
16507 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_INSTANCE_OFST 0
16512 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_ENABLED 0x1 /* enum */
16514 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_DISABLED 0x0
16522 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_USE_FUNCTION_VALUE -0x1
16527 /* MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_USE_FUNCTION_VALUE -0x1 */
16528 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_PORT0 0x0 /* enum */
16529 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_PORT1 0x1 /* enum */
16530 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_PORT2 0x2 /* enum */
16531 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_PORT3 0x3 /* enum */
16532 /* enum: To enable Switch loopback with Rx engine 0 */
16533 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_RX_ENGINE0 0x4
16535 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_RX_ENGINE1 0x5
16540 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_OUT_CP_ID_OFST 0
16548 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO 0x11e
16557 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_CP_OFST 0
16563 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_USE_CP_VALUE -0x1
16564 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_PORT0 0x0 /* enum */
16565 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_PORT1 0x1 /* enum */
16566 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_PORT2 0x2 /* enum */
16567 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_PORT3 0x3 /* enum */
16568 /* enum: To enable Switch loopback with Rx engine 0 */
16569 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_RX_ENGINE0 0x4
16571 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_RX_ENGINE1 0x5
16576 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_NO_MINIMUM 0x0
16584 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_LOWEST_AVAILABLE -0x1
16589 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_OUT_VID_OFST 0
16600 #define MC_CMD_TEARDOWN_TX_VFIFO_VF 0x11f
16608 #define MC_CMD_TEARDOWN_TX_VFIFO_VF_IN_VFIFO_OFST 0
16612 #define MC_CMD_TEARDOWN_TX_VFIFO_VF_OUT_LEN 0
16619 #define MC_CMD_DEALLOCATE_TX_VFIFO_CP 0x121
16627 #define MC_CMD_DEALLOCATE_TX_VFIFO_CP_IN_POOL_ID_OFST 0
16631 #define MC_CMD_DEALLOCATE_TX_VFIFO_CP_OUT_LEN 0
16640 * completion or it may return 0 and continue processing, therefore the caller
16644 * or 0 if there has not been a previous rekey.
16646 #define MC_CMD_REKEY 0x123
16654 #define MC_CMD_REKEY_IN_OP_OFST 0
16657 #define MC_CMD_REKEY_IN_OP_REKEY 0x0
16659 #define MC_CMD_REKEY_IN_OP_POLL 0x1
16662 #define MC_CMD_REKEY_OUT_LEN 0
16669 #define MC_CMD_SWITCH_GET_UNASSIGNED_BUFFERS 0x124
16675 #define MC_CMD_SWITCH_GET_UNASSIGNED_BUFFERS_IN_LEN 0
16680 #define MC_CMD_SWITCH_GET_UNASSIGNED_BUFFERS_OUT_NET_OFST 0
16692 * SF-112079-PS 5.3, the software-defined bits are defined in xpm.h. Returns 0
16696 #define MC_CMD_SET_SECURITY_FUSES 0x126
16704 #define MC_CMD_SET_SECURITY_FUSES_IN_FLAGS_OFST 0
16706 #define MC_CMD_SET_SECURITY_FUSES_IN_SECURE_BOOT_LBN 0
16714 #define MC_CMD_SET_SECURITY_FUSES_OUT_LEN 0
16722 #define MC_CMD_SET_SECURITY_FUSES_V2_OUT_FLAGS_OFST 0
16734 #define MC_CMD_TSA_INFO 0x127
16741 #define MC_CMD_TSA_INFO_IN_OP_HDR_OFST 0
16743 #define MC_CMD_TSA_INFO_IN_OP_LBN 0
16747 #define MC_CMD_TSA_INFO_OP_LOCAL_IP 0x1
16752 #define MC_CMD_TSA_INFO_OP_PKT_SAMPLE 0x2
16771 #define MC_CMD_TSA_INFO_IN_LOCAL_IP_OP_HDR_OFST 0
16778 #define MC_CMD_TSA_INFO_IN_LOCAL_IP_META_PORT_INDEX_LBN 0
16785 #define MC_CMD_TSA_INFO_IP_REASON_TX_ARP 0x0
16787 #define MC_CMD_TSA_INFO_IP_REASON_RX_ARP_PROBE 0x1
16789 #define MC_CMD_TSA_INFO_IP_REASON_RX_GRATUITOUS_ARP 0x2
16791 #define MC_CMD_TSA_INFO_IP_REASON_RX_DHCP_ACK 0x3
16828 #define MC_CMD_TSA_INFO_IN_PKT_SAMPLE_OP_HDR_OFST 0
16833 #define MC_CMD_TSA_INFO_IN_PKT_SAMPLE_META_PORT_INDEX_LBN 0
16858 #define MC_CMD_TSA_INFO_OUT_LEN 0
16865 #define MC_CMD_HOST_INFO 0x128
16873 #define MC_CMD_HOST_INFO_IN_OP_HDR_OFST 0
16875 #define MC_CMD_HOST_INFO_IN_OP_LBN 0
16887 #define MC_CMD_HOST_INFO_OP_GET_UUID 0x0
16892 #define MC_CMD_HOST_INFO_OP_SET_UUID 0x1
16897 #define MC_CMD_HOST_INFO_IN_GET_UUID_OP_HDR_OFST 0
16905 #define MC_CMD_HOST_INFO_OUT_GET_UUID_HOST_UUID_OFST 0
16912 #define MC_CMD_HOST_INFO_IN_SET_UUID_OP_HDR_OFST 0
16922 #define MC_CMD_HOST_INFO_OUT_SET_UUID_LEN 0
16930 #define MC_CMD_TSAN_INFO 0x129
16938 #define MC_CMD_TSAN_INFO_IN_OP_HDR_OFST 0
16940 #define MC_CMD_TSAN_INFO_IN_OP_LBN 0
16946 #define MC_CMD_TSAN_INFO_OP_GET_CFG 0x0
16951 #define MC_CMD_TSAN_INFO_IN_GET_CFG_OP_HDR_OFST 0
16957 #define MC_CMD_TSAN_INFO_OUT_GET_CFG_CONFIG_WORD_OFST 0
16959 #define MC_CMD_TSAN_INFO_OUT_GET_CFG_CAP_FLAGS_LBN 0
16961 #define MC_CMD_TSAN_INFO_OUT_GET_CFG_FLAG_HOST_UUID_VALID_LBN 0
16981 #define MC_CMD_TSAN_INFO_OUT_GET_CFG_V2_CONFIG_WORD_OFST 0
16983 #define MC_CMD_TSAN_INFO_OUT_GET_CFG_V2_CAP_FLAGS_LBN 0
16985 #define MC_CMD_TSAN_INFO_OUT_GET_CFG_V2_FLAG_HOST_UUID_VALID_LBN 0
17021 #define MC_CMD_TSA_STATISTICS 0x130
17029 #define MC_CMD_TSA_STATISTICS_IN_OP_CODE_OFST 0
17034 #define MC_CMD_TSA_STATISTICS_OP_GET_CONFIG 0x0
17036 #define MC_CMD_TSA_STATISTICS_OP_READ_CLEAR 0x1
17041 #define MC_CMD_TSA_STATISTICS_IN_GET_CONFIG_OP_CODE_OFST 0
17051 #define MC_CMD_TSA_STATISTICS_OUT_GET_CONFIG_MAX_STATS_OFST 0
17064 #define MC_CMD_TSA_STATISTICS_IN_READ_CLEAR_OP_CODE_OFST 0
17069 #define MC_CMD_TSA_STATISTICS_IN_READ_CLEAR_READ_LBN 0
17079 #define MC_CMD_TSA_STATISTICS_IN_READ_CLEAR_LIST 0x0
17083 #define MC_CMD_TSA_STATISTICS_IN_READ_CLEAR_RANGE 0x1
17102 #define MC_CMD_TSA_STATISTICS_OUT_READ_CLEAR_NUM_STATS_OFST 0
17115 #define MC_TSA_STATISTICS_ENTRY_TX_STAT_OFST 0
17117 #define MC_TSA_STATISTICS_ENTRY_TX_STAT_LO_OFST 0
17119 #define MC_TSA_STATISTICS_ENTRY_TX_STAT_LBN 0
17136 #define MC_CMD_ERASE_INITIAL_NIC_SECRET 0x131
17142 #define MC_CMD_ERASE_INITIAL_NIC_SECRET_IN_LEN 0
17145 #define MC_CMD_ERASE_INITIAL_NIC_SECRET_OUT_LEN 0
17152 #define MC_CMD_TSA_CONFIG 0x64
17160 #define MC_CMD_TSA_CONFIG_IN_OP_OFST 0
17166 #define MC_CMD_TSA_CONFIG_OP_APPEND 0x1
17168 #define MC_CMD_TSA_CONFIG_OP_RESET 0x2
17173 #define MC_CMD_TSA_CONFIG_OP_READ 0x3
17182 #define MC_CMD_TSA_CONFIG_IN_APPEND_OP_OFST 0
17193 #define MC_CMD_TSA_CONFIG_IN_APPEND_DATA_MINNUM 0
17197 #define MC_CMD_TSA_CONFIG_OUT_APPEND_LEN 0
17204 #define MC_CMD_TSA_CONFIG_IN_RESET_OP_OFST 0
17208 #define MC_CMD_TSA_CONFIG_OUT_RESET_LEN 0
17215 #define MC_CMD_TSA_CONFIG_IN_READ_OP_OFST 0
17226 #define MC_CMD_TSA_CONFIG_OUT_READ_TAG_OFST 0
17234 #define MC_CMD_TSA_CONFIG_OUT_READ_DATA_MINNUM 0
17243 #define MC_TSA_IPV4_ITEM_IPV4_ADDR_META_OFST 0
17245 #define MC_TSA_IPV4_ITEM_PORT_IDX_LBN 0
17247 #define MC_TSA_IPV4_ITEM_IPV4_ADDR_META_LBN 0
17261 #define MC_CMD_TSA_IPADDR 0x65
17272 #define MC_CMD_TSA_IPADDR_IN_OP_HDR_OFST 0
17274 #define MC_CMD_TSA_IPADDR_IN_OP_LBN 0
17283 #define MC_CMD_TSA_IPADDR_OP_VALIDATE_IPV4 0x1
17288 #define MC_CMD_TSA_IPADDR_OP_REMOVE_IPV4 0x2
17298 #define MC_CMD_TSA_IPADDR_IN_VALIDATE_IPV4_OP_HDR_OFST 0
17300 #define MC_CMD_TSA_IPADDR_IN_VALIDATE_IPV4_OP_LBN 0
17314 #define MC_CMD_TSA_IPADDR_OUT_VALIDATE_IPV4_LEN 0
17324 #define MC_CMD_TSA_IPADDR_IN_REMOVE_IPV4_OP_HDR_OFST 0
17326 #define MC_CMD_TSA_IPADDR_IN_REMOVE_IPV4_OP_LBN 0
17340 #define MC_CMD_TSA_IPADDR_OUT_REMOVE_IPV4_LEN 0
17348 #define MC_CMD_SECURE_NIC_INFO 0x132
17356 #define MC_CMD_SECURE_NIC_INFO_IN_OP_HDR_OFST 0
17358 #define MC_CMD_SECURE_NIC_INFO_IN_OP_LBN 0
17363 #define MC_CMD_SECURE_NIC_INFO_OP_STATUS 0x0
17368 #define MC_CMD_SECURE_NIC_INFO_IN_STATUS_OP_HDR_OFST 0
17373 #define MC_CMD_SECURE_NIC_INFO_IN_STATUS_UNUSED 0x0 /* enum */
17375 #define MC_CMD_SECURE_NIC_INFO_IN_STATUS_SF_ADAPTER_AUTH 0x1
17379 #define MC_CMD_SECURE_NIC_INFO_IN_STATUS_TSA_BINDING 0x2
17383 #define MC_CMD_SECURE_NIC_INFO_IN_STATUS_CUSTOMER_ADAPTER_AUTH 0x3
17391 #define MC_CMD_SECURE_NIC_INFO_OUT_STATUS_MSG_SIGNATURE_LEN_OFST 0
17410 #define MC_CMD_SECURE_NIC_INFO_STATUS 0xdb4
17439 #define MC_CMD_TSA_TEST 0x125
17445 #define MC_CMD_TSA_TEST_IN_LEN 0
17448 #define MC_CMD_TSA_TEST_OUT_LEN 0
17459 #define MC_CMD_TSA_RULESET_OVERRIDE 0x12a
17467 #define MC_CMD_TSA_RULESET_OVERRIDE_IN_STATE_OFST 0
17470 #define MC_CMD_TSA_RULESET_OVERRIDE_NONE 0x0
17476 #define MC_CMD_TSA_RULESET_OVERRIDE_BLOCK 0x1
17480 #define MC_CMD_TSA_RULESET_OVERRIDE_ALLOW 0x2
17483 #define MC_CMD_TSA_RULESET_OVERRIDE_OUT_LEN 0
17490 #define MC_CMD_TSAC_REQUEST 0x12b
17498 #define MC_CMD_TSAC_REQUEST_IN_TYPE_OFST 0
17504 #define MC_CMD_TSAC_REQUEST_LOCALIP 0x0
17507 #define MC_CMD_TSAC_REQUEST_OUT_LEN 0
17513 #define MC_CMD_SUC_VERSION 0x134
17519 #define MC_CMD_SUC_VERSION_IN_LEN 0
17524 #define MC_CMD_SUC_VERSION_OUT_VERSION_OFST 0
17542 #define MC_CMD_SUC_BOOT_VERSION_IN_MAGIC_OFST 0
17545 #define MC_CMD_SUC_VERSION_GET_BOOT_VERSION 0xb007700b
17550 #define MC_CMD_SUC_BOOT_VERSION_OUT_VERSION_OFST 0
17557 #define MC_CMD_SUC_MANFTEST 0x135
17565 #define MC_CMD_SUC_MANFTEST_IN_OP_OFST 0
17568 #define MC_CMD_SUC_MANFTEST_WEAROUT_READ 0x0
17570 #define MC_CMD_SUC_MANFTEST_WEAROUT_UPDATE 0x1
17572 #define MC_CMD_SUC_MANFTEST_ADC_CALIBRATE_START 0x2
17574 #define MC_CMD_SUC_MANFTEST_ADC_CALIBRATE_STATUS 0x3
17576 #define MC_CMD_SUC_MANFTEST_ADC_CALIBRATE_RESULT 0x4
17578 #define MC_CMD_SUC_MANFTEST_CONFIG_PCIE_READ 0x5
17580 #define MC_CMD_SUC_MANFTEST_CONFIG_PCIE_WRITE 0x6
17584 #define MC_CMD_SUC_MANFTEST_FRU_WRITE 0x7
17587 #define MC_CMD_SUC_MANFTEST_OUT_LEN 0
17594 #define MC_CMD_SUC_MANFTEST_WEAROUT_READ_IN_OP_OFST 0
17600 #define MC_CMD_SUC_MANFTEST_WEAROUT_READ_OUT_SERIAL_NUMBER_OFST 0
17611 #define MC_CMD_SUC_MANFTEST_WEAROUT_UPDATE_IN_OP_OFST 0
17615 #define MC_CMD_SUC_MANFTEST_WEAROUT_UPDATE_OUT_LEN 0
17622 #define MC_CMD_SUC_MANFTEST_ADC_CALIBRATE_START_IN_OP_OFST 0
17626 #define MC_CMD_SUC_MANFTEST_ADC_CALIBRATE_START_OUT_LEN 0
17633 #define MC_CMD_SUC_MANFTEST_ADC_CALIBRATE_STATUS_IN_OP_OFST 0
17639 #define MC_CMD_SUC_MANFTEST_ADC_CALIBRATE_STATUS_OUT_FLAGS_OFST 0
17641 #define MC_CMD_SUC_MANFTEST_ADC_CALIBRATE_STATUS_OUT_CALIBRATING_LBN 0
17655 #define MC_CMD_SUC_MANFTEST_ADC_CALIBRATE_RESULT_IN_OP_OFST 0
17661 #define MC_CMD_SUC_MANFTEST_ADC_CALIBRATE_RESULT_OUT_VALUE_OFST 0
17670 #define MC_CMD_SUC_MANFTEST_CONFIG_PCIE_READ_IN_OP_OFST 0
17676 #define MC_CMD_SUC_MANFTEST_CONFIG_PCIE_READ_OUT_VENDOR_ID_OFST 0
17687 #define MC_CMD_SUC_MANFTEST_CONFIG_PCIE_WRITE_IN_OP_OFST 0
17697 #define MC_CMD_SUC_MANFTEST_CONFIG_PCIE_WRITE_OUT_LEN 0
17704 #define MC_CMD_SUC_MANFTEST_FRU_WRITE_IN_OP_OFST 0
17708 #define MC_CMD_SUC_MANFTEST_FRU_WRITE_OUT_LEN 0
17714 #define MC_CMD_GET_CERTIFICATE 0x12c
17722 #define MC_CMD_GET_CERTIFICATE_IN_TYPE_OFST 0
17724 #define MC_CMD_GET_CERTIFICATE_IN_UNUSED 0x0 /* enum */
17725 #define MC_CMD_GET_CERTIFICATE_IN_AAC 0x1 /* enum */
17729 #define MC_CMD_GET_CERTIFICATE_IN_ADAPTER_AUTH 0x1
17730 #define MC_CMD_GET_CERTIFICATE_IN_AASC 0x2 /* enum */
17736 #define MC_CMD_GET_CERTIFICATE_IN_ADAPTER_AUTH_SIGNING 0x2
17737 #define MC_CMD_GET_CERTIFICATE_IN_CUSTOMER_AAC 0x3 /* enum */
17743 #define MC_CMD_GET_CERTIFICATE_IN_CUSTOMER_ADAPTER_AUTH 0x3
17744 #define MC_CMD_GET_CERTIFICATE_IN_CUSTOMER_AASC 0x4 /* enum */
17750 #define MC_CMD_GET_CERTIFICATE_IN_CUSTOMER_ADAPTER_AUTH_SIGNING 0x4
17762 #define MC_CMD_GET_CERTIFICATE_OUT_TYPE_OFST 0
17784 #define MC_CMD_GET_NIC_GLOBAL 0x12d
17795 #define MC_CMD_GET_NIC_GLOBAL_IN_KEY_OFST 0
17801 #define MC_CMD_GET_NIC_GLOBAL_OUT_VALUE_OFST 0
17810 #define MC_CMD_SET_NIC_GLOBAL 0x12e
17820 #define MC_CMD_SET_NIC_GLOBAL_IN_KEY_OFST 0
17830 #define MC_CMD_SET_NIC_GLOBAL_IN_FIRMWARE_SUBVARIANT 0x1
17838 #define MC_CMD_SET_NIC_GLOBAL_IN_FW_SUBVARIANT_DEFAULT 0x0
17847 #define MC_CMD_SET_NIC_GLOBAL_IN_FW_SUBVARIANT_NO_TX_CSUM 0x1
17856 #define MC_CMD_LTSSM_TRACE_POLL 0x12f
17868 #define MC_CMD_LTSSM_TRACE_POLL_IN_MAX_ROW_COUNT_OFST 0
17875 #define MC_CMD_LTSSM_TRACE_POLL_OUT_FLAGS_OFST 0
17877 #define MC_CMD_LTSSM_TRACE_POLL_OUT_HW_BUFFER_OVERFLOW_LBN 0
17890 #define MC_CMD_LTSSM_TRACE_POLL_OUT_ROWS_MINNUM 0
17892 #define MC_CMD_LTSSM_TRACE_POLL_OUT_LTSSM_STATE_LBN 0
17902 * reported in picoseconds. 0 <= TIMESTAMP_PS < 1000000 timestamp in seconds =