Lines Matching +full:0 +full:xc01
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
82 // The cpu line is second (after the 'processor: 0' line), so if this in getHostCPUNameForPowerPC()
90 size_t CPULen = 0; in getHostCPUNameForPowerPC()
173 for (unsigned I = 0, E = Lines.size(); I != E; ++I) { in getHostCPUNameForARM()
182 if (Implementer == "0x41") { // ARM Ltd. in getHostCPUNameForARM()
189 // The CPU part is a 3 digit hexadecimal number with a 0x prefix. The in getHostCPUNameForARM()
195 .Case("0x926", "arm926ej-s") in getHostCPUNameForARM()
196 .Case("0xb02", "mpcore") in getHostCPUNameForARM()
197 .Case("0xb36", "arm1136j-s") in getHostCPUNameForARM()
198 .Case("0xb56", "arm1156t2-s") in getHostCPUNameForARM()
199 .Case("0xb76", "arm1176jz-s") in getHostCPUNameForARM()
200 .Case("0xc05", "cortex-a5") in getHostCPUNameForARM()
201 .Case("0xc07", "cortex-a7") in getHostCPUNameForARM()
202 .Case("0xc08", "cortex-a8") in getHostCPUNameForARM()
203 .Case("0xc09", "cortex-a9") in getHostCPUNameForARM()
204 .Case("0xc0f", "cortex-a15") in getHostCPUNameForARM()
205 .Case("0xc0e", "cortex-a17") in getHostCPUNameForARM()
206 .Case("0xc20", "cortex-m0") in getHostCPUNameForARM()
207 .Case("0xc23", "cortex-m3") in getHostCPUNameForARM()
208 .Case("0xc24", "cortex-m4") in getHostCPUNameForARM()
209 .Case("0xc27", "cortex-m7") in getHostCPUNameForARM()
210 .Case("0xd20", "cortex-m23") in getHostCPUNameForARM()
211 .Case("0xd21", "cortex-m33") in getHostCPUNameForARM()
212 .Case("0xd24", "cortex-m52") in getHostCPUNameForARM()
213 .Case("0xd22", "cortex-m55") in getHostCPUNameForARM()
214 .Case("0xd23", "cortex-m85") in getHostCPUNameForARM()
215 .Case("0xc18", "cortex-r8") in getHostCPUNameForARM()
216 .Case("0xd13", "cortex-r52") in getHostCPUNameForARM()
217 .Case("0xd16", "cortex-r52plus") in getHostCPUNameForARM()
218 .Case("0xd15", "cortex-r82") in getHostCPUNameForARM()
219 .Case("0xd14", "cortex-r82ae") in getHostCPUNameForARM()
220 .Case("0xd02", "cortex-a34") in getHostCPUNameForARM()
221 .Case("0xd04", "cortex-a35") in getHostCPUNameForARM()
222 .Case("0xd03", "cortex-a53") in getHostCPUNameForARM()
223 .Case("0xd05", "cortex-a55") in getHostCPUNameForARM()
224 .Case("0xd46", "cortex-a510") in getHostCPUNameForARM()
225 .Case("0xd80", "cortex-a520") in getHostCPUNameForARM()
226 .Case("0xd88", "cortex-a520ae") in getHostCPUNameForARM()
227 .Case("0xd07", "cortex-a57") in getHostCPUNameForARM()
228 .Case("0xd06", "cortex-a65") in getHostCPUNameForARM()
229 .Case("0xd43", "cortex-a65ae") in getHostCPUNameForARM()
230 .Case("0xd08", "cortex-a72") in getHostCPUNameForARM()
231 .Case("0xd09", "cortex-a73") in getHostCPUNameForARM()
232 .Case("0xd0a", "cortex-a75") in getHostCPUNameForARM()
233 .Case("0xd0b", "cortex-a76") in getHostCPUNameForARM()
234 .Case("0xd0e", "cortex-a76ae") in getHostCPUNameForARM()
235 .Case("0xd0d", "cortex-a77") in getHostCPUNameForARM()
236 .Case("0xd41", "cortex-a78") in getHostCPUNameForARM()
237 .Case("0xd42", "cortex-a78ae") in getHostCPUNameForARM()
238 .Case("0xd4b", "cortex-a78c") in getHostCPUNameForARM()
239 .Case("0xd47", "cortex-a710") in getHostCPUNameForARM()
240 .Case("0xd4d", "cortex-a715") in getHostCPUNameForARM()
241 .Case("0xd81", "cortex-a720") in getHostCPUNameForARM()
242 .Case("0xd89", "cortex-a720ae") in getHostCPUNameForARM()
243 .Case("0xd87", "cortex-a725") in getHostCPUNameForARM()
244 .Case("0xd44", "cortex-x1") in getHostCPUNameForARM()
245 .Case("0xd4c", "cortex-x1c") in getHostCPUNameForARM()
246 .Case("0xd48", "cortex-x2") in getHostCPUNameForARM()
247 .Case("0xd4e", "cortex-x3") in getHostCPUNameForARM()
248 .Case("0xd82", "cortex-x4") in getHostCPUNameForARM()
249 .Case("0xd85", "cortex-x925") in getHostCPUNameForARM()
250 .Case("0xd4a", "neoverse-e1") in getHostCPUNameForARM()
251 .Case("0xd0c", "neoverse-n1") in getHostCPUNameForARM()
252 .Case("0xd49", "neoverse-n2") in getHostCPUNameForARM()
253 .Case("0xd8e", "neoverse-n3") in getHostCPUNameForARM()
254 .Case("0xd40", "neoverse-v1") in getHostCPUNameForARM()
255 .Case("0xd4f", "neoverse-v2") in getHostCPUNameForARM()
256 .Case("0xd84", "neoverse-v3") in getHostCPUNameForARM()
257 .Case("0xd83", "neoverse-v3ae") in getHostCPUNameForARM()
261 if (Implementer == "0x42" || Implementer == "0x43") { // Broadcom | Cavium. in getHostCPUNameForARM()
263 .Case("0x516", "thunderx2t99") in getHostCPUNameForARM()
264 .Case("0x0516", "thunderx2t99") in getHostCPUNameForARM()
265 .Case("0xaf", "thunderx2t99") in getHostCPUNameForARM()
266 .Case("0x0af", "thunderx2t99") in getHostCPUNameForARM()
267 .Case("0xa1", "thunderxt88") in getHostCPUNameForARM()
268 .Case("0x0a1", "thunderxt88") in getHostCPUNameForARM()
272 if (Implementer == "0x46") { // Fujitsu Ltd. in getHostCPUNameForARM()
274 .Case("0x001", "a64fx") in getHostCPUNameForARM()
278 if (Implementer == "0x4e") { // NVIDIA Corporation in getHostCPUNameForARM()
280 .Case("0x004", "carmel") in getHostCPUNameForARM()
284 if (Implementer == "0x48") // HiSilicon Technologies, Inc. in getHostCPUNameForARM()
285 // The CPU part is a 3 digit hexadecimal number with a 0x prefix. The in getHostCPUNameForARM()
289 .Case("0xd01", "tsv110") in getHostCPUNameForARM()
292 if (Implementer == "0x51") // Qualcomm Technologies, Inc. in getHostCPUNameForARM()
293 // The CPU part is a 3 digit hexadecimal number with a 0x prefix. The in getHostCPUNameForARM()
297 .Case("0x06f", "krait") // APQ8064 in getHostCPUNameForARM()
298 .Case("0x201", "kryo") in getHostCPUNameForARM()
299 .Case("0x205", "kryo") in getHostCPUNameForARM()
300 .Case("0x211", "kryo") in getHostCPUNameForARM()
301 .Case("0x800", "cortex-a73") // Kryo 2xx Gold in getHostCPUNameForARM()
302 .Case("0x801", "cortex-a73") // Kryo 2xx Silver in getHostCPUNameForARM()
303 .Case("0x802", "cortex-a75") // Kryo 3xx Gold in getHostCPUNameForARM()
304 .Case("0x803", "cortex-a75") // Kryo 3xx Silver in getHostCPUNameForARM()
305 .Case("0x804", "cortex-a76") // Kryo 4xx Gold in getHostCPUNameForARM()
306 .Case("0x805", "cortex-a76") // Kryo 4xx/5xx Silver in getHostCPUNameForARM()
307 .Case("0xc00", "falkor") in getHostCPUNameForARM()
308 .Case("0xc01", "saphira") in getHostCPUNameForARM()
309 .Case("0x001", "oryon-1") in getHostCPUNameForARM()
311 if (Implementer == "0x53") { // Samsung Electronics Co., Ltd. in getHostCPUNameForARM()
314 unsigned Variant = 0, Part = 0; in getHostCPUNameForARM()
320 I.ltrim("\t :").getAsInteger(0, Variant); in getHostCPUNameForARM()
326 I.ltrim("\t :").getAsInteger(0, Part); in getHostCPUNameForARM()
333 case 0x1002: in getHostCPUNameForARM()
335 case 0x1003: in getHostCPUNameForARM()
340 if (Implementer == "0x6d") { // Microsoft Corporation. in getHostCPUNameForARM()
343 .Case("0xd49", "neoverse-n2") in getHostCPUNameForARM()
347 if (Implementer == "0xc0") { // Ampere Computing in getHostCPUNameForARM()
349 .Case("0xac3", "ampere1") in getHostCPUNameForARM()
350 .Case("0xac4", "ampere1a") in getHostCPUNameForARM()
351 .Case("0xac5", "ampere1b") in getHostCPUNameForARM()
397 // The "processor 0:" line comes after a fair amount of other information, in getHostCPUNameForS390x()
404 for (unsigned I = 0, E = Lines.size(); I != E; ++I) in getHostCPUNameForS390x()
417 for (unsigned I = 0, E = CPUFeatures.size(); I != E; ++I) { in getHostCPUNameForS390x()
423 for (unsigned I = 0, E = Lines.size(); I != E; ++I) { in getHostCPUNameForS390x()
446 for (unsigned I = 0, E = Lines.size(); I != E; ++I) { in getHostCPUNameForRISCV()
464 /* BPF_MOV64_IMM(BPF_REG_0, 0) */ in getHostCPUNameForBPF()
465 { 0xb7, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, in getHostCPUNameForBPF()
467 0xb7, 0x2, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, in getHostCPUNameForBPF()
469 0xae, 0x20, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, in getHostCPUNameForBPF()
471 0xb7, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, in getHostCPUNameForBPF()
473 0x95, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }; in getHostCPUNameForBPF()
476 /* BPF_MOV64_IMM(BPF_REG_0, 0) */ in getHostCPUNameForBPF()
477 { 0xb7, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, in getHostCPUNameForBPF()
479 0xb7, 0x2, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, in getHostCPUNameForBPF()
481 0xad, 0x20, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, in getHostCPUNameForBPF()
483 0xb7, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, in getHostCPUNameForBPF()
485 0x95, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }; in getHostCPUNameForBPF()
505 if (fd >= 0) { in getHostCPUNameForBPF()
511 memset(&attr, 0, sizeof(attr)); in getHostCPUNameForBPF()
517 if (fd >= 0) { in getHostCPUNameForBPF()
542 " xorl $0x00200000,%%eax\n" in isCpuIdSupported()
547 " movl $0,%0\n" in isCpuIdSupported()
550 " movl $1,%0\n" in isCpuIdSupported()
591 *rEAX = registers[0]; in getX86CpuIDAndInfo()
607 unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0; in getVendorSignature()
611 *MaxLeaf = 0; in getVendorSignature()
616 if (getX86CpuIDAndInfo(0, MaxLeaf, &EBX, &ECX, &EDX) || *MaxLeaf < 1) in getVendorSignature()
620 if (EBX == 0x756e6547 && EDX == 0x49656e69 && ECX == 0x6c65746e) in getVendorSignature()
624 if (EBX == 0x68747541 && EDX == 0x69746e65 && ECX == 0x444d4163) in getVendorSignature()
666 *rEAX = registers[0]; in getX86CpuIDAndInfoEx()
676 // Read control register 0 (XCR0). Used to detect features such as AVX.
682 __asm__(".byte 0x0f, 0x01, 0xd0" : "=a"(*rEAX), "=d"(*rEDX) : "c"(0)); in getX86XCR0()
696 *Family = (EAX >> 8) & 0xf; // Bits 8 - 11 in detectX86FamilyModel()
697 *Model = (EAX >> 4) & 0xf; // Bits 4 - 7 in detectX86FamilyModel()
698 if (*Family == 6 || *Family == 0xf) { in detectX86FamilyModel()
699 if (*Family == 0xf) in detectX86FamilyModel()
701 *Family += (EAX >> 20) & 0xff; // Bits 20 - 27 in detectX86FamilyModel()
703 *Model += ((EAX >> 16) & 0xf) << 4; // Bits 16 - 19 in detectX86FamilyModel()
707 #define testFeature(F) (Features[F / 32] & (1 << (F % 32))) != 0
732 case 0x0f: // Intel Core 2 Duo processor, Intel Core 2 Duo mobile in getIntelProcessorTypeAndSubtype()
736 // 0Fh. All processors are manufactured using the 65 nm process. in getIntelProcessorTypeAndSubtype()
737 case 0x16: // Intel Celeron processor model 16h. All processors are in getIntelProcessorTypeAndSubtype()
742 case 0x17: // Intel Core 2 Extreme processor, Intel Xeon processor, model in getIntelProcessorTypeAndSubtype()
746 case 0x1d: // Intel Xeon processor MP. All processors are manufactured using in getIntelProcessorTypeAndSubtype()
751 case 0x1a: // Intel Core i7 processor and Intel Xeon processor. All in getIntelProcessorTypeAndSubtype()
753 case 0x1e: // Intel(R) Core(TM) i7 CPU 870 @ 2.93GHz. in getIntelProcessorTypeAndSubtype()
755 case 0x1f: in getIntelProcessorTypeAndSubtype()
756 case 0x2e: // Nehalem EX in getIntelProcessorTypeAndSubtype()
761 case 0x25: // Intel Core i7, laptop version. in getIntelProcessorTypeAndSubtype()
762 case 0x2c: // Intel Core i7 processor and Intel Xeon processor. All in getIntelProcessorTypeAndSubtype()
764 case 0x2f: // Westmere EX in getIntelProcessorTypeAndSubtype()
769 case 0x2a: // Intel Core i7 processor. All processors are manufactured in getIntelProcessorTypeAndSubtype()
771 case 0x2d: in getIntelProcessorTypeAndSubtype()
776 case 0x3a: in getIntelProcessorTypeAndSubtype()
777 case 0x3e: // Ivy Bridge EP in getIntelProcessorTypeAndSubtype()
784 case 0x3c: in getIntelProcessorTypeAndSubtype()
785 case 0x3f: in getIntelProcessorTypeAndSubtype()
786 case 0x45: in getIntelProcessorTypeAndSubtype()
787 case 0x46: in getIntelProcessorTypeAndSubtype()
794 case 0x3d: in getIntelProcessorTypeAndSubtype()
795 case 0x47: in getIntelProcessorTypeAndSubtype()
796 case 0x4f: in getIntelProcessorTypeAndSubtype()
797 case 0x56: in getIntelProcessorTypeAndSubtype()
804 case 0x4e: // Skylake mobile in getIntelProcessorTypeAndSubtype()
805 case 0x5e: // Skylake desktop in getIntelProcessorTypeAndSubtype()
806 case 0x8e: // Kaby Lake mobile in getIntelProcessorTypeAndSubtype()
807 case 0x9e: // Kaby Lake desktop in getIntelProcessorTypeAndSubtype()
808 case 0xa5: // Comet Lake-H/S in getIntelProcessorTypeAndSubtype()
809 case 0xa6: // Comet Lake-U in getIntelProcessorTypeAndSubtype()
816 case 0xa7: in getIntelProcessorTypeAndSubtype()
823 case 0x55: in getIntelProcessorTypeAndSubtype()
838 case 0x66: in getIntelProcessorTypeAndSubtype()
845 case 0x7d: in getIntelProcessorTypeAndSubtype()
846 case 0x7e: in getIntelProcessorTypeAndSubtype()
853 case 0x8c: in getIntelProcessorTypeAndSubtype()
854 case 0x8d: in getIntelProcessorTypeAndSubtype()
861 case 0x97: in getIntelProcessorTypeAndSubtype()
862 case 0x9a: in getIntelProcessorTypeAndSubtype()
864 case 0xbe: in getIntelProcessorTypeAndSubtype()
866 case 0xb7: in getIntelProcessorTypeAndSubtype()
867 case 0xba: in getIntelProcessorTypeAndSubtype()
868 case 0xbf: in getIntelProcessorTypeAndSubtype()
870 case 0xaa: in getIntelProcessorTypeAndSubtype()
871 case 0xac: in getIntelProcessorTypeAndSubtype()
878 case 0xc5: in getIntelProcessorTypeAndSubtype()
885 case 0xc6: in getIntelProcessorTypeAndSubtype()
887 case 0xbd: in getIntelProcessorTypeAndSubtype()
894 case 0xcc: in getIntelProcessorTypeAndSubtype()
901 case 0xad: in getIntelProcessorTypeAndSubtype()
908 case 0xae: in getIntelProcessorTypeAndSubtype()
915 case 0x6a: in getIntelProcessorTypeAndSubtype()
916 case 0x6c: in getIntelProcessorTypeAndSubtype()
923 case 0xcf: in getIntelProcessorTypeAndSubtype()
925 case 0x8f: in getIntelProcessorTypeAndSubtype()
931 case 0x1c: // Most 45 nm Intel Atom processors in getIntelProcessorTypeAndSubtype()
932 case 0x26: // 45 nm Atom Lincroft in getIntelProcessorTypeAndSubtype()
933 case 0x27: // 32 nm Atom Medfield in getIntelProcessorTypeAndSubtype()
934 case 0x35: // 32 nm Atom Midview in getIntelProcessorTypeAndSubtype()
935 case 0x36: // 32 nm Atom Midview in getIntelProcessorTypeAndSubtype()
941 case 0x37: in getIntelProcessorTypeAndSubtype()
942 case 0x4a: in getIntelProcessorTypeAndSubtype()
943 case 0x4d: in getIntelProcessorTypeAndSubtype()
944 case 0x5a: in getIntelProcessorTypeAndSubtype()
945 case 0x5d: in getIntelProcessorTypeAndSubtype()
946 case 0x4c: // really airmont in getIntelProcessorTypeAndSubtype()
951 case 0x5c: // Apollo Lake in getIntelProcessorTypeAndSubtype()
952 case 0x5f: // Denverton in getIntelProcessorTypeAndSubtype()
956 case 0x7a: in getIntelProcessorTypeAndSubtype()
960 case 0x86: in getIntelProcessorTypeAndSubtype()
961 case 0x8a: // Lakefield in getIntelProcessorTypeAndSubtype()
962 case 0x96: // Elkhart Lake in getIntelProcessorTypeAndSubtype()
963 case 0x9c: // Jasper Lake in getIntelProcessorTypeAndSubtype()
969 case 0xaf: in getIntelProcessorTypeAndSubtype()
975 case 0xb6: in getIntelProcessorTypeAndSubtype()
981 case 0xdd: in getIntelProcessorTypeAndSubtype()
987 case 0x57: in getIntelProcessorTypeAndSubtype()
991 case 0x85: in getIntelProcessorTypeAndSubtype()
1075 const char *CPU = 0; in getAMDProcessorTypeAndSubtype()
1136 if (Model >= 0x60 && Model <= 0x7f) { in getAMDProcessorTypeAndSubtype()
1141 if (Model >= 0x30 && Model <= 0x3f) { in getAMDProcessorTypeAndSubtype()
1146 if ((Model >= 0x10 && Model <= 0x1f) || Model == 0x02) { in getAMDProcessorTypeAndSubtype()
1151 if (Model <= 0x0f) { in getAMDProcessorTypeAndSubtype()
1153 break; // 00h-0Fh: Bulldozer in getAMDProcessorTypeAndSubtype()
1163 if ((Model >= 0x30 && Model <= 0x3f) || (Model == 0x47) || in getAMDProcessorTypeAndSubtype()
1164 (Model >= 0x60 && Model <= 0x67) || (Model >= 0x68 && Model <= 0x6f) || in getAMDProcessorTypeAndSubtype()
1165 (Model >= 0x70 && Model <= 0x7f) || (Model >= 0x84 && Model <= 0x87) || in getAMDProcessorTypeAndSubtype()
1166 (Model >= 0x90 && Model <= 0x97) || (Model >= 0x98 && Model <= 0x9f) || in getAMDProcessorTypeAndSubtype()
1167 (Model >= 0xa0 && Model <= 0xaf)) { in getAMDProcessorTypeAndSubtype()
1181 if ((Model >= 0x10 && Model <= 0x1f) || (Model >= 0x20 && Model <= 0x2f)) { in getAMDProcessorTypeAndSubtype()
1192 if (Model <= 0x0f || (Model >= 0x20 && Model <= 0x2f) || in getAMDProcessorTypeAndSubtype()
1193 (Model >= 0x30 && Model <= 0x3f) || (Model >= 0x40 && Model <= 0x4f) || in getAMDProcessorTypeAndSubtype()
1194 (Model >= 0x50 && Model <= 0x5f)) { in getAMDProcessorTypeAndSubtype()
1195 // Family 19h Models 00h-0Fh (Genesis, Chagall) Zen 3 in getAMDProcessorTypeAndSubtype()
1203 if ((Model >= 0x10 && Model <= 0x1f) || (Model >= 0x60 && Model <= 0x6f) || in getAMDProcessorTypeAndSubtype()
1204 (Model >= 0x70 && Model <= 0x77) || (Model >= 0x78 && Model <= 0x7f) || in getAMDProcessorTypeAndSubtype()
1205 (Model >= 0xa0 && Model <= 0xaf)) { in getAMDProcessorTypeAndSubtype()
1219 if (Model <= 0x77) { in getAMDProcessorTypeAndSubtype()
1220 // Models 00h-0Fh (Breithorn). in getAMDProcessorTypeAndSubtype()
1261 if ((ECX >> 0) & 1) in getAvailableFeatures()
1288 ((EAX & 0x6) == 0x6); in getAvailableFeatures()
1296 bool HasAVX512Save = HasAVX && ((EAX & 0xe0) == 0xe0); in getAvailableFeatures()
1303 MaxLeaf >= 0x7 && !getX86CpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX); in getAvailableFeatures()
1354 // EAX from subleaf 0 is the maximum subleaf supported. Some CPUs don't in getAvailableFeatures()
1355 // return all 0s for invalid subleaves so check the limit. in getAvailableFeatures()
1358 !getX86CpuIDAndInfoEx(0x7, 0x1, &EAX, &EBX, &ECX, &EDX); in getAvailableFeatures()
1363 getX86CpuIDAndInfo(0x80000000, &MaxExtLevel, &EBX, &ECX, &EDX); in getAvailableFeatures()
1365 bool HasExtLeaf1 = MaxExtLevel >= 0x80000001 && in getAvailableFeatures()
1366 !getX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX); in getAvailableFeatures()
1379 unsigned MaxLeaf = 0; in getHostCPUName()
1384 unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0; in getHostCPUName()
1385 getX86CpuIDAndInfo(0x1, &EAX, &EBX, &ECX, &EDX); in getHostCPUName()
1387 unsigned Family = 0, Model = 0; in getHostCPUName()
1388 unsigned Features[(X86::CPU_FEATURE_MAX + 31) / 32] = {0}; in getHostCPUName()
1394 unsigned Type = 0; in getHostCPUName()
1395 unsigned Subtype = 0; in getHostCPUName()
1480 int *StartToCVTOffset = reinterpret_cast<int *>(0x10); in getHostCPUName()
1485 ReadValue = (ReadValue & 0x7FFFFFFF); in getHostCPUName()
1495 bool HaveVectorSupport = CVT[244] & 0x80; in getHostCPUName()
1499 #define CPUFAMILY_ARM_SWIFT 0x1e2d6381
1500 #define CPUFAMILY_ARM_CYCLONE 0x37a09642
1501 #define CPUFAMILY_ARM_TYPHOON 0x2c91a47e
1502 #define CPUFAMILY_ARM_TWISTER 0x92fb37c8
1503 #define CPUFAMILY_ARM_HURRICANE 0x67ceee93
1504 #define CPUFAMILY_ARM_MONSOON_MISTRAL 0xe81e7ef6
1505 #define CPUFAMILY_ARM_VORTEX_TEMPEST 0x07d34b9f
1506 #define CPUFAMILY_ARM_LIGHTNING_THUNDER 0x462504d2
1507 #define CPUFAMILY_ARM_FIRESTORM_ICESTORM 0x1b588bb3
1508 #define CPUFAMILY_ARM_BLIZZARD_AVALANCHE 0xda33d83d
1509 #define CPUFAMILY_ARM_EVEREST_SAWTOOTH 0x8765edea
1514 sysctlbyname("hw.cpufamily", &Family, &Length, NULL, 0); in getHostCPUName()
1569 case 0x40000: in getHostCPUName()
1575 case 0x80000: in getHostCPUName()
1588 switch (processor_id & 0xf000) { in getHostCPUName()
1589 case 0xc000: // Loongson 64bit, 4-issue in getHostCPUName()
1591 case 0xd000: // Loongson 64bit, 6-issue in getHostCPUName()
1624 for (unsigned I = 0, E = Lines.size(); I != E; ++I) { in getHostCPUNameForSPARC()
1741 unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0; in getHostCPUFeatures()
1745 if (getX86CpuIDAndInfo(0, &MaxLevel, &EBX, &ECX, &EDX) || MaxLevel < 1) in getHostCPUFeatures()
1757 Features["sse3"] = (ECX >> 0) & 1; in getHostCPUFeatures()
1773 bool HasAVXSave = HasXSave && ((ECX >> 28) & 1) && ((EAX & 0x6) == 0x6); in getHostCPUFeatures()
1781 bool HasAVX512Save = HasAVXSave && ((EAX & 0xe0) == 0xe0); in getHostCPUFeatures()
1794 getX86CpuIDAndInfo(0x80000000, &MaxExtLevel, &EBX, &ECX, &EDX); in getHostCPUFeatures()
1796 bool HasExtLeaf1 = MaxExtLevel >= 0x80000001 && in getHostCPUFeatures()
1797 !getX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX); in getHostCPUFeatures()
1798 Features["sahf"] = HasExtLeaf1 && ((ECX >> 0) & 1); in getHostCPUFeatures()
1811 // using the 0x80000008 leaf of the CPUID instruction in getHostCPUFeatures()
1812 bool HasExtLeaf8 = MaxExtLevel >= 0x80000008 && in getHostCPUFeatures()
1813 !getX86CpuIDAndInfo(0x80000008, &EAX, &EBX, &ECX, &EDX); in getHostCPUFeatures()
1814 Features["clzero"] = HasExtLeaf8 && ((EBX >> 0) & 1); in getHostCPUFeatures()
1819 MaxLevel >= 7 && !getX86CpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX); in getHostCPUFeatures()
1821 Features["fsgsbase"] = HasLeaf7 && ((EBX >> 0) & 1); in getHostCPUFeatures()
1869 // EAX=0x7, ECX=0x0 indicates the availability of the instruction (via the 18th in getHostCPUFeatures()
1870 // bit of EDX), while the EAX=0x1b leaf returns information on the in getHostCPUFeatures()
1882 // EAX from subleaf 0 is the maximum subleaf supported. Some CPUs don't in getHostCPUFeatures()
1883 // return all 0s for invalid subleaves so check the limit. in getHostCPUFeatures()
1886 !getX86CpuIDAndInfoEx(0x7, 0x1, &EAX, &EBX, &ECX, &EDX); in getHostCPUFeatures()
1887 Features["sha512"] = HasLeaf7Subleaf1 && ((EAX >> 0) & 1); in getHostCPUFeatures()
1912 bool HasLeafD = MaxLevel >= 0xd && in getHostCPUFeatures()
1913 !getX86CpuIDAndInfoEx(0xd, 0x1, &EAX, &EBX, &ECX, &EDX); in getHostCPUFeatures()
1916 Features["xsaveopt"] = HasLeafD && ((EAX >> 0) & 1) && HasAVXSave; in getHostCPUFeatures()
1920 bool HasLeaf14 = MaxLevel >= 0x14 && in getHostCPUFeatures()
1921 !getX86CpuIDAndInfoEx(0x14, 0x0, &EAX, &EBX, &ECX, &EDX); in getHostCPUFeatures()
1926 MaxLevel >= 0x19 && !getX86CpuIDAndInfo(0x19, &EAX, &EBX, &ECX, &EDX); in getHostCPUFeatures()
1930 MaxLevel >= 0x24 && !getX86CpuIDAndInfo(0x24, &EAX, &EBX, &ECX, &EDX); in getHostCPUFeatures()
1949 for (unsigned I = 0, E = Lines.size(); I != E; ++I) in getHostCPUFeatures()
1957 enum { CAP_AES = 0x1, CAP_PMULL = 0x2, CAP_SHA1 = 0x4, CAP_SHA2 = 0x8 }; in getHostCPUFeatures()
1958 uint32_t crypto = 0; in getHostCPUFeatures()
1961 for (unsigned I = 0, E = CPUFeatures.size(); I != E; ++I) { in getHostCPUFeatures()
2024 uint32_t cpucfg2 = 0x2; in getHostCPUFeatures()
2045 RISCVHwProbe Query[]{{/*RISCV_HWPROBE_KEY_BASE_BEHAVIOR=*/3, 0}, in getHostCPUFeatures()
2046 {/*RISCV_HWPROBE_KEY_IMA_EXT_0=*/4, 0}}; in getHostCPUFeatures()
2048 /*pair_count=*/std::size(Query), /*cpu_count=*/0, in getHostCPUFeatures()
2049 /*cpus=*/0, /*flags=*/0); in getHostCPUFeatures()
2050 if (Ret != 0) in getHostCPUFeatures()
2054 uint64_t BaseMask = Query[0].Value; in getHostCPUFeatures()
2063 Features["f"] = ExtMask & (1 << 0); // RISCV_HWPROBE_IMA_FD in getHostCPUFeatures()
2064 Features["d"] = ExtMask & (1 << 0); // RISCV_HWPROBE_IMA_FD in getHostCPUFeatures()