Lines Matching +full:0 +full:xc01
34 #clock-cells = <0>;
41 #clock-cells = <0>;
49 #size-cells = <0>;
54 reg = <0x0 0x100>;
74 reg = <0x0 0x101>;
89 reg = <0x0 0x102>;
104 reg = <0x0 0x103>;
116 CPU4: cpu@0 {
119 reg = <0x0 0x0>;
139 reg = <0x0 0x1>;
154 reg = <0x0 0x2>;
169 reg = <0x0 0x3>;
222 PWR_CPU_SLEEP_0: cpu-sleep-0-0 {
225 arm,psci-suspend-param = <0x40000002>;
231 PWR_CPU_SLEEP_1: cpu-sleep-0-1 {
234 arm,psci-suspend-param = <0x40000003>;
241 PERF_CPU_SLEEP_0: cpu-sleep-1-0 {
244 arm,psci-suspend-param = <0x40000002>;
253 arm,psci-suspend-param = <0x40000003>;
260 PWR_CLUSTER_SLEEP_0: cluster-sleep-0-0 {
263 arm,psci-suspend-param = <0x400000F2>;
270 PWR_CLUSTER_SLEEP_1: cluster-sleep-0-1 {
273 arm,psci-suspend-param = <0x400000F3>;
280 PWR_CLUSTER_SLEEP_2: cluster-sleep-0-2 {
283 arm,psci-suspend-param = <0x400000F4>;
290 PERF_CLUSTER_SLEEP_0: cluster-sleep-1-0 {
293 arm,psci-suspend-param = <0x400000F2>;
303 arm,psci-suspend-param = <0x400000F3>;
313 arm,psci-suspend-param = <0x400000F4>;
331 reg = <0x0 0x80000000 0x0 0x0>;
371 mboxes = <&apcs_glb 0>;
437 reg = <0x0 0x85600000 0x0 0x100000>;
442 reg = <0x0 0x85700000 0x0 0x100000>;
447 reg = <0x0 0x85800000 0x0 0x600000>;
453 reg = <0x0 0x85e00000 0x0 0x200000>;
461 reg = <0 0x86000000 0 0x200000>;
466 reg = <0x0 0x86200000 0x0 0x3300000>;
471 reg = <0x0 0x8ac00000 0x0 0x7e00000>;
476 reg = <0x0 0x92a00000 0x0 0x1e00000>;
481 reg = <0x0 0x94800000 0x0 0x200000>;
486 reg = <0x0 0x94a00000 0x0 0x100000>;
491 reg = <0x0 0x9f800000 0x0 0x800000>;
496 reg = <0x0 0xf6000000 0x0 0x800000>;
501 reg = <0x0 0xf6800000 0x0 0x1400000>;
507 reg = <0x0 0xfed00000 0x0 0xa00000>;
523 qcom,local-pid = <0>;
543 qcom,local-pid = <0>;
558 soc@0 {
561 ranges = <0 0 0 0xffffffff>;
569 reg = <0x00100000 0x94000>;
578 reg = <0x00778000 0x7000>;
583 reg = <0x00780000 0x621c>;
588 reg = <0x243 0x1>;
593 reg = <0x41a2 0x1>;
600 reg = <0x00793000 0x1000>;
607 reg = <0x01008000 0x78000>;
613 reg = <0x010ac000 0x4>;
618 reg = <0x01500000 0x10000>;
624 reg = <0x01626000 0x7090>;
630 reg = <0x016c0000 0x40000>;
673 reg = <0x01704000 0xc100>;
689 reg = <0x01745000 0xa010>;
697 reg = <0x010ae000 0x1000>, /* TM */
698 <0x010ad000 0x1000>; /* SROT */
708 reg = <0x01f40000 0x20000>;
714 reg = <0x01f60000 0x20000>;
719 reg = <0x03100000 0x400000>,
720 <0x03500000 0x400000>,
721 <0x03900000 0x400000>;
725 gpio-ranges = <&tlmm 0 0 114>;
1014 reg = <0x04080000 0x100>, <0x04180000 0x40>;
1018 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1047 qcom,smem-states = <&modem_smp2p_out 0>;
1053 qcom,halt-regs = <&tcsr_regs_1 0x3000 0x5000 0x4000>;
1074 reg = <0x05000000 0x40000>;
1094 iommus = <&kgsl_smmu 0>;
1112 opp-supported-hw = <0xa2>;
1118 opp-supported-hw = <0xff>;
1124 opp-supported-hw = <0xff>;
1130 opp-supported-hw = <0xff>;
1136 opp-supported-hw = <0xff>;
1142 opp-supported-hw = <0xff>;
1148 opp-supported-hw = <0xff>;
1156 reg = <0x05040000 0x10000>;
1196 reg = <0x05065000 0x9038>;
1209 reg = <0x05100000 0x40000>;
1240 reg = <0x00290000 0x10000>;
1245 reg = <0x0800f000 0x1000>,
1246 <0x08400000 0x1000000>,
1247 <0x09400000 0x1000000>,
1248 <0x0a400000 0x220000>,
1249 <0x0800a000 0x3000>;
1253 qcom,ee = <0>;
1254 qcom,channel = <0>;
1256 #size-cells = <0>;
1263 reg = <0x0a8f8800 0x400>;
1295 reg = <0x0a800000 0xc8d0>;
1307 snps,hird-threshold = /bits/ 8 <0>;
1313 reg = <0x0c012000 0x180>;
1314 #phy-cells = <0>;
1327 reg = <0x0c014000 0x180>;
1328 #phy-cells = <0>;
1341 reg = <0x0c084000 0x1000>;
1357 <&gnoc 0 &cnoc 28>;
1362 pinctrl-0 = <&sdc2_state_on>;
1394 reg = <0x0c0c4000 0x1000>,
1395 <0x0c0c5000 0x1000>,
1396 <0x0c0c8000 0x8000>;
1410 <&gnoc 0 &cnoc 27>;
1414 pinctrl-0 = <&sdc1_state_on>;
1449 reg = <0x0c2f8800 0x400>;
1475 reg = <0x0c200000 0xc8d0>;
1484 snps,hird-threshold = /bits/ 8 <0>;
1490 reg = <0x0c8c0000 0x40000>;
1509 <&mdss_dsi0_phy 0>,
1510 <0>,
1511 <0>,
1512 <0>,
1513 <0>;
1518 reg = <0x0c900000 0x1000>,
1519 <0x0c9b0000 0x1040>;
1545 reg = <0x0c901000 0x89000>;
1549 interrupts = <0>;
1566 <&gnoc 0 &mnoc 17>;
1570 iommus = <&mmss_smmu 0>;
1576 #size-cells = <0>;
1578 port@0 {
1579 reg = <0>;
1620 reg = <0x0c994000 0x400>;
1631 assigned-clock-parents = <&mdss_dsi0_phy 0>,
1659 #size-cells = <0>;
1661 port@0 {
1662 reg = <0>;
1678 reg = <0x0c994400 0x100>,
1679 <0x0c994500 0x300>,
1680 <0x0c994800 0x188>;
1686 #phy-cells = <0>;
1696 reg = <0x0c144000 0x1f000>;
1701 qcom,ee = <0>;
1709 reg = <0x0c16f000 0x200>;
1714 dmas = <&blsp1_dma 0>, <&blsp1_dma 1>;
1717 pinctrl-0 = <&blsp1_uart1_default>;
1724 reg = <0x0c170000 0x1000>;
1732 pinctrl-0 = <&blsp1_uart2_default>;
1738 reg = <0x0c175000 0x600>;
1749 pinctrl-0 = <&i2c1_default>;
1752 #size-cells = <0>;
1758 reg = <0x0c176000 0x600>;
1769 pinctrl-0 = <&i2c2_default>;
1772 #size-cells = <0>;
1778 reg = <0x0c177000 0x600>;
1789 pinctrl-0 = <&i2c3_default>;
1792 #size-cells = <0>;
1798 reg = <0x0c178000 0x600>;
1809 pinctrl-0 = <&i2c4_default>;
1812 #size-cells = <0>;
1818 reg = <0x0c184000 0x1f000>;
1823 qcom,ee = <0>;
1831 reg = <0x0c1af000 0x200>;
1836 dmas = <&blsp2_dma 0>, <&blsp2_dma 1>;
1839 pinctrl-0 = <&blsp2_uart1_default>;
1846 reg = <0x0c1b5000 0x600>;
1857 pinctrl-0 = <&i2c5_default>;
1860 #size-cells = <0>;
1866 reg = <0x0c1b6000 0x600>;
1877 pinctrl-0 = <&i2c6_default>;
1880 #size-cells = <0>;
1886 reg = <0x0c1b7000 0x600>;
1897 pinctrl-0 = <&i2c7_default>;
1900 #size-cells = <0>;
1906 reg = <0x0c1b8000 0x600>;
1917 pinctrl-0 = <&i2c8_default>;
1920 #size-cells = <0>;
1926 reg = <0x146bf000 0x1000>;
1931 ranges = <0 0x146bf000 0x1000>;
1935 reg = <0x94c 0xc8>;
1941 reg = <0x0ca00020 0x10>,
1942 <0x0ca30000 0x100>,
1943 <0x0ca30400 0x100>,
1944 <0x0ca30800 0x100>,
1945 <0x0ca30c00 0x100>,
1946 <0x0c824000 0x1000>,
1947 <0x0ca00120 0x4>,
1948 <0x0c825000 0x1000>,
1949 <0x0ca00124 0x4>,
1950 <0x0c826000 0x1000>,
1951 <0x0ca00128 0x4>,
1952 <0x0ca31000 0x500>,
1953 <0x0ca10000 0x1000>,
1954 <0x0ca14000 0x1000>;
2075 iommus = <&mmss_smmu 0xc00>,
2076 <&mmss_smmu 0xc01>,
2077 <&mmss_smmu 0xc02>,
2078 <&mmss_smmu 0xc03>;
2085 #size-cells = <0>;
2092 #size-cells = <0>;
2093 reg = <0x0ca0c000 0x1000>;
2109 pinctrl-0 = <&cci0_default &cci1_default>;
2113 cci_i2c0: i2c-bus@0 {
2114 reg = <0>;
2117 #size-cells = <0>;
2124 #size-cells = <0>;
2130 reg = <0x0cc00000 0xff000>;
2136 interconnects = <&gnoc 0 &mnoc 13>,
2140 iommus = <&mmss_smmu 0x400>,
2141 <&mmss_smmu 0x401>,
2142 <&mmss_smmu 0x40a>,
2143 <&mmss_smmu 0x407>,
2144 <&mmss_smmu 0x40e>,
2145 <&mmss_smmu 0x40f>,
2146 <&mmss_smmu 0x408>,
2147 <&mmss_smmu 0x409>,
2148 <&mmss_smmu 0x40b>,
2149 <&mmss_smmu 0x40c>,
2150 <&mmss_smmu 0x40d>,
2151 <&mmss_smmu 0x410>,
2152 <&mmss_smmu 0x421>,
2153 <&mmss_smmu 0x428>,
2154 <&mmss_smmu 0x429>,
2155 <&mmss_smmu 0x42b>,
2156 <&mmss_smmu 0x42c>,
2157 <&mmss_smmu 0x42d>,
2158 <&mmss_smmu 0x411>,
2159 <&mmss_smmu 0x431>;
2181 reg = <0x0cd00000 0x40000>;
2225 reg = <0x15700000 0x4040>;
2229 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2243 qcom,smem-states = <&adsp_smp2p_out 0>;
2258 #size-cells = <0>;
2271 #size-cells = <0>;
2282 #size-cells = <0>;
2293 #sound-dai-cells = <0>;
2302 reg = <0x17900000 0xe000>;
2309 reg = <0x17911000 0x1000>;
2319 reg = <0x17920000 0x1000>;
2323 frame-number = <0>;
2326 reg = <0x17921000 0x1000>,
2327 <0x17922000 0x1000>;
2333 reg = <0x17923000 0x1000>;
2340 reg = <0x17924000 0x1000>;
2347 reg = <0x17925000 0x1000>;
2354 reg = <0x17926000 0x1000>;
2361 reg = <0x17927000 0x1000>;
2368 reg = <0x17928000 0x1000>;
2375 reg = <0x17a00000 0x10000>, /* GICD */
2376 <0x17b00000 0x100000>; /* GICR * 8 */
2383 redistributor-stride = <0x0 0x20000>;
2396 thermal-sensors = <&tsens 0>;
2566 interrupts = <GIC_PPI 1 0xf08>,
2567 <GIC_PPI 2 0xf08>,
2568 <GIC_PPI 3 0xf08>,
2569 <GIC_PPI 0 0xf08>;