1//===-- ARMSystemRegister.td - ARM Register defs -------------*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8 9include "llvm/TableGen/SearchableTable.td" 10 11//===----------------------------------------------------------------------===// 12// Declarations that describe the ARM system-registers 13//===----------------------------------------------------------------------===// 14 15// M-Class System Registers. 16// 'Mask' bits create unique keys for searches. 17// 18class MClassSysReg<bits<1> UniqMask1, 19 bits<1> UniqMask2, 20 bits<1> UniqMask3, 21 bits<12> Enc12, 22 string name> : SearchableTable { 23 let SearchableFields = ["Name", "M1Encoding12", "M2M3Encoding8", "Encoding"]; 24 string Name; 25 bits<13> M1Encoding12; 26 bits<10> M2M3Encoding8; 27 bits<12> Encoding; 28 29 let Name = name; 30 let EnumValueField = "M1Encoding12"; 31 let EnumValueField = "M2M3Encoding8"; 32 let EnumValueField = "Encoding"; 33 34 let M1Encoding12{12} = UniqMask1; 35 let M1Encoding12{11-00} = Enc12; 36 let Encoding = Enc12; 37 38 let M2M3Encoding8{9} = UniqMask2; 39 let M2M3Encoding8{8} = UniqMask3; 40 let M2M3Encoding8{7-0} = Enc12{7-0}; 41 code Requires = [{ {} }]; 42} 43 44// [|i|e|x]apsr_nzcvq has alias [|i|e|x]apsr. 45// Mask1 Mask2 Mask3 Enc12, Name 46let Requires = [{ {ARM::FeatureDSP} }] in { 47def : MClassSysReg<0, 0, 0, 0x400, "apsr_g">; 48def : MClassSysReg<0, 1, 1, 0xc00, "apsr_nzcvqg">; 49def : MClassSysReg<0, 0, 0, 0x401, "iapsr_g">; 50def : MClassSysReg<0, 1, 1, 0xc01, "iapsr_nzcvqg">; 51def : MClassSysReg<0, 0, 0, 0x402, "eapsr_g">; 52def : MClassSysReg<0, 1, 1, 0xc02, "eapsr_nzcvqg">; 53def : MClassSysReg<0, 0, 0, 0x403, "xpsr_g">; 54def : MClassSysReg<0, 1, 1, 0xc03, "xpsr_nzcvqg">; 55} 56 57def : MClassSysReg<0, 0, 1, 0x800, "apsr">; 58def : MClassSysReg<1, 1, 0, 0x800, "apsr_nzcvq">; 59def : MClassSysReg<0, 0, 1, 0x801, "iapsr">; 60def : MClassSysReg<1, 1, 0, 0x801, "iapsr_nzcvq">; 61def : MClassSysReg<0, 0, 1, 0x802, "eapsr">; 62def : MClassSysReg<1, 1, 0, 0x802, "eapsr_nzcvq">; 63def : MClassSysReg<0, 0, 1, 0x803, "xpsr">; 64def : MClassSysReg<1, 1, 0, 0x803, "xpsr_nzcvq">; 65 66def : MClassSysReg<0, 0, 1, 0x805, "ipsr">; 67def : MClassSysReg<0, 0, 1, 0x806, "epsr">; 68def : MClassSysReg<0, 0, 1, 0x807, "iepsr">; 69def : MClassSysReg<0, 0, 1, 0x808, "msp">; 70def : MClassSysReg<0, 0, 1, 0x809, "psp">; 71 72let Requires = [{ {ARM::HasV8MBaselineOps} }] in { 73def : MClassSysReg<0, 0, 1, 0x80a, "msplim">; 74def : MClassSysReg<0, 0, 1, 0x80b, "psplim">; 75} 76 77def : MClassSysReg<0, 0, 1, 0x810, "primask">; 78 79let Requires = [{ {ARM::HasV7Ops} }] in { 80def : MClassSysReg<0, 0, 1, 0x811, "basepri">; 81def : MClassSysReg<0, 0, 1, 0x812, "basepri_max">; 82def : MClassSysReg<0, 0, 1, 0x813, "faultmask">; 83} 84 85def : MClassSysReg<0, 0, 1, 0x814, "control">; 86 87let Requires = [{ {ARM::Feature8MSecExt} }] in { 88def : MClassSysReg<0, 0, 1, 0x888, "msp_ns">; 89def : MClassSysReg<0, 0, 1, 0x889, "psp_ns">; 90} 91 92let Requires = [{ {ARM::Feature8MSecExt, ARM::HasV8MBaselineOps} }] in { 93def : MClassSysReg<0, 0, 1, 0x88a, "msplim_ns">; 94def : MClassSysReg<0, 0, 1, 0x88b, "psplim_ns">; 95} 96 97def : MClassSysReg<0, 0, 1, 0x890, "primask_ns">; 98 99let Requires = [{ {ARM::Feature8MSecExt, ARM::HasV7Ops} }] in { 100def : MClassSysReg<0, 0, 1, 0x891, "basepri_ns">; 101def : MClassSysReg<0, 0, 1, 0x893, "faultmask_ns">; 102} 103 104let Requires = [{ {ARM::Feature8MSecExt} }] in { 105def : MClassSysReg<0, 0, 1, 0x894, "control_ns">; 106def : MClassSysReg<0, 0, 1, 0x898, "sp_ns">; 107} 108 109let Requires = [{ {ARM::FeaturePACBTI} }] in { 110def : MClassSysReg<0, 0, 1, 0x820, "pac_key_p_0">; 111def : MClassSysReg<0, 0, 1, 0x821, "pac_key_p_1">; 112def : MClassSysReg<0, 0, 1, 0x822, "pac_key_p_2">; 113def : MClassSysReg<0, 0, 1, 0x823, "pac_key_p_3">; 114def : MClassSysReg<0, 0, 1, 0x824, "pac_key_u_0">; 115def : MClassSysReg<0, 0, 1, 0x825, "pac_key_u_1">; 116def : MClassSysReg<0, 0, 1, 0x826, "pac_key_u_2">; 117def : MClassSysReg<0, 0, 1, 0x827, "pac_key_u_3">; 118def : MClassSysReg<0, 0, 1, 0x8a0, "pac_key_p_0_ns">; 119def : MClassSysReg<0, 0, 1, 0x8a1, "pac_key_p_1_ns">; 120def : MClassSysReg<0, 0, 1, 0x8a2, "pac_key_p_2_ns">; 121def : MClassSysReg<0, 0, 1, 0x8a3, "pac_key_p_3_ns">; 122def : MClassSysReg<0, 0, 1, 0x8a4, "pac_key_u_0_ns">; 123def : MClassSysReg<0, 0, 1, 0x8a5, "pac_key_u_1_ns">; 124def : MClassSysReg<0, 0, 1, 0x8a6, "pac_key_u_2_ns">; 125def : MClassSysReg<0, 0, 1, 0x8a7, "pac_key_u_3_ns">; 126} 127 128// Banked Registers 129// 130class BankedReg<string name, bits<8> enc> 131 : SearchableTable { 132 string Name; 133 bits<8> Encoding; 134 let Name = name; 135 let Encoding = enc; 136 let SearchableFields = ["Name", "Encoding"]; 137} 138 139// The values here come from B9.2.3 of the ARM ARM, where bits 4-0 are SysM 140// and bit 5 is R. 141def : BankedReg<"r8_usr", 0x00>; 142def : BankedReg<"r9_usr", 0x01>; 143def : BankedReg<"r10_usr", 0x02>; 144def : BankedReg<"r11_usr", 0x03>; 145def : BankedReg<"r12_usr", 0x04>; 146def : BankedReg<"sp_usr", 0x05>; 147def : BankedReg<"lr_usr", 0x06>; 148def : BankedReg<"r8_fiq", 0x08>; 149def : BankedReg<"r9_fiq", 0x09>; 150def : BankedReg<"r10_fiq", 0x0a>; 151def : BankedReg<"r11_fiq", 0x0b>; 152def : BankedReg<"r12_fiq", 0x0c>; 153def : BankedReg<"sp_fiq", 0x0d>; 154def : BankedReg<"lr_fiq", 0x0e>; 155def : BankedReg<"lr_irq", 0x10>; 156def : BankedReg<"sp_irq", 0x11>; 157def : BankedReg<"lr_svc", 0x12>; 158def : BankedReg<"sp_svc", 0x13>; 159def : BankedReg<"lr_abt", 0x14>; 160def : BankedReg<"sp_abt", 0x15>; 161def : BankedReg<"lr_und", 0x16>; 162def : BankedReg<"sp_und", 0x17>; 163def : BankedReg<"lr_mon", 0x1c>; 164def : BankedReg<"sp_mon", 0x1d>; 165def : BankedReg<"elr_hyp", 0x1e>; 166def : BankedReg<"sp_hyp", 0x1f>; 167def : BankedReg<"spsr_fiq", 0x2e>; 168def : BankedReg<"spsr_irq", 0x30>; 169def : BankedReg<"spsr_svc", 0x32>; 170def : BankedReg<"spsr_abt", 0x34>; 171def : BankedReg<"spsr_und", 0x36>; 172def : BankedReg<"spsr_mon", 0x3c>; 173def : BankedReg<"spsr_hyp", 0x3e>; 174